llvm-6502/lib/CodeGen
Jakob Stoklund Olesen dbc372f47e Link to the live DomainValue after merging.
When merging two uncollapsed DomainValues, place a link to the active
DomainValue from the passive DomainValue.  This allows old stale
references to the passive DomainValue to be updated to point to the
active DomainValue.

The new resolve() function finds the active DomainValue and updates the
pointer.

This change makes old live-out lists more useful since they may contain
uncollapsed DomainValues that have since been merged into other
DomainValues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144149 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09 00:06:18 +00:00
..
AsmPrinter Also add the linkage name to the name accelerator tables if it exists 2011-11-08 21:56:23 +00:00
SelectionDAG Add a hack to the scheduler to disable pseudo-two-address dependencies in 2011-11-08 21:29:06 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
AntiDepBreaker.h
BranchFolding.cpp Reapply r142920 with fix: 2011-10-26 01:10:25 +00:00
BranchFolding.h When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). 2011-07-06 23:41:48 +00:00
CalcSpillWeights.cpp Move CalculateRegClass to MRI::recomputeRegClass. 2011-08-09 16:46:27 +00:00
CallingConvLower.cpp
CMakeLists.txt Implement a block placement pass based on the branch probability and 2011-10-21 06:46:38 +00:00
CodeGen.cpp Begin collecting some of the statistics for block placement discussed on 2011-11-02 07:17:12 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp This code is dead, what with the new EH model and the auto-upgraders in place. 2011-11-07 23:36:48 +00:00
EdgeBundles.cpp
ELF.h
ELFCodeEmitter.cpp Fix asserts in CodeGen from: 2011-09-10 01:07:54 +00:00
ELFCodeEmitter.h Fix asserts in CodeGen from: 2011-09-10 01:07:54 +00:00
ELFWriter.cpp Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. 2011-07-20 19:50:42 +00:00
ELFWriter.h
ExecutionDepsFix.cpp Link to the live DomainValue after merging. 2011-11-09 00:06:18 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp Give targets a chance to expand even standard pseudos. 2011-10-10 20:34:28 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp Added missing &. Fixes <rdar://problem/10393723> 2011-11-04 23:49:14 +00:00
InlineSpiller.cpp Add value numbers when spilling dead defs. 2011-10-14 00:34:31 +00:00
InterferenceCache.cpp Allow null interference cursors to be queried. 2011-07-23 03:10:17 +00:00
InterferenceCache.h Allow null interference cursors to be queried. 2011-07-23 03:10:17 +00:00
IntrinsicLowering.cpp land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
LatencyPriorityQueue.cpp
LexicalScopes.cpp Don't forget to reconstruct D after changing the scope that we're 2011-10-13 21:43:44 +00:00
LiveDebugVariables.cpp Namespacify. 2011-09-16 00:35:06 +00:00
LiveDebugVariables.h
LiveInterval.cpp Leave hasPHIKill flags alone in LiveInterval::RenumberValues. 2011-09-15 04:37:18 +00:00
LiveIntervalAnalysis.cpp Add a FIXME. 2011-10-05 16:51:21 +00:00
LiveIntervalUnion.cpp Simplify the interference checking code a bit. 2011-08-12 00:22:04 +00:00
LiveIntervalUnion.h Simplify the interference checking code a bit. 2011-08-12 00:22:04 +00:00
LiveRangeCalc.cpp Switch extendInBlock() to take a kill slot instead of the last use slot. 2011-09-13 16:47:56 +00:00
LiveRangeCalc.h Unbreak msvc. 2011-09-13 03:58:34 +00:00
LiveRangeEdit.cpp Move CalculateRegClass to MRI::recomputeRegClass. 2011-08-09 16:46:27 +00:00
LiveRangeEdit.h Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used. 2011-07-18 12:00:32 +00:00
LiveStackAnalysis.cpp Move getCommonSubClass() into TRI. 2011-09-30 22:18:51 +00:00
LiveVariables.cpp Silence a bunch (but not all) "variable written but not read" warnings 2011-08-12 14:54:45 +00:00
LLVMBuild.txt build: Add initial cut at LLVMBuild.txt files. 2011-11-03 18:53:17 +00:00
LLVMTargetMachine.cpp Begin collecting some of the statistics for block placement discussed on 2011-11-02 07:17:12 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp Update live-in lists when splitting critical edges. 2011-10-14 17:25:46 +00:00
MachineBlockFrequencyInfo.cpp Add more constantness in BlockFrequencyInfo. 2011-08-03 21:30:57 +00:00
MachineBlockPlacement.cpp Begin collecting some of the statistics for block placement discussed on 2011-11-02 07:17:12 +00:00
MachineBranchProbabilityInfo.cpp Use BranchProbability compare operators. 2011-10-28 11:14:31 +00:00
MachineCSE.cpp We need to verify that the machine instruction we're using as a replacement for 2011-10-12 23:03:40 +00:00
MachineDominators.cpp
MachineFunction.cpp land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Added invariant field to the DAG.getLoad method and changed all calls. 2011-11-08 18:42:53 +00:00
MachineLICM.cpp Disable LICM speculation in high register pressure situation again now that Devang has fixed other issues. 2011-10-26 01:26:57 +00:00
MachineLoopInfo.cpp
MachineLoopRanges.cpp
MachineModuleInfo.cpp Add an ivar that maps a landing pad's EH symbol to the call sites that may jump 2011-10-05 22:20:38 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Also inflate register classes around inline asm. 2011-10-12 23:37:40 +00:00
MachineSink.cpp While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor. 2011-09-07 00:07:58 +00:00
MachineSSAUpdater.cpp
MachineVerifier.cpp Fix sub-register operand verification. 2011-10-05 22:12:57 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizePHIs.cpp When deleting a phi cycle after looking through copies, constrain the register 2011-10-17 21:54:46 +00:00
Passes.cpp
PeepholeOptimizer.cpp If MI is deleted then remove it from the set. If a new MI is created, it could 2011-10-13 02:16:18 +00:00
PHIElimination.cpp Add an isSSA() flag to MachineRegisterInfo. 2011-07-29 22:51:22 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp
ProcessImplicitDefs.cpp Handle REG_SEQUENCE with implicitly defined operands. 2011-07-28 21:38:51 +00:00
PrologEpilogInserter.cpp A few 80-col violations. 2011-10-14 20:36:23 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.h
RegAllocBasic.cpp Privatize an unused part of the LiveIntervalUnion::Query interface. 2011-08-11 21:00:42 +00:00
RegAllocFast.cpp
RegAllocGreedy.cpp Update split candidate correctly when interference cache is full. 2011-11-01 00:02:31 +00:00
RegAllocLinearScan.cpp Refer to the RegisterCoalescer pass by ID. 2011-08-09 00:29:53 +00:00
RegAllocPBQP.cpp Refer to the RegisterCoalescer pass by ID. 2011-08-09 00:29:53 +00:00
RegisterClassInfo.cpp Detect proper register sub-classes. 2011-08-05 21:28:14 +00:00
RegisterClassInfo.h Detect proper register sub-classes. 2011-08-05 21:28:14 +00:00
RegisterCoalescer.cpp Remove unused DstSubIdx argument. 2011-10-05 21:22:53 +00:00
RegisterCoalescer.h Rename member variables to follow coding standards. 2011-08-09 01:01:27 +00:00
RegisterScavenging.cpp Silence a bunch (but not all) "variable written but not read" warnings 2011-08-12 14:54:45 +00:00
RenderMachineFunction.cpp
RenderMachineFunction.h
ScheduleDAG.cpp Make a bunch of symbols private. 2011-08-19 01:42:18 +00:00
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp PostRA scheduler fix. Clear stale loop dependencies. 2011-10-07 06:33:09 +00:00
ScheduleDAGInstrs.h PostRA scheduler fix. Clear stale loop dependencies. 2011-10-07 06:33:09 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp Remove an invalid assert that is really just asserting when the scheduler emits 2011-09-27 21:59:16 +00:00
ShadowStackGC.cpp Use the C personality function instead of the C++ personality function. 2011-09-22 17:56:40 +00:00
ShrinkWrapping.cpp
SjLjEHPrepare.cpp Cleanup. Get rid of the old SjLj EH lowering code. No functionality change. 2011-10-24 17:12:36 +00:00
SlotIndexes.cpp
Spiller.cpp
Spiller.h
SpillPlacement.cpp Be more conservative when forming compact regions. 2011-08-03 23:09:38 +00:00
SpillPlacement.h Be more conservative when forming compact regions. 2011-08-03 23:09:38 +00:00
SplitKit.cpp Spill mode: Hoist back-copies locally. 2011-09-16 00:03:35 +00:00
SplitKit.h Hoist back-copies to the least busy dominator. 2011-09-14 16:45:39 +00:00
Splitter.cpp Refer to the RegisterCoalescer pass by ID. 2011-08-09 00:29:53 +00:00
Splitter.h
StackProtector.cpp land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
StackSlotColoring.cpp
StrongPHIElimination.cpp Use an existing method. 2011-10-13 07:36:41 +00:00
TailDuplication.cpp Trim an unneeded header. 2011-08-09 23:49:21 +00:00
TargetInstrInfoImpl.cpp Permit remat of partial register defs when it is safe. 2011-09-01 18:27:51 +00:00
TargetLoweringObjectFileImpl.cpp Check the visibility of the global variable before placing it into the stubs 2011-10-24 23:05:43 +00:00
TwoAddressInstructionPass.cpp PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that. 2011-09-23 22:41:57 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Also add <imp-use,kill> flags for redefined super-registers. 2011-10-05 00:01:48 +00:00
VirtRegMap.h Be more aggressive about following hints. 2011-07-08 20:46:18 +00:00
VirtRegRewriter.cpp
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.