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dfd0e7bc34
llvm-6502/lib/Target/PowerPC
History
Nate Begeman dfd0e7bc34 Eliminate usage of MRegisterInfo::getRegClass(physreg) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17240 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-26 05:40:45 +00:00
..
LICENSE.TXT Added Louis Gerbarg. Louis is given credit in the CREDITS.TXT file, so I 2004-08-05 23:46:27 +00:00
Makefile Remove extraneous blank line 2004-10-23 04:59:22 +00:00
PowerPC.td PowerPC instruction definitions use LittleEndian-style encoding [0..31] 2004-10-14 05:54:38 +00:00
PowerPCInstrInfo.h The PowerPCInstrInfo class has gone away. 2004-08-17 05:00:46 +00:00
PowerPCRegisterInfo.h PowerPCRegisterInfo no longer takes a bool to differentiate 32 vs 64 bits 2004-08-17 05:02:18 +00:00
PowerPCTargetMachine.h All PPC instructions are now auto-printed 2004-09-04 05:00:00 +00:00
PPC32.td PowerPC instruction definitions use LittleEndian-style encoding [0..31] 2004-10-14 05:54:38 +00:00
PPC32ISelSimple.cpp Fix treecc. Also fix a latent bug in emitBinaryConstOperation that would 2004-10-26 03:48:25 +00:00
PPC32JITInfo.h Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer. 2004-08-11 07:40:04 +00:00
PPC32RegisterInfo.td Switch from bytes to bits for alignment. 2004-08-21 20:14:40 +00:00
PPC64.td PowerPC instruction definitions use LittleEndian-style encoding [0..31] 2004-10-14 05:54:38 +00:00
PPC64CodeEmitter.cpp Breaking up the PowerPC target into 32- and 64-bit subparts: Part II: 64-bit. 2004-08-11 00:10:41 +00:00
PPC64InstrInfo.cpp PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC 2004-08-17 04:57:37 +00:00
PPC64InstrInfo.h PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC 2004-08-17 04:57:37 +00:00
PPC64ISelSimple.cpp Several fixes and enhancements to the PPC32 backend. 2004-10-07 22:30:03 +00:00
PPC64JITInfo.h Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer. 2004-08-11 07:40:04 +00:00
PPC64RegisterInfo.cpp Eliminate usage of MRegisterInfo::getRegClass(physreg) 2004-10-26 05:40:45 +00:00
PPC64RegisterInfo.h PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC 2004-08-17 04:57:37 +00:00
PPC64RegisterInfo.td Switch from bytes to bits for alignment. 2004-08-21 20:14:40 +00:00
PPC64TargetMachine.h PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC 2004-08-17 04:57:37 +00:00
PPC.h All PPC instructions are now auto-printed 2004-09-04 05:00:00 +00:00
PPCAsmPrinter.cpp Align function arguments in function headers 2004-10-23 04:58:32 +00:00
PPCBranchSelector.cpp Remove unnecessary header include 2004-10-07 22:24:32 +00:00
PPCCodeEmitter.cpp * Correctly handle the MovePCtoLR pseudo-instr with a bl to next instr 2004-10-23 23:47:34 +00:00
PPCFrameInfo.h LR needs to be saved at 16-byte offset on a 64-bit arch 2004-08-19 21:36:14 +00:00
PPCInstrBuilder.h * Wrap long lines (comments and code) 2004-07-07 20:01:36 +00:00
PPCInstrFormats.td DForm_1, particularly used by store instructions, needs the immediate operand to 2004-10-23 06:08:38 +00:00
PPCInstrInfo.cpp Add ori reg, reg, 0 as a move instruction. This can be generated from 2004-10-07 22:26:12 +00:00
PPCInstrInfo.h PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC* 2004-08-17 04:55:41 +00:00
PPCInstrInfo.td Add BA, BL, and BLA opcodes 2004-10-23 20:29:24 +00:00
PPCJITInfo.h Breaking up the PowerPC target into 32- and 64-bit subparts, Part III: the rest. 2004-08-11 00:11:25 +00:00
PPCRegisterInfo.cpp Eliminate usage of MRegisterInfo::getRegClass(physreg) 2004-10-26 05:40:45 +00:00
PPCRegisterInfo.h PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC* 2004-08-17 04:55:41 +00:00
PPCRegisterInfo.td Revamp the Register class, and allow the use of the RegisterGroup class to 2004-09-14 04:17:02 +00:00
PPCTargetMachine.cpp Disable the JIT until it can sorta kinda work. 2004-10-25 20:53:41 +00:00
PPCTargetMachine.h All PPC instructions are now auto-printed 2004-09-04 05:00:00 +00:00
README.txt Update to-do list 2004-10-26 04:10:53 +00:00

README.txt 

TODO:
* implement not-R0 register GPR class
* implement scheduling info
* implement do-loop pass
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* implement powerpc-64 for aix
* use stfiwx in float->int
* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

Currently failing tests that should pass:
* MultiSource
  |- Applications
  |  `- hbd: miscompilation