marqs
3a12592c53
fix linebuf read address timing bottleneck
2019-10-07 01:25:33 +03:00
marqs
9d496383c3
optimize clock network
...
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-06 23:54:32 +03:00
marqs
6266976114
first OSD implementation
2019-10-03 02:03:43 +03:00
borti4938
209130b167
misc updates:
...
- integrate mask and border generation more deeply into the post processing chain
- delay RLPF by one PP stage (reduce logic length after large mux)
- synthesise a registers after several adder logics
2018-03-06 13:08:20 +01:00
paulb-nl
a39888845a
Add 32 step grayramp to test pattern
2018-01-20 22:08:10 +01:00
marqs
a24d6b0e3a
Update latency tester
...
* Enable operation with all sources
* Measure strobe length on low-persistence displays
2017-10-28 12:10:54 +03:00
marqs
1bf279b2a7
Initial latency tester implementation
2017-10-22 22:45:29 +03:00
marqs
4f36278cb7
Sync processing rewritten and some issues fixed
...
* add 480i/576i line3x/4x
* clean up RTL and SDC
* update AVI infoframe properly
* add HDMI IT content option
2017-05-18 23:36:37 +03:00
marqs
d77c293b70
* Clean up some FPGA code
...
* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
2016-12-31 14:18:21 +02:00
marqs
f502b2e46c
Release 0.67.
...
- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
2016-03-27 23:09:31 +03:00
marqs
388c464f63
Initial public release (FW 0.64)
2016-02-23 01:03:50 +02:00
