12 Commits

Author	SHA1	Message	Date
marqs	434186d64e	Improve lo-res mode processing features ... * workaround for phase shift issue on optimized modes * add hscale option for 256x240 opt Line3x mode * distribute video modes to groups and allow passthru for all modes	2017-01-23 00:56:17 +02:00
marqs	d77c293b70	* Clean up some FPGA code ... * Wrap sampling phase setting * Enable hal.enable_lightweight_device_driver_api to reduce CPU code size	2016-12-31 14:18:21 +02:00
marqs	79f215d41e	Minor fixes.	2016-12-27 11:16:08 +02:00
marqs	03bf4c2c9a	Update to Quartus 16.1.	2016-12-13 20:55:10 +02:00
marqs	f55e9a877e	SD SPI implementation finished	2016-10-21 01:19:53 +03:00
marqs	71d60144e8	Timer and SPI added.	2016-10-16 12:53:54 +03:00
marqs	827df7930f	* L3 optimized mode scanlines fixed ... * Advanced timing tweaker implemented	2016-08-16 22:45:23 +03:00
marqs	a488422089	* Fix scanline rendering issues ... * Add initial input and SDTV sync glitch filter settings * Modify input initialization logic * Fix debug build warnings	2016-08-14 18:57:50 +03:00
marqs	c8b542b917	* 480p/576p line2x ... * 480i/576i passthrough * alternating scanlines for interlaced material	2016-07-09 23:12:35 +03:00
marqs	c83653c880	Release 0.69 ... * Improved remote control handling code * Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal * Fixed randomly missing blue channel at power-on when using DVI output mode * Added H-PLL coast options * Finer tuning range for scanline strength and mask	2016-04-15 22:05:53 +03:00
marqs	f502b2e46c	Release 0.67. ... - Code cleanup - Some project files added - PAL linetriple added - FPGA PLL parameters optimized - Reduced jitter on low video clock sources	2016-03-27 23:09:31 +03:00
marqs	388c464f63	Initial public release (FW 0.64)	2016-02-23 01:03:50 +02:00