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mirror of https://github.com/marqs85/ossc.git synced 2024-12-29 09:32:45 +00:00
ossc/rtl
2020-02-09 21:35:50 +02:00
..
char_array.qip osd_generator: add M9K support to allow larger character array 2019-10-05 11:33:59 +03:00
char_array.v osd_generator: add M9K support to allow larger character array 2019-10-05 11:33:59 +03:00
char_rom.qip first OSD implementation 2019-10-03 02:03:43 +03:00
char_rom.v first OSD implementation 2019-10-03 02:03:43 +03:00
ir_rcv.v Improve IR receiver tolerance 2017-01-28 03:37:29 +02:00
lat_tester_includes.v Scanline updates and fixes 2019-03-23 00:09:46 +02:00
lat_tester.v use LEDs for debug in latency tester mode 2020-02-09 21:35:50 +02:00
linebuf.qip update to Quartus 17.1 2017-12-07 21:35:08 +02:00
linebuf.v update to Quartus 17.1 2017-12-07 21:35:08 +02:00
lpm_mult_4_hybr_ref_pre.qip add missing IP files 2018-03-06 09:36:38 +01:00
lpm_mult_4_hybr_ref_pre.v add missing IP files 2018-03-06 09:36:38 +01:00
lpm_mult_4_hybr_ref.qip various post processing pipeline updates: 2018-03-06 09:36:21 +01:00
lpm_mult_4_hybr_ref.v finer granulated steps for hybrid sl settings 2018-03-07 10:21:18 +01:00
lpm_mult_4_sl.qip add missing IP files 2018-03-06 09:33:28 +01:00
lpm_mult_4_sl.v SL Multiplication: 2018-03-06 09:34:12 +01:00
ossc.v use LEDs for debug in latency tester mode 2020-02-09 21:35:50 +02:00
pll_2x.ppf fix PLL reference clock switchover logic 2019-10-09 23:58:55 +03:00
pll_2x.qip update quartus to 19.1 2020-02-09 21:28:24 +02:00
pll_2x.v update quartus to 19.1 2020-02-09 21:28:24 +02:00
pll_config_2x_5x_data.mif optimize clock network 2019-10-06 23:54:32 +03:00
pll_config_3x_4x_data.mif optimize clock network 2019-10-06 23:54:32 +03:00
pll_config_default_data.mif fix PLL reference clock switchover logic 2019-10-09 23:58:55 +03:00
scanconverter.v make pll_reconfig more robust 2019-10-12 22:56:10 +03:00
timescale.v Initial public release (FW 0.64) 2016-02-23 01:03:50 +02:00
videogen.v fix linebuf read address timing bottleneck 2019-10-07 01:25:33 +03:00