10 Commits

Author	SHA1	Message	Date
Alan Garfield	20919fa726	wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok	2018-02-05 00:12:06 +11:00
Alan Garfield	69f1b53e18	added basic rom and fix uart issue on HX	2018-01-28 15:02:51 +11:00
Niels Moseley	ac2d460f92	Added SIM define to run_testbench.bat	2018-01-27 22:32:51 +01:00
Niels Moseley	6823d0e3f9	Added 6502 PC monitoring	2018-01-27 18:11:33 +01:00
Alan Garfield	f081eb674f	added pretend UART RX waveform	2018-01-28 00:21:48 +11:00
Alan Garfield	bcaf9e6962	Yay got iverilog sim working!	2018-01-27 22:13:52 +11:00
Alan Garfield	c4d42fae3c	fixed testbench and split CPU cores	2018-01-27 17:00:33 +11:00
Niels Moseley	5e3f065223	Forced some internal CPU signals at start of simuation to get rid of undefined signals. Also made sure hard_reset signal is never undefined	2018-01-27 01:21:47 +01:00
Niels Moseley	9465e0c14d	Added synchronous reset to clk enable divider to avoid undefined logic state in simulation	2018-01-26 23:41:58 +01:00
Niels Moseley	cca11b7925	Added iverilog simulation support	2018-01-26 23:32:31 +01:00