11 Commits

Author	SHA1	Message	Date
freitz85	7e2414c1bf	AddressDecoder in VHDL	2017-10-10 22:36:48 +02:00
freitz85	74c6b83b4e	Synthesis guards for debug signals	2017-10-10 21:58:22 +02:00
freitz85	2e4ebd9ac0	Test bench worst and best case timings	2017-10-10 21:22:18 +02:00
freitz85	797993500e	Test bench added	2017-10-10 01:35:18 +02:00
freitz85	c03bc37834	Test bench	2017-10-10 00:41:31 +02:00
freitz85	caa40196d7	Removed BUFG constraint warnings	2017-10-09 23:35:52 +02:00
freitz85	b888590d11	Top level in VHDL	2017-10-09 22:35:47 +02:00
freitz85	84cfbdde92	test with clocked input buffers	2017-10-08 21:48:07 +02:00
Florian Reitz	d0a9254893	several fixes tried	2017-10-05 22:57:38 +02:00
freitz85	9c3b1c33ff	Reset inited on card remove	2017-09-10 14:07:23 +02:00
freitz85	04e26f32da	Update to ISE 14.7	2017-09-10 13:41:13 +02:00