mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-25 15:33:32 +00:00
All compiling
This commit is contained in:
Zane Kaminski
parent
065ad56ccc
commit
6457809037
9
CPLD/LCMXO2-1200HC/.run_manager.ini
Normal file
9
CPLD/LCMXO2-1200HC/.run_manager.ini
Normal file
@ -0,0 +1,9 @@
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[Runmanager]
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Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
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||||
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
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headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
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[impl1%3CStrategy1%3E]
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isChecked=false
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isHidden=false
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isExpanded=false
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4
CPLD/LCMXO2-1200HC/.setting.ini
Normal file
4
CPLD/LCMXO2-1200HC/.setting.ini
Normal file
@ -0,0 +1,4 @@
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[General]
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PAR.auto_tasks=PARTrace, IOTiming
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Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile
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Export.auto_tasks=Jedecgen
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17
CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf
Normal file
17
CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf
Normal file
@ -0,0 +1,17 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="RAM2GS_LCMXO2_1200HC" device="LCMXO2-1200HC-4TG100C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
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<Options def_top="RAM2GS"/>
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<Source name="../RAM2GS-SPI.v" type="Verilog" type_short="Verilog">
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<Options top_module="RAM2GS"/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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<Source name="RAM2GS_LCMXO2_1200HC.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="RAM2GS_LCMXO2_640HC1.sty"/>
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</BaliProject>
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68
CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf
Normal file
68
CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf
Normal file
@ -0,0 +1,68 @@
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BLOCK RESETPATHS ;
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BLOCK ASYNCPATHS ;
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LOCATE COMP "CROW[0]" SITE "10" ;
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LOCATE COMP "CROW[1]" SITE "16" ;
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LOCATE COMP "PHI2" SITE "8" ;
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LOCATE COMP "RCLK" SITE "62" ;
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LOCATE COMP "nCCAS" SITE "9" ;
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LOCATE COMP "nCRAS" SITE "17" ;
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LOCATE COMP "Din[0]" SITE "3" ;
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LOCATE COMP "Din[6]" SITE "2" ;
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LOCATE COMP "Din[7]" SITE "1" ;
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LOCATE COMP "Din[4]" SITE "99" ;
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LOCATE COMP "Din[5]" SITE "98" ;
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LOCATE COMP "Din[3]" SITE "97" ;
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LOCATE COMP "Din[1]" SITE "96" ;
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LOCATE COMP "Din[2]" SITE "88" ;
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LOCATE COMP "MAin[0]" SITE "14" ;
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LOCATE COMP "MAin[1]" SITE "12" ;
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LOCATE COMP "MAin[2]" SITE "13" ;
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LOCATE COMP "MAin[3]" SITE "21" ;
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LOCATE COMP "MAin[4]" SITE "20" ;
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LOCATE COMP "MAin[5]" SITE "19" ;
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LOCATE COMP "MAin[6]" SITE "24" ;
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LOCATE COMP "MAin[7]" SITE "18" ;
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LOCATE COMP "MAin[8]" SITE "25" ;
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LOCATE COMP "MAin[9]" SITE "32" ;
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LOCATE COMP "UFMSDO" SITE "27" ;
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LOCATE COMP "nFWE" SITE "28" ;
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LOCATE COMP "Dout[0]" SITE "76" ;
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LOCATE COMP "Dout[1]" SITE "86" ;
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LOCATE COMP "Dout[2]" SITE "87" ;
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LOCATE COMP "Dout[3]" SITE "85" ;
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LOCATE COMP "Dout[4]" SITE "83" ;
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LOCATE COMP "Dout[5]" SITE "84" ;
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LOCATE COMP "Dout[6]" SITE "78" ;
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LOCATE COMP "Dout[7]" SITE "82" ;
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LOCATE COMP "LED" SITE "34" ;
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LOCATE COMP "RA[0]" SITE "66" ;
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LOCATE COMP "RA[1]" SITE "67" ;
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LOCATE COMP "RA[2]" SITE "69" ;
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LOCATE COMP "RA[3]" SITE "71" ;
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LOCATE COMP "RA[4]" SITE "74" ;
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LOCATE COMP "RA[5]" SITE "70" ;
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LOCATE COMP "RA[6]" SITE "68" ;
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LOCATE COMP "RA[7]" SITE "75" ;
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LOCATE COMP "RA[8]" SITE "65" ;
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LOCATE COMP "RA[9]" SITE "63" ;
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LOCATE COMP "RA[10]" SITE "64" ;
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LOCATE COMP "RA[11]" SITE "59" ;
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LOCATE COMP "RBA[0]" SITE "58" ;
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LOCATE COMP "RBA[1]" SITE "60" ;
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LOCATE COMP "RCKE" SITE "53" ;
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LOCATE COMP "RDQMH" SITE "51" ;
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LOCATE COMP "RDQML" SITE "48" ;
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LOCATE COMP "UFMCLK" SITE "29" ;
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LOCATE COMP "UFMSDI" SITE "30" ;
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LOCATE COMP "nRCAS" SITE "52" ;
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LOCATE COMP "nRCS" SITE "57" ;
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LOCATE COMP "nRRAS" SITE "54" ;
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LOCATE COMP "nRWE" SITE "49" ;
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LOCATE COMP "RD[0]" SITE "36" ;
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LOCATE COMP "RD[1]" SITE "37" ;
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LOCATE COMP "RD[2]" SITE "38" ;
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LOCATE COMP "RD[3]" SITE "39" ;
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LOCATE COMP "RD[4]" SITE "40" ;
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LOCATE COMP "RD[5]" SITE "41" ;
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LOCATE COMP "RD[6]" SITE "42" ;
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LOCATE COMP "RD[7]" SITE "43" ;
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70
CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html
Normal file
70
CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html
Normal file
@ -0,0 +1,70 @@
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<HTML>
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<HEAD><TITLE>Lattice TCL Log</TITLE>
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<STYLE TYPE="text/css">
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<!--
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body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
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-->
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</STYLE>
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</HEAD>
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<PRE><A name="pn230815050136"></A><B><U><big>pn230815050136</big></U></B>
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#Start recording tcl command: 8/15/2023 05:01:06
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#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
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prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
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prj_run Export -impl impl1 -forceAll
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#Stop recording: 8/15/2023 05:01:36
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<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
|
||||
<BR>
|
||||
<BR>
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||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
|
||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
|
||||
<BR>
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||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
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||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
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||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
<BR>
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||||
</PRE></FONT>
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</BODY>
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</HTML>
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@ -0,0 +1,5 @@
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#Start recording tcl command: 8/15/2023 05:01:06
|
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#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
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prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
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prj_run Export -impl impl1 -forceAll
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#Stop recording: 8/15/2023 05:01:36
|
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205
CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty
Normal file
205
CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty
Normal file
@ -0,0 +1,205 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE strategy>
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||||
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
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||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
|
||||
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
62
CPLD/LCMXO2-1200HC/impl1/.build_status
Normal file
62
CPLD/LCMXO2-1200HC/impl1/.build_status
Normal file
@ -0,0 +1,62 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BuildStatus>
|
||||
<Strategy name="Strategy1">
|
||||
<Milestone name="Export" build_result="0" build_time="0">
|
||||
<Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692090225"/>
|
||||
</Milestone>
|
||||
<Milestone name="Map" build_result="2" build_time="1692090207">
|
||||
<Task name="Map" build_result="2" update_result="0" update_time="1692090207"/>
|
||||
<Task name="MapTrace" build_result="2" update_result="0" update_time="1692090208"/>
|
||||
<Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1692090210"/>
|
||||
<Task name="MapVHDLSimFile" build_result="2" update_result="0" update_time="1692090211"/>
|
||||
</Milestone>
|
||||
<Milestone name="PAR" build_result="2" build_time="1692090219">
|
||||
<Task name="PAR" build_result="2" update_result="0" update_time="1692090219"/>
|
||||
<Task name="PARTrace" build_result="2" update_result="0" update_time="1692090220"/>
|
||||
<Task name="IOTiming" build_result="2" update_result="0" update_time="1692090221"/>
|
||||
</Milestone>
|
||||
<Milestone name="Synthesis" build_result="2" build_time="1692090206">
|
||||
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1692090206"/>
|
||||
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1692090225"/>
|
||||
</Milestone>
|
||||
<Milestone name="TOOL_Report" build_result="0" build_time="0">
|
||||
<Task name="HDLE" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="BKM" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Report name=".vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb" last_build_time="1692090207" last_build_size="70832"/>
|
||||
<Report name=".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" last_build_time="1692089743" last_build_size="67964"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1.bgn" last_build_time="1692090225" last_build_size="4432"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1.ior" last_build_time="1692090221" last_build_size="6877"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1.jed" last_build_time="1692090225" last_build_size="351905"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1.lsedata" last_build_time="1692090205" last_build_size="237766"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1.ncd" last_build_time="1692090219" last_build_size="197895"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1.ngd" last_build_time="1692090206" last_build_size="156243"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1.tw1" last_build_time="1692090208" last_build_size="14613"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1.twr" last_build_time="1692090220" last_build_size="88214"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1_map.ncd" last_build_time="1692090207" last_build_size="140118"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf" last_build_time="1692090211" last_build_size="118434"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho" last_build_time="1692090211" last_build_size="973593"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf" last_build_time="1692090210" last_build_size="117902"/>
|
||||
<Report name="RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo" last_build_time="1692090210" last_build_size="127959"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.bgn" last_build_time="1692089755" last_build_size="4349"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ior" last_build_time="1692089751" last_build_size="6793"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.jed" last_build_time="1692089755" last_build_size="177183"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.lsedata" last_build_time="1692089741" last_build_size="237766"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ncd" last_build_time="1692089750" last_build_size="194841"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ngd" last_build_time="1692089742" last_build_size="156242"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.tw1" last_build_time="1692089743" last_build_size="14448"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.twr" last_build_time="1692089750" last_build_size="88131"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_map.ncd" last_build_time="1692089742" last_build_size="137575"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf" last_build_time="1692089745" last_build_size="118434"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvho.vho" last_build_time="1692089744" last_build_size="973515"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf" last_build_time="1692089744" last_build_size="117902"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvo.vo" last_build_time="1692089744" last_build_size="127881"/>
|
||||
</Strategy>
|
||||
</BuildStatus>
|
||||
Binary file not shown.
BIN
CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_rtl.vdb
Normal file
BIN
CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_rtl.vdb
Normal file
Binary file not shown.
BIN
CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_tech.vdb
Normal file
BIN
CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_tech.vdb
Normal file
Binary file not shown.
1
CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt
Normal file
1
CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt
Normal file
@ -0,0 +1 @@
|
||||
RAM2GS_rtl.vdb
|
||||
75
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt
Normal file
75
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt
Normal file
@ -0,0 +1,75 @@
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Tue Aug 15 05:03:45 2023 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS Dout[7] : 82 : out *
|
||||
NOTE PINS Dout[6] : 78 : out *
|
||||
NOTE PINS Dout[5] : 84 : out *
|
||||
NOTE PINS Dout[4] : 83 : out *
|
||||
NOTE PINS Dout[3] : 85 : out *
|
||||
NOTE PINS Dout[2] : 87 : out *
|
||||
NOTE PINS Dout[1] : 86 : out *
|
||||
NOTE PINS Dout[0] : 76 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS RBA[1] : 60 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 63 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 75 : out *
|
||||
NOTE PINS RA[6] : 68 : out *
|
||||
NOTE PINS RA[5] : 70 : out *
|
||||
NOTE PINS RA[4] : 74 : out *
|
||||
NOTE PINS RA[3] : 71 : out *
|
||||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS nRCS : 57 : out *
|
||||
NOTE PINS RCKE : 53 : out *
|
||||
NOTE PINS nRWE : 49 : out *
|
||||
NOTE PINS nRRAS : 54 : out *
|
||||
NOTE PINS nRCAS : 52 : out *
|
||||
NOTE PINS RDQMH : 51 : out *
|
||||
NOTE PINS RDQML : 48 : out *
|
||||
NOTE PINS nUFMCS : 47 : out *
|
||||
NOTE PINS UFMCLK : 29 : out *
|
||||
NOTE PINS UFMSDI : 30 : out *
|
||||
NOTE PINS PHI2 : 8 : in *
|
||||
NOTE PINS MAin[9] : 32 : in *
|
||||
NOTE PINS MAin[8] : 25 : in *
|
||||
NOTE PINS MAin[7] : 18 : in *
|
||||
NOTE PINS MAin[6] : 24 : in *
|
||||
NOTE PINS MAin[5] : 19 : in *
|
||||
NOTE PINS MAin[4] : 20 : in *
|
||||
NOTE PINS MAin[3] : 21 : in *
|
||||
NOTE PINS MAin[2] : 13 : in *
|
||||
NOTE PINS MAin[1] : 12 : in *
|
||||
NOTE PINS MAin[0] : 14 : in *
|
||||
NOTE PINS CROW[1] : 16 : in *
|
||||
NOTE PINS CROW[0] : 10 : in *
|
||||
NOTE PINS Din[7] : 1 : in *
|
||||
NOTE PINS Din[6] : 2 : in *
|
||||
NOTE PINS Din[5] : 98 : in *
|
||||
NOTE PINS Din[4] : 99 : in *
|
||||
NOTE PINS Din[3] : 97 : in *
|
||||
NOTE PINS Din[2] : 88 : in *
|
||||
NOTE PINS Din[1] : 96 : in *
|
||||
NOTE PINS Din[0] : 3 : in *
|
||||
NOTE PINS nCCAS : 9 : in *
|
||||
NOTE PINS nCRAS : 17 : in *
|
||||
NOTE PINS nFWE : 28 : in *
|
||||
NOTE PINS RCLK : 62 : in *
|
||||
NOTE PINS UFMSDO : 27 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
21
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep
Normal file
21
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep
Normal file
@ -0,0 +1,21 @@
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2GS.TECH
|
||||
Register bits: 102 of 1520 (6.711%)
|
||||
I/O cells: 67
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 10 100.0
|
||||
FD1P3AX 29 100.0
|
||||
FD1P3AY 5 100.0
|
||||
FD1P3IX 3 100.0
|
||||
FD1S3AX 47 100.0
|
||||
FD1S3IX 14 100.0
|
||||
FD1S3JX 4 100.0
|
||||
GSR 1 100.0
|
||||
IB 26 100.0
|
||||
INV 3 100.0
|
||||
LUT4 122 100.0
|
||||
OB 33 100.0
|
||||
PFUMX 1 100.0
|
||||
TOTAL 306
|
||||
86
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn
Normal file
86
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn
Normal file
@ -0,0 +1,86 @@
|
||||
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:42 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 0 Page.
|
||||
|
||||
Total CPU Time: 2 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 253 MB
|
||||
BIN
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd
Normal file
BIN
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd
Normal file
Binary file not shown.
309
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad
Normal file
309
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad
Normal file
@ -0,0 +1,309 @@
|
||||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Tue Aug 15 05:03:35 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS25_IN | PL4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS25_IN | PL8A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS25_IN | PL3A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS25_IN | PT10B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS25_IN | PT12A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS25_IN | PT10A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS25_IN | PT9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS25_IN | PL2D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS25_OUT | PT17D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVCMOS25_OUT | PT12C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVCMOS25_OUT | PT12B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVCMOS25_OUT | PT12D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVCMOS25_OUT | PT15B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVCMOS25_OUT | PT15A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVCMOS25_OUT | PT16C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVCMOS25_OUT | PT15C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| LED | 34/2 | LVCMOS25_OUT | PB9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS25_IN | PL9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS25_IN | PL9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS25_IN | PL8D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS25_IN | PL10C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS25_IN | PL8C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS25_IN | PL10D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS25_IN | PB6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS25_OUT | PR4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS25_OUT | PR8D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS25_OUT | PR4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS25_OUT | PR4A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS25_OUT | PR4B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS25_OUT | PR9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS25_OUT | PR8C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS25_OUT | PR9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS25_OUT | PR10D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS25_OUT | PB20C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS25_BIDI | PB11C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS25_BIDI | PB11D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS25_BIDI | PB11A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS25_BIDI | PB11B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS25_BIDI | PB15A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS25_BIDI | PB15B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS25_BIDI | PB18A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS25_BIDI | PB18B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| UFMCLK | 29/2 | LVCMOS25_OUT | PB6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| UFMSDI | 30/2 | LVCMOS25_OUT | PB6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| UFMSDO | 27/2 | LVCMOS25_IN | PB4C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCCAS | 9/3 | LVCMOS25_IN | PL4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS25_IN | PL8B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 28/2 | LVCMOS25_IN | PB4D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS25_OUT | PR10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS25_OUT | PR9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS25_OUT | PR9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS25_OUT | PB20D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nUFMCS | 47/2 | LVCMOS25_OUT | PB18D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 2.5V |
|
||||
| 1 | 2.5V |
|
||||
| 2 | 2.5V |
|
||||
| 3 | 2.5V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3D | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL4A | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL4B | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | |
|
||||
| 15/3 | unused, PULL:DOWN | | | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL8A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL8B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL8C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL8D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL10C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL10D | | | |
|
||||
| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4C | CSSPIN | | |
|
||||
| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4D | | | |
|
||||
| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB6A | | | |
|
||||
| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB6B | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB11C | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB11D | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB15A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB15B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | nUFMCS | | LVCMOS25_OUT | PB18D | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB20C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT15B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT15A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT10B | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT10A | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT9B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "62";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "UFMCLK" SITE "29";
|
||||
LOCATE COMP "UFMSDI" SITE "30";
|
||||
LOCATE COMP "UFMSDO" SITE "27";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "28";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
LOCATE COMP "nUFMCS" SITE "47";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:38 2023
|
||||
|
||||
301
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par
Normal file
301
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par
Normal file
@ -0,0 +1,301 @@
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Tue Aug 15 05:03:31 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 67+4(JTAG)/108 66% used
|
||||
67+4(JTAG)/80 89% bonded
|
||||
|
||||
SLICE 75/640 11% used
|
||||
|
||||
|
||||
|
||||
Number of Signals: 285
|
||||
Number of Connections: 674
|
||||
WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
|
||||
|
||||
Pin Constraint Summary:
|
||||
66 out of 67 pins locked (98% locked).
|
||||
|
||||
The following 2 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 40)
|
||||
PHI2_c (driver: PHI2, clk load #: 13)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
.
|
||||
Starting Placer Phase 0.
|
||||
..........
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...................
|
||||
Placer score = 143529.
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 143450
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 3 out of 108 (2%)
|
||||
PLL : 0 out of 1 (0%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13
|
||||
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 2 out of 8 (25%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
Edge Clocks:
|
||||
No edge clock selected.
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
67 + 4(JTAG) out of 108 (65.7%) PIO sites used.
|
||||
67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 67; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 2.5V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 2.5V | - |
|
||||
| 2 | 17 / 20 ( 85%) | 2.5V | - |
|
||||
| 3 | 17 / 20 ( 85%) | 2.5V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 4 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 674 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=nCCAS_c loads=6 clock_loads=4
|
||||
|
||||
Completed router resource preassignment. Real time: 7 secs
|
||||
|
||||
Start NBR router at 05:03:38 08/15/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:03:38 08/15/23
|
||||
|
||||
Start NBR section for initial routing at 05:03:38 08/15/23
|
||||
Level 1, iteration 1
|
||||
2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -5.186ns/-468.418ns; real time: 7 secs
|
||||
Level 2, iteration 1
|
||||
11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-377.051ns; real time: 8 secs
|
||||
Level 3, iteration 1
|
||||
20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-373.496ns; real time: 8 secs
|
||||
Level 4, iteration 1
|
||||
11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-386.255ns; real time: 8 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:03:39 08/15/23
|
||||
Level 1, iteration 1
|
||||
7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-379.537ns; real time: 8 secs
|
||||
Level 4, iteration 1
|
||||
9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-380.800ns; real time: 8 secs
|
||||
Level 4, iteration 2
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-390.587ns; real time: 8 secs
|
||||
Level 4, iteration 3
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs
|
||||
Level 4, iteration 4
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs
|
||||
Level 4, iteration 5
|
||||
4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs
|
||||
Level 4, iteration 6
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs
|
||||
Level 4, iteration 7
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs
|
||||
Level 4, iteration 8
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs
|
||||
Level 4, iteration 9
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs
|
||||
Level 4, iteration 10
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs
|
||||
Level 4, iteration 11
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs
|
||||
Level 4, iteration 12
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs
|
||||
Level 4, iteration 13
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs
|
||||
Level 4, iteration 14
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs
|
||||
Level 4, iteration 15
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 16
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 17
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs
|
||||
Level 4, iteration 18
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs
|
||||
Level 4, iteration 19
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 20
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 21
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 22
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 23
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs
|
||||
Level 4, iteration 24
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs
|
||||
Level 4, iteration 25
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs
|
||||
|
||||
Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23
|
||||
Level 4, iteration 1
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-405.830ns; real time: 8 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs
|
||||
|
||||
Start NBR section for re-routing at 05:03:39 08/15/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs
|
||||
|
||||
Start NBR section for post-routing at 05:03:39 08/15/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 254 (37.69%)
|
||||
Estimated worst slack<setup> : -4.650ns
|
||||
Timing score<setup> : 391939
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=nCCAS_c loads=6 clock_loads=4
|
||||
|
||||
Total CPU time 7 secs
|
||||
Total REAL time: 8 secs
|
||||
Completely routed.
|
||||
End of route. 674 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 391939
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = -4.650
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 391.939
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 8 secs
|
||||
Total REAL time to completion: 8 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
@ -0,0 +1,38 @@
|
||||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 2;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 40;
|
||||
; Global primary clock #1
|
||||
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
|
||||
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_1_LOADNUM = 13;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 1;
|
||||
; Global secondary clock #0
|
||||
GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c;
|
||||
GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_SECONDARY_0_LOADNUM = 9;
|
||||
GLOBAL_SECONDARY_0_SIGTYPE = CLK;
|
||||
; I/O Bank 0 Usage
|
||||
BANK_0_USED = 13;
|
||||
BANK_0_AVAIL = 19;
|
||||
BANK_0_VCCIO = 2.5V;
|
||||
BANK_0_VREF1 = NA;
|
||||
; I/O Bank 1 Usage
|
||||
BANK_1_USED = 20;
|
||||
BANK_1_AVAIL = 21;
|
||||
BANK_1_VCCIO = 2.5V;
|
||||
BANK_1_VREF1 = NA;
|
||||
; I/O Bank 2 Usage
|
||||
BANK_2_USED = 17;
|
||||
BANK_2_AVAIL = 20;
|
||||
BANK_2_VCCIO = 2.5V;
|
||||
BANK_2_VREF1 = NA;
|
||||
; I/O Bank 3 Usage
|
||||
BANK_3_USED = 17;
|
||||
BANK_3_AVAIL = 20;
|
||||
BANK_3_VCCIO = 2.5V;
|
||||
BANK_3_VREF1 = NA;
|
||||
@ -0,0 +1,28 @@
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:31 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 -4.650 391939 0.304 0 08 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 8 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
1
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc
Normal file
1
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc
Normal file
@ -0,0 +1 @@
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
2779
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
Normal file
2779
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
Normal file
File diff suppressed because it is too large
Load Diff
4
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log
Normal file
4
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log
Normal file
@ -0,0 +1,4 @@
|
||||
---- MParTrce Tool Log File ----
|
||||
|
||||
==== Par Standard Out ====
|
||||
==== End of Par Standard Out ====
|
||||
4
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf
Normal file
4
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf
Normal file
@ -0,0 +1,4 @@
|
||||
#BLOCK ASYNCPATHS;
|
||||
#BLOCK RESETPATHS;
|
||||
|
||||
#FREQUENCY 200.000000 MHz;
|
||||
6331
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata
Normal file
6331
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata
Normal file
File diff suppressed because it is too large
Load Diff
402
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
Normal file
402
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
Normal file
@ -0,0 +1,402 @@
|
||||
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf D:/O
|
||||
neDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200
|
||||
HC_impl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RA
|
||||
M2GS_LCMXO2_1200HC.lpf -c 0 -gui -msgset
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 08/15/23 05:03:26
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 102 out of 1520 (7%)
|
||||
PFU registers: 102 out of 1280 (8%)
|
||||
PIO registers: 0 out of 240 (0%)
|
||||
Number of SLICEs: 75 out of 640 (12%)
|
||||
SLICEs as Logic/ROM: 75 out of 640 (12%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 10 out of 640 (2%)
|
||||
Number of LUT4s: 143 out of 1280 (11%)
|
||||
Number used as logic LUTs: 123
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : No
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/15/23 05:03:26
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
|
||||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
|
||||
Number of Clock Enables: 14
|
||||
Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
|
||||
Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
|
||||
Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
|
||||
Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
|
||||
Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
|
||||
Net Ready_N_292: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 7
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
|
||||
Net Ready: 7 loads, 7 LSLICEs
|
||||
Net nRWE_N_177: 1 loads, 1 LSLICEs
|
||||
Net C1Submitted_N_237: 2 loads, 2 LSLICEs
|
||||
Net n2366: 2 loads, 2 LSLICEs
|
||||
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net Ready: 18 loads
|
||||
Net InitReady: 15 loads
|
||||
Net RASr2: 15 loads
|
||||
Net nRowColSel_N_35: 13 loads
|
||||
Net nRowColSel: 12 loads
|
||||
Net Din_c_4: 10 loads
|
||||
Net MAin_c_1: 10 loads
|
||||
Net Din_c_5: 9 loads
|
||||
Net MAin_c_0: 9 loads
|
||||
Net Din_c_0: 8 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 0
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
No errors or warnings present.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/15/23 05:03:26
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/15/23 05:03:26
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| RA[3] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nUFMCS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| UFMCLK | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| UFMSDI | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/15/23 05:03:26
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Din[6] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| UFMSDO | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block i2 undriven or does not drive anything - clipped.
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal PHI2_N_120 was merged into signal PHI2_c
|
||||
Signal n1407 was merged into signal nRowColSel_N_34
|
||||
Signal n2380 was merged into signal Ready
|
||||
Signal n1408 was merged into signal nRowColSel_N_35
|
||||
Signal nRWE_N_176 was merged into signal nRWE_N_177
|
||||
Signal GND_net undriven or does not drive anything - clipped.
|
||||
Signal VCC_net undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped.
|
||||
Block i2046 was optimized away.
|
||||
Block i1118_1_lut was optimized away.
|
||||
Block i637_1_lut_rep_31 was optimized away.
|
||||
Block i1119_1_lut was optimized away.
|
||||
Block nRWE_I_50_1_lut was optimized away.
|
||||
Block i1 was optimized away.
|
||||
|
||||
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 41 MB
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/15/23 05:03:26
|
||||
|
||||
Run Time and Memory Usage (cont)
|
||||
--------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
9
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mt
Normal file
9
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mt
Normal file
@ -0,0 +1,9 @@
|
||||
-v
|
||||
1
|
||||
|
||||
|
||||
-gt
|
||||
|
||||
|
||||
-mapchkpnt 0
|
||||
-sethld
|
||||
BIN
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd
Normal file
BIN
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd
Normal file
Binary file not shown.
BIN
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ngd
Normal file
BIN
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ngd
Normal file
Binary file not shown.
9
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t
Normal file
9
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t
Normal file
@ -0,0 +1,9 @@
|
||||
-w
|
||||
-l 5
|
||||
-i 6
|
||||
-n 1
|
||||
-t 1
|
||||
-s 1
|
||||
-c 0
|
||||
-e 0
|
||||
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
|
||||
5
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t
Normal file
5
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t
Normal file
@ -0,0 +1,5 @@
|
||||
-rem
|
||||
-distrce
|
||||
-log "RAM2GS_LCMXO2_1200HC_impl1.log"
|
||||
-o "RAM2GS_LCMXO2_1200HC_impl1.csv"
|
||||
-pr "RAM2GS_LCMXO2_1200HC_impl1.prf"
|
||||
309
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad
Normal file
309
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad
Normal file
@ -0,0 +1,309 @@
|
||||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Tue Aug 15 05:03:35 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS25_IN | PL4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS25_IN | PL8A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS25_IN | PL3A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS25_IN | PT10B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS25_IN | PT12A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS25_IN | PT10A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS25_IN | PT9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS25_IN | PL2D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS25_OUT | PT17D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVCMOS25_OUT | PT12C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVCMOS25_OUT | PT12B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVCMOS25_OUT | PT12D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVCMOS25_OUT | PT15B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVCMOS25_OUT | PT15A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVCMOS25_OUT | PT16C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVCMOS25_OUT | PT15C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| LED | 34/2 | LVCMOS25_OUT | PB9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS25_IN | PL9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS25_IN | PL9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS25_IN | PL8D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS25_IN | PL10C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS25_IN | PL8C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS25_IN | PL10D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS25_IN | PB6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS25_OUT | PR4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS25_OUT | PR8D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS25_OUT | PR4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS25_OUT | PR4A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS25_OUT | PR4B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS25_OUT | PR9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS25_OUT | PR8C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS25_OUT | PR9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS25_OUT | PR10D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS25_OUT | PB20C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS25_BIDI | PB11C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS25_BIDI | PB11D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS25_BIDI | PB11A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS25_BIDI | PB11B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS25_BIDI | PB15A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS25_BIDI | PB15B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS25_BIDI | PB18A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS25_BIDI | PB18B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| UFMCLK | 29/2 | LVCMOS25_OUT | PB6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| UFMSDI | 30/2 | LVCMOS25_OUT | PB6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| UFMSDO | 27/2 | LVCMOS25_IN | PB4C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCCAS | 9/3 | LVCMOS25_IN | PL4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS25_IN | PL8B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 28/2 | LVCMOS25_IN | PB4D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS25_OUT | PR10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS25_OUT | PR9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS25_OUT | PR9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS25_OUT | PB20D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nUFMCS | 47/2 | LVCMOS25_OUT | PB18D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 2.5V |
|
||||
| 1 | 2.5V |
|
||||
| 2 | 2.5V |
|
||||
| 3 | 2.5V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3D | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL4A | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL4B | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | |
|
||||
| 15/3 | unused, PULL:DOWN | | | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL8A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL8B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL8C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL8D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL10C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL10D | | | |
|
||||
| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4C | CSSPIN | | |
|
||||
| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4D | | | |
|
||||
| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB6A | | | |
|
||||
| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB6B | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB11C | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB11D | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB15A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB15B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | nUFMCS | | LVCMOS25_OUT | PB18D | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB20C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT15B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT15A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT10B | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT10A | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT9B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "62";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "UFMCLK" SITE "29";
|
||||
LOCATE COMP "UFMSDI" SITE "30";
|
||||
LOCATE COMP "UFMSDO" SITE "27";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "28";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
LOCATE COMP "nUFMCS" SITE "47";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:38 2023
|
||||
|
||||
329
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par
Normal file
329
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par
Normal file
@ -0,0 +1,329 @@
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:31 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 -4.650 391939 0.304 0 08 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 8 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Tue Aug 15 05:03:31 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 67+4(JTAG)/108 66% used
|
||||
67+4(JTAG)/80 89% bonded
|
||||
|
||||
SLICE 75/640 11% used
|
||||
|
||||
|
||||
|
||||
Number of Signals: 285
|
||||
Number of Connections: 674
|
||||
WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
|
||||
|
||||
Pin Constraint Summary:
|
||||
66 out of 67 pins locked (98% locked).
|
||||
|
||||
The following 2 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 40)
|
||||
PHI2_c (driver: PHI2, clk load #: 13)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
.
|
||||
Starting Placer Phase 0.
|
||||
..........
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...................
|
||||
Placer score = 143529.
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 143450
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 3 out of 108 (2%)
|
||||
PLL : 0 out of 1 (0%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13
|
||||
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 2 out of 8 (25%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
Edge Clocks:
|
||||
No edge clock selected.
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
67 + 4(JTAG) out of 108 (65.7%) PIO sites used.
|
||||
67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 67; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 2.5V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 2.5V | - |
|
||||
| 2 | 17 / 20 ( 85%) | 2.5V | - |
|
||||
| 3 | 17 / 20 ( 85%) | 2.5V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 4 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 674 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=nCCAS_c loads=6 clock_loads=4
|
||||
|
||||
Completed router resource preassignment. Real time: 7 secs
|
||||
|
||||
Start NBR router at 05:03:38 08/15/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:03:38 08/15/23
|
||||
|
||||
Start NBR section for initial routing at 05:03:38 08/15/23
|
||||
Level 1, iteration 1
|
||||
2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -5.186ns/-468.418ns; real time: 7 secs
|
||||
Level 2, iteration 1
|
||||
11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-377.051ns; real time: 8 secs
|
||||
Level 3, iteration 1
|
||||
20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-373.496ns; real time: 8 secs
|
||||
Level 4, iteration 1
|
||||
11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-386.255ns; real time: 8 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:03:39 08/15/23
|
||||
Level 1, iteration 1
|
||||
7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-379.537ns; real time: 8 secs
|
||||
Level 4, iteration 1
|
||||
9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-380.800ns; real time: 8 secs
|
||||
Level 4, iteration 2
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-390.587ns; real time: 8 secs
|
||||
Level 4, iteration 3
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs
|
||||
Level 4, iteration 4
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs
|
||||
Level 4, iteration 5
|
||||
4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs
|
||||
Level 4, iteration 6
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs
|
||||
Level 4, iteration 7
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs
|
||||
Level 4, iteration 8
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs
|
||||
Level 4, iteration 9
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs
|
||||
Level 4, iteration 10
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs
|
||||
Level 4, iteration 11
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs
|
||||
Level 4, iteration 12
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs
|
||||
Level 4, iteration 13
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs
|
||||
Level 4, iteration 14
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs
|
||||
Level 4, iteration 15
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 16
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 17
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs
|
||||
Level 4, iteration 18
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs
|
||||
Level 4, iteration 19
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 20
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 21
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 22
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 23
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs
|
||||
Level 4, iteration 24
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs
|
||||
Level 4, iteration 25
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs
|
||||
|
||||
Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23
|
||||
Level 4, iteration 1
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-405.830ns; real time: 8 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs
|
||||
|
||||
Start NBR section for re-routing at 05:03:39 08/15/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs
|
||||
|
||||
Start NBR section for post-routing at 05:03:39 08/15/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 254 (37.69%)
|
||||
Estimated worst slack<setup> : -4.650ns
|
||||
Timing score<setup> : 391939
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=nCCAS_c loads=6 clock_loads=4
|
||||
|
||||
Total CPU time 7 secs
|
||||
Total REAL time: 8 secs
|
||||
Completely routed.
|
||||
End of route. 674 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 391939
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = -4.650
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 391.939
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 8 secs
|
||||
Total REAL time to completion: 8 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
80
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
Normal file
80
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
Normal file
@ -0,0 +1,80 @@
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:27 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "UFMCLK" SITE "29" ;
|
||||
LOCATE COMP "UFMSDI" SITE "30" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "nFWE" SITE "28" ;
|
||||
LOCATE COMP "RCLK" SITE "62" ;
|
||||
LOCATE COMP "UFMSDO" SITE "27" ;
|
||||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
COMMERCIAL ;
|
||||
|
||||
// No timing preferences found. TRCE invokes auto-generation of timing preferences
|
||||
// Section Autogen
|
||||
FREQUENCY NET "RCLK_c" 299.401 MHz ;
|
||||
FREQUENCY NET "PHI2_c" 99.079 MHz ;
|
||||
// End Section Autogen
|
||||
10
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt
Normal file
10
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt
Normal file
@ -0,0 +1,10 @@
|
||||
-v
|
||||
10
|
||||
|
||||
|
||||
|
||||
|
||||
-gt
|
||||
-sethld
|
||||
-sp 4
|
||||
-sphld m
|
||||
5
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b
Normal file
5
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b
Normal file
@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
-g RamCfg:Reset
|
||||
|
||||
-path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
|
||||
349
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1
Normal file
349
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1
Normal file
@ -0,0 +1,349 @@
|
||||
|
||||
Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Tue Aug 15 05:03:28 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Report Type: based on TRACE automatically generated preferences
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
|
||||
459 items scored, 245 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path exceeds requirements by 3.815ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS_610__i13 (from RCLK_c +)
|
||||
Destination: FF Data in n8MEGEN_418 (to RCLK_c +)
|
||||
|
||||
Delay: 6.873ns (28.2% logic, 71.8% route), 4 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
6.873ns physical path delay SLICE_0 to SLICE_57 exceeds
|
||||
3.340ns delay constraint less
|
||||
0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_0 to SLICE_57:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_0.CLK to SLICE_0.Q0 SLICE_0 (from RCLK_c)
|
||||
ROUTE 3 e 1.234 SLICE_0.Q0 to SLICE_85.B0 FS_13
|
||||
CTOF_DEL --- 0.495 SLICE_85.B0 to SLICE_85.F0 SLICE_85
|
||||
ROUTE 5 e 1.234 SLICE_85.F0 to SLICE_57.A1 n10
|
||||
CTOF_DEL --- 0.495 SLICE_57.A1 to SLICE_57.F1 SLICE_57
|
||||
ROUTE 2 e 1.234 SLICE_57.F1 to SLICE_84.A0 n2367
|
||||
CTOF_DEL --- 0.495 SLICE_84.A0 to SLICE_84.F0 SLICE_84
|
||||
ROUTE 1 e 1.234 SLICE_84.F0 to SLICE_57.CE RCLK_c_enable_15 (to RCLK_c)
|
||||
--------
|
||||
6.873 (28.2% logic, 71.8% route), 4 logic levels.
|
||||
|
||||
Warning: 139.762MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
|
||||
113 items scored, 104 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns)
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_i7 (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable_405 (to PHI2_c -)
|
||||
|
||||
Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.577ns physical path delay SLICE_101 to SLICE_19 exceeds
|
||||
5.047ns delay constraint less
|
||||
0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_101 to SLICE_19:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_101.CLK to SLICE_101.Q1 SLICE_101 (from PHI2_c)
|
||||
ROUTE 1 e 1.234 SLICE_101.Q1 to SLICE_100.C1 Bank_7
|
||||
CTOF_DEL --- 0.495 SLICE_100.C1 to SLICE_100.F1 SLICE_100
|
||||
ROUTE 1 e 1.234 SLICE_100.F1 to SLICE_74.B1 n2277
|
||||
CTOF_DEL --- 0.495 SLICE_74.B1 to SLICE_74.F1 SLICE_74
|
||||
ROUTE 8 e 1.234 SLICE_74.F1 to SLICE_91.B1 n26
|
||||
CTOF_DEL --- 0.495 SLICE_91.B1 to SLICE_91.F1 SLICE_91
|
||||
ROUTE 1 e 1.234 SLICE_91.F1 to SLICE_88.D0 n2362
|
||||
CTOF_DEL --- 0.495 SLICE_88.D0 to SLICE_88.F0 SLICE_88
|
||||
ROUTE 3 e 0.480 SLICE_88.F0 to SLICE_88.C1 C1Submitted_N_237
|
||||
CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88
|
||||
ROUTE 1 e 1.234 SLICE_88.F1 to SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c)
|
||||
--------
|
||||
9.577 (30.6% logic, 69.4% route), 6 logic levels.
|
||||
|
||||
Warning: 50.592MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 139.762 MHz| 4 *
|
||||
| | |
|
||||
FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 50.592 MHz| 6 *
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 preferences(marked by "*" above) not met.
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
Critical Nets | Loads| Errors| % of total
|
||||
----------------------------------------------------------------------------
|
||||
n26 | 8| 78| 22.35%
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40
|
||||
Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
|
||||
Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
Timing summary (Setup):
|
||||
---------------
|
||||
|
||||
Timing errors: 349 Score: 848079
|
||||
Cumulative negative slack: 584487
|
||||
|
||||
Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Tue Aug 15 05:03:28 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
|
||||
459 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.351ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q IS_FSM__i4 (from RCLK_c +)
|
||||
Destination: FF Data in IS_FSM__i5 (to RCLK_c +)
|
||||
|
||||
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.332ns physical path delay SLICE_106 to SLICE_106 meets
|
||||
-0.019ns M_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_106 to SLICE_106:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_106.CLK to SLICE_106.Q0 SLICE_106 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_106.Q0 to SLICE_106.M1 n736 (to RCLK_c)
|
||||
--------
|
||||
0.332 (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
|
||||
113 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q C1Submitted_406 (from PHI2_c -)
|
||||
Destination: FF Data in C1Submitted_406 (to PHI2_c -)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_15 to SLICE_15 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_15 to SLICE_15:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c)
|
||||
ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.C0 C1Submitted
|
||||
CTOF_DEL --- 0.101 SLICE_15.C0 to SLICE_15.F0 SLICE_15
|
||||
ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n1398 (to PHI2_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.351 ns| 1
|
||||
| | |
|
||||
FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.447 ns| 2
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40
|
||||
Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
|
||||
Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
Timing summary (Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup and Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 349 (setup), 0 (hold)
|
||||
Score: 848079 (setup), 0 (hold)
|
||||
Cumulative negative slack: 584487 (584487+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
2163
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr
Normal file
2163
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr
Normal file
File diff suppressed because it is too large
Load Diff
152
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html
Normal file
152
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html
Normal file
@ -0,0 +1,152 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:01:23 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 0 Page.
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 253 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -0,0 +1,204 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>I/O Timing Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2GS
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Tue Aug 15 05:03:41 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 0.891 4 0.676 4
|
||||
CROW[1] nCRAS F 0.281 4 1.216 4
|
||||
Din[0] PHI2 F 7.907 4 0.089 6
|
||||
Din[0] nCCAS F 1.465 4 0.158 4
|
||||
Din[1] PHI2 F 7.300 4 1.026 4
|
||||
Din[1] nCCAS F 1.035 4 0.527 4
|
||||
Din[2] PHI2 F 6.237 4 1.467 4
|
||||
Din[2] nCCAS F 1.719 4 -0.108 M
|
||||
Din[3] PHI2 F 6.623 4 0.176 6
|
||||
Din[3] nCCAS F 0.339 4 0.916 4
|
||||
Din[4] PHI2 F 6.902 4 1.033 4
|
||||
Din[4] nCCAS F 0.687 4 0.951 4
|
||||
Din[5] PHI2 F 6.837 4 1.369 4
|
||||
Din[5] nCCAS F 2.810 4 -0.220 M
|
||||
Din[6] PHI2 F 7.648 4 -0.050 M
|
||||
Din[6] nCCAS F 1.281 4 0.266 4
|
||||
Din[7] PHI2 F 7.823 4 -0.159 M
|
||||
Din[7] nCCAS F 1.810 4 -0.096 M
|
||||
MAin[0] PHI2 F 6.751 4 -0.273 M
|
||||
MAin[0] nCRAS F 1.765 4 -0.033 4
|
||||
MAin[1] PHI2 F 5.718 4 0.117 M
|
||||
MAin[1] nCRAS F 1.814 4 -0.051 M
|
||||
MAin[2] PHI2 F 5.759 4 -0.021 M
|
||||
MAin[2] nCRAS F 1.323 4 0.309 4
|
||||
MAin[3] PHI2 F 6.165 4 -0.235 M
|
||||
MAin[3] nCRAS F 0.694 4 0.836 4
|
||||
MAin[4] PHI2 F 5.236 4 -0.147 M
|
||||
MAin[4] nCRAS F 0.730 4 0.835 4
|
||||
MAin[5] PHI2 F 6.024 4 0.135 M
|
||||
MAin[5] nCRAS F 0.734 4 0.868 4
|
||||
MAin[6] PHI2 F 5.689 4 -0.277 M
|
||||
MAin[6] nCRAS F 0.288 4 1.210 4
|
||||
MAin[7] PHI2 F 6.398 4 -0.307 M
|
||||
MAin[7] nCRAS F 1.215 4 0.401 4
|
||||
MAin[8] nCRAS F 0.817 4 0.727 4
|
||||
MAin[9] nCRAS F 0.941 4 0.601 4
|
||||
PHI2 RCLK R 0.771 4 1.143 4
|
||||
UFMSDO RCLK R -0.238 M 2.305 4
|
||||
nCCAS RCLK R 1.651 4 0.388 4
|
||||
nCCAS nCRAS F 5.028 4 -0.828 M
|
||||
nCRAS RCLK R 0.593 4 1.309 4
|
||||
nFWE PHI2 F 5.741 4 0.781 4
|
||||
nFWE nCRAS F 0.578 4 0.996 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 14.758 4 4.129 M
|
||||
LED nCRAS F 12.396 4 3.434 M
|
||||
RA[0] RCLK R 13.780 4 3.894 M
|
||||
RA[0] nCRAS F 11.795 4 3.277 M
|
||||
RA[10] RCLK R 12.425 4 3.587 M
|
||||
RA[11] PHI2 R 10.432 4 3.084 M
|
||||
RA[1] RCLK R 15.081 4 4.198 M
|
||||
RA[1] nCRAS F 12.364 4 3.447 M
|
||||
RA[2] RCLK R 14.518 4 4.082 M
|
||||
RA[2] nCRAS F 11.696 4 3.275 M
|
||||
RA[3] RCLK R 13.789 4 3.897 M
|
||||
RA[3] nCRAS F 12.223 4 3.392 M
|
||||
RA[4] RCLK R 15.175 4 4.228 M
|
||||
RA[4] nCRAS F 12.424 4 3.464 M
|
||||
RA[5] RCLK R 13.789 4 3.897 M
|
||||
RA[5] nCRAS F 12.359 4 3.437 M
|
||||
RA[6] RCLK R 15.420 4 4.299 M
|
||||
RA[6] nCRAS F 12.865 4 3.560 M
|
||||
RA[7] RCLK R 14.672 4 4.127 M
|
||||
RA[7] nCRAS F 12.253 4 3.386 M
|
||||
RA[8] RCLK R 14.952 4 4.191 M
|
||||
RA[8] nCRAS F 12.244 4 3.383 M
|
||||
RA[9] RCLK R 14.092 4 3.978 M
|
||||
RA[9] nCRAS F 13.164 4 3.653 M
|
||||
RBA[0] nCRAS F 10.278 4 2.970 M
|
||||
RBA[1] nCRAS F 10.474 4 3.030 M
|
||||
RCKE RCLK R 12.407 4 3.610 M
|
||||
RDQMH RCLK R 13.754 4 3.857 M
|
||||
RDQML RCLK R 13.482 4 3.833 M
|
||||
RD[0] nCCAS F 10.515 4 3.076 M
|
||||
RD[1] nCCAS F 10.118 4 2.965 M
|
||||
RD[2] nCCAS F 9.759 4 2.886 M
|
||||
RD[3] nCCAS F 9.798 4 2.878 M
|
||||
RD[4] nCCAS F 10.979 4 3.178 M
|
||||
RD[5] nCCAS F 11.063 4 3.207 M
|
||||
RD[6] nCCAS F 10.317 4 3.018 M
|
||||
RD[7] nCCAS F 10.232 4 2.986 M
|
||||
UFMCLK RCLK R 12.402 4 3.606 M
|
||||
UFMSDI RCLK R 11.975 4 3.501 M
|
||||
nRCAS RCLK R 12.350 4 3.564 M
|
||||
nRCS RCLK R 11.923 4 3.459 M
|
||||
nRRAS RCLK R 11.995 4 3.494 M
|
||||
nRWE RCLK R 11.975 4 3.501 M
|
||||
nUFMCS RCLK R 11.818 4 3.434 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -0,0 +1,41 @@
|
||||
-a "MachXO2"
|
||||
-d LCMXO2-1200HC
|
||||
-t TQFP100
|
||||
-s 4
|
||||
-frequency 200
|
||||
-optimization_goal Balanced
|
||||
-bram_utilization 100
|
||||
-ramstyle Auto
|
||||
-romstyle auto
|
||||
-dsp_utilization 100
|
||||
-use_dsp 1
|
||||
-use_carry_chain 1
|
||||
-carry_chain_length 0
|
||||
-force_gsr Auto
|
||||
-resource_sharing 1
|
||||
-propagate_constants 1
|
||||
-remove_duplicate_regs 1
|
||||
-mux_style Auto
|
||||
-max_fanout 1000
|
||||
-fsm_encoding_style Auto
|
||||
-twr_paths 3
|
||||
-fix_gated_clocks 1
|
||||
-loop_limit 1950
|
||||
|
||||
|
||||
|
||||
-use_io_insertion 1
|
||||
-resolve_mixed_drivers 0
|
||||
-use_io_reg auto
|
||||
|
||||
|
||||
-lpf 1
|
||||
-p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
|
||||
-ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v"
|
||||
-top RAM2GS
|
||||
|
||||
|
||||
-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
|
||||
|
||||
-ngd "RAM2GS_LCMXO2_1200HC_impl1.ngd"
|
||||
|
||||
15
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd
Normal file
15
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd
Normal file
@ -0,0 +1,15 @@
|
||||
[ActiveSupport MAP]
|
||||
Device = LCMXO2-1200HC;
|
||||
Package = TQFP100;
|
||||
Performance = 4;
|
||||
LUTS_avail = 1280;
|
||||
LUTS_used = 143;
|
||||
FF_avail = 1360;
|
||||
FF_used = 102;
|
||||
INPUT_LVCMOS25 = 26;
|
||||
OUTPUT_LVCMOS25 = 33;
|
||||
BIDI_LVCMOS25 = 8;
|
||||
IO_avail = 80;
|
||||
IO_used = 67;
|
||||
EBR_avail = 7;
|
||||
EBR_used = 0;
|
||||
88
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam
Normal file
88
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam
Normal file
@ -0,0 +1,88 @@
|
||||
[ START MERGED ]
|
||||
n2380 Ready
|
||||
PHI2_N_120 PHI2_c
|
||||
nRWE_N_176 nRWE_N_177
|
||||
n1407 nRowColSel_N_34
|
||||
n1408 nRowColSel_N_35
|
||||
[ END MERGED ]
|
||||
[ START CLIPPED ]
|
||||
GND_net
|
||||
VCC_net
|
||||
FS_610_add_4_19/S1
|
||||
FS_610_add_4_19/CO
|
||||
FS_610_add_4_1/S0
|
||||
FS_610_add_4_1/CI
|
||||
[ END CLIPPED ]
|
||||
[ START DESIGN PREFS ]
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:27 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "UFMCLK" SITE "29" ;
|
||||
LOCATE COMP "UFMSDI" SITE "30" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "nFWE" SITE "28" ;
|
||||
LOCATE COMP "RCLK" SITE "62" ;
|
||||
LOCATE COMP "UFMSDO" SITE "27" ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
||||
10
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr
Normal file
10
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr
Normal file
@ -0,0 +1,10 @@
|
||||
---------------------------------------------------
|
||||
Report for cell RAM2GS
|
||||
Instance path: RAM2GS
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 75.00 100.0
|
||||
LUT4 123.00 100.0
|
||||
IOBUF 67 100.0
|
||||
PFUREG 102 100.0
|
||||
RIPPLE 10 100.0
|
||||
BIN
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd
Normal file
BIN
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd
Normal file
Binary file not shown.
3176
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf
Normal file
3176
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf
Normal file
File diff suppressed because it is too large
Load Diff
26387
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho
Normal file
26387
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho
Normal file
File diff suppressed because it is too large
Load Diff
3176
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
Normal file
3176
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf
Normal file
File diff suppressed because it is too large
Load Diff
3692
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
Normal file
3692
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo
Normal file
File diff suppressed because it is too large
Load Diff
425
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html
Normal file
425
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html
Normal file
@ -0,0 +1,425 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Mrp"></A>
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
|
||||
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf D:/O
|
||||
neDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200
|
||||
HC_impl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RA
|
||||
M2GS_LCMXO2_1200HC.lpf -c 0 -gui -msgset
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 08/15/23 05:03:26
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 102 out of 1520 (7%)
|
||||
PFU registers: 102 out of 1280 (8%)
|
||||
PIO registers: 0 out of 240 (0%)
|
||||
Number of SLICEs: 75 out of 640 (12%)
|
||||
SLICEs as Logic/ROM: 75 out of 640 (12%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 10 out of 640 (2%)
|
||||
Number of LUT4s: 143 out of 1280 (11%)
|
||||
Number used as logic LUTs: 123
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : No
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
|
||||
|
||||
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
|
||||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
|
||||
Number of Clock Enables: 14
|
||||
Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
|
||||
Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
|
||||
Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
|
||||
Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
|
||||
Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
|
||||
Net Ready_N_292: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 7
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
|
||||
Net Ready: 7 loads, 7 LSLICEs
|
||||
Net nRWE_N_177: 1 loads, 1 LSLICEs
|
||||
Net C1Submitted_N_237: 2 loads, 2 LSLICEs
|
||||
Net n2366: 2 loads, 2 LSLICEs
|
||||
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net Ready: 18 loads
|
||||
Net InitReady: 15 loads
|
||||
Net RASr2: 15 loads
|
||||
Net nRowColSel_N_35: 13 loads
|
||||
Net nRowColSel: 12 loads
|
||||
Net Din_c_4: 10 loads
|
||||
Net MAin_c_1: 10 loads
|
||||
Net Din_c_5: 9 loads
|
||||
Net MAin_c_0: 9 loads
|
||||
Net Din_c_0: 8 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 0
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
|
||||
|
||||
No errors or warnings present.
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| RA[3] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nUFMCS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| UFMCLK | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| UFMSDI | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Din[6] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| UFMSDO | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
|
||||
|
||||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Block i2 undriven or does not drive anything - clipped.
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal PHI2_N_120 was merged into signal PHI2_c
|
||||
Signal n1407 was merged into signal nRowColSel_N_34
|
||||
Signal n2380 was merged into signal Ready
|
||||
Signal n1408 was merged into signal nRowColSel_N_35
|
||||
Signal nRWE_N_176 was merged into signal nRWE_N_177
|
||||
Signal GND_net undriven or does not drive anything - clipped.
|
||||
Signal VCC_net undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped.
|
||||
Block i2046 was optimized away.
|
||||
Block i1118_1_lut was optimized away.
|
||||
Block i637_1_lut_rep_31 was optimized away.
|
||||
Block i1119_1_lut was optimized away.
|
||||
Block nRWE_I_50_1_lut was optimized away.
|
||||
Block i1 was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 41 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
374
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html
Normal file
374
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html
Normal file
@ -0,0 +1,374 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>PAD Specification File</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Pad"></A>PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Tue Aug 15 05:03:35 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS25_IN | PL4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS25_IN | PL8A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS25_IN | PL3A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS25_IN | PT10B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS25_IN | PT12A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS25_IN | PT10A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS25_IN | PT9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS25_IN | PL2D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS25_OUT | PT17D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVCMOS25_OUT | PT12C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVCMOS25_OUT | PT12B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVCMOS25_OUT | PT12D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVCMOS25_OUT | PT15B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVCMOS25_OUT | PT15A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVCMOS25_OUT | PT16C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVCMOS25_OUT | PT15C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| LED | 34/2 | LVCMOS25_OUT | PB9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS25_IN | PL9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS25_IN | PL9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS25_IN | PL8D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS25_IN | PL10C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS25_IN | PL8C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS25_IN | PL10D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS25_IN | PB6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS25_OUT | PR4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS25_OUT | PR8D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS25_OUT | PR4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS25_OUT | PR4A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS25_OUT | PR4B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS25_OUT | PR9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS25_OUT | PR8C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS25_OUT | PR9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS25_OUT | PR10D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS25_OUT | PB20C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS25_BIDI | PB11C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS25_BIDI | PB11D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS25_BIDI | PB11A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS25_BIDI | PB11B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS25_BIDI | PB15A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS25_BIDI | PB15B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS25_BIDI | PB18A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS25_BIDI | PB18B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| UFMCLK | 29/2 | LVCMOS25_OUT | PB6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| UFMSDI | 30/2 | LVCMOS25_OUT | PB6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| UFMSDO | 27/2 | LVCMOS25_IN | PB4C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCCAS | 9/3 | LVCMOS25_IN | PL4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS25_IN | PL8B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 28/2 | LVCMOS25_IN | PB4D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS25_OUT | PR10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS25_OUT | PR9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS25_OUT | PR9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS25_OUT | PB20D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nUFMCS | 47/2 | LVCMOS25_OUT | PB18D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 2.5V |
|
||||
| 1 | 2.5V |
|
||||
| 2 | 2.5V |
|
||||
| 3 | 2.5V |
|
||||
+------+-------+
|
||||
|
||||
|
||||
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3D | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL4A | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL4B | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | |
|
||||
| 15/3 | unused, PULL:DOWN | | | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL8A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL8B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL8C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL8D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL10C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL10D | | | |
|
||||
| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4C | CSSPIN | | |
|
||||
| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4D | | | |
|
||||
| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB6A | | | |
|
||||
| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB6B | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB11C | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB11D | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB15A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB15B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | nUFMCS | | LVCMOS25_OUT | PB18D | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB20C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT15B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT15A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT10B | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT10A | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT9B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "62";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "UFMCLK" SITE "29";
|
||||
LOCATE COMP "UFMSDI" SITE "30";
|
||||
LOCATE COMP "UFMSDO" SITE "27";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "28";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
LOCATE COMP "nUFMCS" SITE "47";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:38 2023
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
397
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html
Normal file
397
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html
Normal file
@ -0,0 +1,397 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Place & Route Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:31 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
<span style="background-color:red">5_1 * 0 -4.650 391939 0.304 0 08 Completed</span>
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 8 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Tue Aug 15 05:03:31 2023
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 67+4(JTAG)/108 66% used
|
||||
67+4(JTAG)/80 89% bonded
|
||||
|
||||
SLICE 75/640 11% used
|
||||
|
||||
|
||||
|
||||
Number of Signals: 285
|
||||
Number of Connections: 674
|
||||
WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
|
||||
|
||||
Pin Constraint Summary:
|
||||
66 out of 67 pins locked (98% locked).
|
||||
|
||||
The following 2 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 40)
|
||||
PHI2_c (driver: PHI2, clk load #: 13)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
.
|
||||
Starting Placer Phase 0.
|
||||
..........
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...................
|
||||
Placer score = 143529.
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 143450
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
|
||||
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 3 out of 108 (2%)
|
||||
PLL : 0 out of 1 (0%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13
|
||||
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 2 out of 8 (25%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
Edge Clocks:
|
||||
No edge clock selected.
|
||||
|
||||
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
67 + 4(JTAG) out of 108 (65.7%) PIO sites used.
|
||||
67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 67; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 2.5V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 2.5V | - |
|
||||
| 2 | 17 / 20 ( 85%) | 2.5V | - |
|
||||
| 3 | 17 / 20 ( 85%) | 2.5V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 4 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 674 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=nCCAS_c loads=6 clock_loads=4
|
||||
|
||||
Completed router resource preassignment. Real time: 7 secs
|
||||
|
||||
Start NBR router at 05:03:38 08/15/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:03:38 08/15/23
|
||||
|
||||
Start NBR section for initial routing at 05:03:38 08/15/23
|
||||
Level 1, iteration 1
|
||||
2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -5.186ns/-468.418ns; real time: 7 secs
|
||||
Level 2, iteration 1
|
||||
11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-377.051ns; real time: 8 secs
|
||||
Level 3, iteration 1
|
||||
20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-373.496ns; real time: 8 secs
|
||||
Level 4, iteration 1
|
||||
11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-386.255ns; real time: 8 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:03:39 08/15/23
|
||||
Level 1, iteration 1
|
||||
7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-379.537ns; real time: 8 secs
|
||||
Level 4, iteration 1
|
||||
9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-380.800ns; real time: 8 secs
|
||||
Level 4, iteration 2
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-390.587ns; real time: 8 secs
|
||||
Level 4, iteration 3
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs
|
||||
Level 4, iteration 4
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs
|
||||
Level 4, iteration 5
|
||||
4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs
|
||||
Level 4, iteration 6
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs
|
||||
Level 4, iteration 7
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs
|
||||
Level 4, iteration 8
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs
|
||||
Level 4, iteration 9
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs
|
||||
Level 4, iteration 10
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs
|
||||
Level 4, iteration 11
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs
|
||||
Level 4, iteration 12
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs
|
||||
Level 4, iteration 13
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs
|
||||
Level 4, iteration 14
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs
|
||||
Level 4, iteration 15
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 16
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 17
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs
|
||||
Level 4, iteration 18
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs
|
||||
Level 4, iteration 19
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 20
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 21
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 22
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs
|
||||
Level 4, iteration 23
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs
|
||||
Level 4, iteration 24
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs
|
||||
Level 4, iteration 25
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs
|
||||
|
||||
Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23
|
||||
Level 4, iteration 1
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-405.830ns; real time: 8 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs
|
||||
|
||||
Start NBR section for re-routing at 05:03:39 08/15/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs
|
||||
|
||||
Start NBR section for post-routing at 05:03:39 08/15/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 254 (37.69%)
|
||||
Estimated worst slack<setup> : -4.650ns
|
||||
Timing score<setup> : 391939
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=nCCAS_c loads=6 clock_loads=4
|
||||
|
||||
Total CPU time 7 secs
|
||||
Total REAL time: 8 secs
|
||||
Completely routed.
|
||||
End of route. 674 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 391939
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = -4.650
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 391.939
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 8 secs
|
||||
Total REAL time to completion: 8 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -0,0 +1,83 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
|
||||
<TR>
|
||||
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2GS_LCMXO2_1200HC project summary</B></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2GS_LCMXO2_1200HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Lattice LSE</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC-4TG100C</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2GS_LCMXO2_1200HC.lpf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2GS_LCMXO2_1200HC_impl1.prf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.12.1.454</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/08/15 05:03:45</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf</SPAN></TD>
|
||||
</TR>
|
||||
</small></TABLE>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
430
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html
Normal file
430
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html
Normal file
@ -0,0 +1,430 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
|
||||
|
||||
Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Tue Aug 15 05:03:28 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<FONT COLOR=red><LI><A href='#map_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "RCLK_c" 299.401000 MHz (245 errors)</FONT></A></LI>
|
||||
</FONT> 459 items scored, 245 timing errors detected.
|
||||
Warning: 139.762MHz is the maximum frequency for this preference.
|
||||
|
||||
<FONT COLOR=red><LI><A href='#map_twr_pref_0_1' Target='right'><FONT COLOR=red>FREQUENCY NET "PHI2_c" 99.079000 MHz (104 errors)</FONT></A></LI>
|
||||
</FONT> 113 items scored, 104 timing errors detected.
|
||||
Warning: 50.592MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Type: based on TRACE automatically generated preferences
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
|
||||
459 items scored, 245 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path exceeds requirements by 3.815ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS_610__i13 (from RCLK_c +)
|
||||
Destination: FF Data in n8MEGEN_418 (to RCLK_c +)
|
||||
|
||||
Delay: 6.873ns (28.2% logic, 71.8% route), 4 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
6.873ns physical path delay SLICE_0 to SLICE_57 exceeds
|
||||
3.340ns delay constraint less
|
||||
0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_0 to SLICE_57:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_0.CLK to SLICE_0.Q0 SLICE_0 (from RCLK_c)
|
||||
ROUTE 3 e 1.234 SLICE_0.Q0 to SLICE_85.B0 FS_13
|
||||
CTOF_DEL --- 0.495 SLICE_85.B0 to SLICE_85.F0 SLICE_85
|
||||
ROUTE 5 e 1.234 SLICE_85.F0 to SLICE_57.A1 n10
|
||||
CTOF_DEL --- 0.495 SLICE_57.A1 to SLICE_57.F1 SLICE_57
|
||||
ROUTE 2 e 1.234 SLICE_57.F1 to SLICE_84.A0 n2367
|
||||
CTOF_DEL --- 0.495 SLICE_84.A0 to SLICE_84.F0 SLICE_84
|
||||
ROUTE 1 e 1.234 SLICE_84.F0 to SLICE_57.CE RCLK_c_enable_15 (to RCLK_c)
|
||||
--------
|
||||
6.873 (28.2% logic, 71.8% route), 4 logic levels.
|
||||
|
||||
Warning: 139.762MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
|
||||
113 items scored, 104 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns)
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_i7 (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable_405 (to PHI2_c -)
|
||||
|
||||
Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.577ns physical path delay SLICE_101 to SLICE_19 exceeds
|
||||
5.047ns delay constraint less
|
||||
0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_101 to SLICE_19:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_101.CLK to SLICE_101.Q1 SLICE_101 (from PHI2_c)
|
||||
ROUTE 1 e 1.234 SLICE_101.Q1 to SLICE_100.C1 Bank_7
|
||||
CTOF_DEL --- 0.495 SLICE_100.C1 to SLICE_100.F1 SLICE_100
|
||||
ROUTE 1 e 1.234 SLICE_100.F1 to SLICE_74.B1 n2277
|
||||
CTOF_DEL --- 0.495 SLICE_74.B1 to SLICE_74.F1 SLICE_74
|
||||
ROUTE 8 e 1.234 SLICE_74.F1 to SLICE_91.B1 n26
|
||||
CTOF_DEL --- 0.495 SLICE_91.B1 to SLICE_91.F1 SLICE_91
|
||||
ROUTE 1 e 1.234 SLICE_91.F1 to SLICE_88.D0 n2362
|
||||
CTOF_DEL --- 0.495 SLICE_88.D0 to SLICE_88.F0 SLICE_88
|
||||
ROUTE 3 e 0.480 SLICE_88.F0 to SLICE_88.C1 C1Submitted_N_237
|
||||
CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88
|
||||
ROUTE 1 e 1.234 SLICE_88.F1 to SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c)
|
||||
--------
|
||||
9.577 (30.6% logic, 69.4% route), 6 logic levels.
|
||||
|
||||
Warning: 50.592MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 139.762 MHz| 4 *
|
||||
| | |
|
||||
FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 50.592 MHz| 6 *
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 preferences(marked by "*" above) not met.
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
Critical Nets | Loads| Errors| % of total
|
||||
----------------------------------------------------------------------------
|
||||
n26 | 8| 78| 22.35%
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40
|
||||
Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
|
||||
Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 349 Score: 848079
|
||||
Cumulative negative slack: 584487
|
||||
|
||||
Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Tue Aug 15 05:03:28 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)</A></LI> 459 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)</A></LI> 113 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
|
||||
459 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.351ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q IS_FSM__i4 (from RCLK_c +)
|
||||
Destination: FF Data in IS_FSM__i5 (to RCLK_c +)
|
||||
|
||||
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.332ns physical path delay SLICE_106 to SLICE_106 meets
|
||||
-0.019ns M_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_106 to SLICE_106:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_106.CLK to SLICE_106.Q0 SLICE_106 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_106.Q0 to SLICE_106.M1 n736 (to RCLK_c)
|
||||
--------
|
||||
0.332 (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
|
||||
113 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q C1Submitted_406 (from PHI2_c -)
|
||||
Destination: FF Data in C1Submitted_406 (to PHI2_c -)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_15 to SLICE_15 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_15 to SLICE_15:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c)
|
||||
ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.C0 C1Submitted
|
||||
CTOF_DEL --- 0.101 SLICE_15.C0 to SLICE_15.F0 SLICE_15
|
||||
ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n1398 (to PHI2_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.351 ns| 1
|
||||
| | |
|
||||
FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.447 ns| 2
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40
|
||||
Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
|
||||
Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
|
||||
|
||||
|
||||
|
||||
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 349 (setup), 0 (hold)
|
||||
Score: 848079 (setup), 0 (hold)
|
||||
Cumulative negative slack: 584487 (584487+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
2244
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
Normal file
2244
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
Normal file
File diff suppressed because it is too large
Load Diff
16
CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log
Normal file
16
CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log
Normal file
@ -0,0 +1,16 @@
|
||||
Results of NGD DRC are available in RAM2GS_drc.log.
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
|
||||
|
||||
Running DRC...
|
||||
|
||||
DRC complete with no errors or warnings
|
||||
|
||||
Design Results:
|
||||
309 blocks expanded
|
||||
completed the first expansion
|
||||
All blocks are expanded and NGD expansion is successful.
|
||||
Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd.
|
||||
297
CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr
Normal file
297
CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr
Normal file
@ -0,0 +1,297 @@
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice Synthesis Timing Report, Version
|
||||
Tue Aug 15 05:03:26 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Design: RAM2GS
|
||||
Constraint file:
|
||||
Report level: verbose report, limited to 3 items per constraint
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
|
||||
122 items scored, 119 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 7.418ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i1 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -)
|
||||
|
||||
Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.633ns data_path Bank_i1 to CmdEnable_405 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
|
||||
|
||||
Path Details: Bank_i1 to CmdEnable_405
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[1]
|
||||
LUT4 --- 0.493 D to Z i8_4_lut
|
||||
Route 2 e 1.141 n22
|
||||
LUT4 --- 0.493 B to Z i11_3_lut_rep_20
|
||||
Route 7 e 1.502 n2369
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut
|
||||
Route 1 e 0.941 n2362
|
||||
LUT4 --- 0.493 D to Z i1_4_lut_adj_13
|
||||
Route 3 e 1.258 C1Submitted_N_237
|
||||
LUT4 --- 0.493 C to Z i34_4_lut
|
||||
Route 1 e 0.941 PHI2_N_120_enable_1
|
||||
--------
|
||||
9.633 (30.2% logic, 69.8% route), 6 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 7.418ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -)
|
||||
|
||||
Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.633ns data_path Bank_i4 to CmdEnable_405 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
|
||||
|
||||
Path Details: Bank_i4 to CmdEnable_405
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[4]
|
||||
LUT4 --- 0.493 C to Z i8_4_lut
|
||||
Route 2 e 1.141 n22
|
||||
LUT4 --- 0.493 B to Z i11_3_lut_rep_20
|
||||
Route 7 e 1.502 n2369
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut
|
||||
Route 1 e 0.941 n2362
|
||||
LUT4 --- 0.493 D to Z i1_4_lut_adj_13
|
||||
Route 3 e 1.258 C1Submitted_N_237
|
||||
LUT4 --- 0.493 C to Z i34_4_lut
|
||||
Route 1 e 0.941 PHI2_N_120_enable_1
|
||||
--------
|
||||
9.633 (30.2% logic, 69.8% route), 6 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 7.256ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i3 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -)
|
||||
|
||||
Delay: 9.471ns (30.7% logic, 69.3% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.471ns data_path Bank_i3 to CmdEnable_405 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
|
||||
|
||||
Path Details: Bank_i3 to CmdEnable_405
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[3]
|
||||
LUT4 --- 0.493 B to Z i1989_2_lut
|
||||
Route 1 e 0.941 n2287
|
||||
LUT4 --- 0.493 C to Z i12_4_lut
|
||||
Route 8 e 1.540 n26
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_rep_13_3_lut
|
||||
Route 1 e 0.941 n2362
|
||||
LUT4 --- 0.493 D to Z i1_4_lut_adj_13
|
||||
Route 3 e 1.258 C1Submitted_N_237
|
||||
LUT4 --- 0.493 C to Z i34_4_lut
|
||||
Route 1 e 0.941 PHI2_N_120_enable_1
|
||||
--------
|
||||
9.471 (30.7% logic, 69.3% route), 6 logic levels.
|
||||
|
||||
Warning: 9.918 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
|
||||
498 items scored, 186 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 3.319ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_610__i13 (from RCLK_c +)
|
||||
Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +)
|
||||
|
||||
Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.159ns data_path FS_610__i13 to nUFMCS_415 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
|
||||
|
||||
Path Details: FS_610__i13 to nUFMCS_415
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_610__i13 (from RCLK_c)
|
||||
Route 3 e 1.315 FS[13]
|
||||
LUT4 --- 0.493 B to Z i3_4_lut_adj_7
|
||||
Route 5 e 1.405 n10
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut
|
||||
Route 2 e 1.141 n2368
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_4_lut
|
||||
Route 1 e 0.941 n64
|
||||
LUT4 --- 0.493 B to Z i1448_4_lut
|
||||
Route 1 e 0.941 nUFMCS_N_199
|
||||
--------
|
||||
8.159 (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 3.319ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_610__i15 (from RCLK_c +)
|
||||
Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +)
|
||||
|
||||
Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.159ns data_path FS_610__i15 to nUFMCS_415 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
|
||||
|
||||
Path Details: FS_610__i15 to nUFMCS_415
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_610__i15 (from RCLK_c)
|
||||
Route 3 e 1.315 FS[15]
|
||||
LUT4 --- 0.493 C to Z i3_4_lut_adj_7
|
||||
Route 5 e 1.405 n10
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut
|
||||
Route 2 e 1.141 n2368
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_4_lut
|
||||
Route 1 e 0.941 n64
|
||||
LUT4 --- 0.493 B to Z i1448_4_lut
|
||||
Route 1 e 0.941 nUFMCS_N_199
|
||||
--------
|
||||
8.159 (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 3.319ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_610__i16 (from RCLK_c +)
|
||||
Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +)
|
||||
|
||||
Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.159ns data_path FS_610__i16 to nUFMCS_415 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
|
||||
|
||||
Path Details: FS_610__i16 to nUFMCS_415
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_610__i16 (from RCLK_c)
|
||||
Route 3 e 1.315 FS[16]
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_7
|
||||
Route 5 e 1.405 n10
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut
|
||||
Route 2 e 1.141 n2368
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_4_lut
|
||||
Route 1 e 0.941 n64
|
||||
LUT4 --- 0.493 B to Z i1448_4_lut
|
||||
Route 1 e 0.941 nUFMCS_N_199
|
||||
--------
|
||||
8.159 (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
Warning: 8.319 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
Timing Report Summary
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets PHI2_c] | 5.000 ns| 19.836 ns| 6 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 5.000 ns| 8.319 ns| 5 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 constraints not met.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Critical Nets | Loads| Errors| % of total
|
||||
--------------------------------------------------------------------------------
|
||||
n26 | 8| 84| 27.54%
|
||||
| | |
|
||||
n1997 | 1| 36| 11.80%
|
||||
| | |
|
||||
n1996 | 1| 35| 11.48%
|
||||
| | |
|
||||
n1995 | 1| 33| 10.82%
|
||||
| | |
|
||||
n10 | 5| 32| 10.49%
|
||||
| | |
|
||||
n1998 | 1| 32| 10.49%
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Timing summary:
|
||||
---------------
|
||||
|
||||
Timing errors: 305 Score: 1313492
|
||||
|
||||
Constraints cover 621 paths, 182 nets, and 471 connections (64.2% coverage)
|
||||
|
||||
|
||||
Peak memory: 57921536 bytes, TRCE: 2363392 bytes, DLYMAN: 0 bytes
|
||||
CPU_TIME_REPORT: 0 secs
|
||||
362
CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html
Normal file
362
CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html
Normal file
@ -0,0 +1,362 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Lattice Synthesis Timing Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
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h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
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margin-top: 4px;
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margin-right: 4px;
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{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
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font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
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a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
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.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice Synthesis Timing Report, Version
|
||||
Tue Aug 15 05:03:26 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Design: RAM2GS
|
||||
Constraint file:
|
||||
Report level: verbose report, limited to 3 items per constraint
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
|
||||
122 items scored, 119 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 7.418ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i1 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -)
|
||||
|
||||
Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.633ns data_path Bank_i1 to CmdEnable_405 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
|
||||
|
||||
Path Details: Bank_i1 to CmdEnable_405
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[1]
|
||||
LUT4 --- 0.493 D to Z i8_4_lut
|
||||
Route 2 e 1.141 n22
|
||||
LUT4 --- 0.493 B to Z i11_3_lut_rep_20
|
||||
Route 7 e 1.502 n2369
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut
|
||||
Route 1 e 0.941 n2362
|
||||
LUT4 --- 0.493 D to Z i1_4_lut_adj_13
|
||||
Route 3 e 1.258 C1Submitted_N_237
|
||||
LUT4 --- 0.493 C to Z i34_4_lut
|
||||
Route 1 e 0.941 PHI2_N_120_enable_1
|
||||
--------
|
||||
9.633 (30.2% logic, 69.8% route), 6 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 7.418ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -)
|
||||
|
||||
Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.633ns data_path Bank_i4 to CmdEnable_405 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
|
||||
|
||||
Path Details: Bank_i4 to CmdEnable_405
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[4]
|
||||
LUT4 --- 0.493 C to Z i8_4_lut
|
||||
Route 2 e 1.141 n22
|
||||
LUT4 --- 0.493 B to Z i11_3_lut_rep_20
|
||||
Route 7 e 1.502 n2369
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut
|
||||
Route 1 e 0.941 n2362
|
||||
LUT4 --- 0.493 D to Z i1_4_lut_adj_13
|
||||
Route 3 e 1.258 C1Submitted_N_237
|
||||
LUT4 --- 0.493 C to Z i34_4_lut
|
||||
Route 1 e 0.941 PHI2_N_120_enable_1
|
||||
--------
|
||||
9.633 (30.2% logic, 69.8% route), 6 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 7.256ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i3 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -)
|
||||
|
||||
Delay: 9.471ns (30.7% logic, 69.3% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.471ns data_path Bank_i3 to CmdEnable_405 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
|
||||
|
||||
Path Details: Bank_i3 to CmdEnable_405
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[3]
|
||||
LUT4 --- 0.493 B to Z i1989_2_lut
|
||||
Route 1 e 0.941 n2287
|
||||
LUT4 --- 0.493 C to Z i12_4_lut
|
||||
Route 8 e 1.540 n26
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_rep_13_3_lut
|
||||
Route 1 e 0.941 n2362
|
||||
LUT4 --- 0.493 D to Z i1_4_lut_adj_13
|
||||
Route 3 e 1.258 C1Submitted_N_237
|
||||
LUT4 --- 0.493 C to Z i34_4_lut
|
||||
Route 1 e 0.941 PHI2_N_120_enable_1
|
||||
--------
|
||||
9.471 (30.7% logic, 69.3% route), 6 logic levels.
|
||||
|
||||
Warning: 9.918 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
|
||||
498 items scored, 186 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 3.319ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_610__i13 (from RCLK_c +)
|
||||
Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +)
|
||||
|
||||
Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.159ns data_path FS_610__i13 to nUFMCS_415 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
|
||||
|
||||
Path Details: FS_610__i13 to nUFMCS_415
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_610__i13 (from RCLK_c)
|
||||
Route 3 e 1.315 FS[13]
|
||||
LUT4 --- 0.493 B to Z i3_4_lut_adj_7
|
||||
Route 5 e 1.405 n10
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut
|
||||
Route 2 e 1.141 n2368
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_4_lut
|
||||
Route 1 e 0.941 n64
|
||||
LUT4 --- 0.493 B to Z i1448_4_lut
|
||||
Route 1 e 0.941 nUFMCS_N_199
|
||||
--------
|
||||
8.159 (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 3.319ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_610__i15 (from RCLK_c +)
|
||||
Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +)
|
||||
|
||||
Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.159ns data_path FS_610__i15 to nUFMCS_415 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
|
||||
|
||||
Path Details: FS_610__i15 to nUFMCS_415
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_610__i15 (from RCLK_c)
|
||||
Route 3 e 1.315 FS[15]
|
||||
LUT4 --- 0.493 C to Z i3_4_lut_adj_7
|
||||
Route 5 e 1.405 n10
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut
|
||||
Route 2 e 1.141 n2368
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_4_lut
|
||||
Route 1 e 0.941 n64
|
||||
LUT4 --- 0.493 B to Z i1448_4_lut
|
||||
Route 1 e 0.941 nUFMCS_N_199
|
||||
--------
|
||||
8.159 (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 3.319ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_610__i16 (from RCLK_c +)
|
||||
Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +)
|
||||
|
||||
Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
8.159ns data_path FS_610__i16 to nUFMCS_415 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
|
||||
|
||||
Path Details: FS_610__i16 to nUFMCS_415
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_610__i16 (from RCLK_c)
|
||||
Route 3 e 1.315 FS[16]
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_7
|
||||
Route 5 e 1.405 n10
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut
|
||||
Route 2 e 1.141 n2368
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_4_lut
|
||||
Route 1 e 0.941 n64
|
||||
LUT4 --- 0.493 B to Z i1448_4_lut
|
||||
Route 1 e 0.941 nUFMCS_N_199
|
||||
--------
|
||||
8.159 (29.6% logic, 70.4% route), 5 logic levels.
|
||||
|
||||
Warning: 8.319 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets PHI2_c] | 5.000 ns| 19.836 ns| 6 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 5.000 ns| 8.319 ns| 5 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 constraints not met.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Critical Nets | Loads| Errors| % of total
|
||||
--------------------------------------------------------------------------------
|
||||
n26 | 8| 84| 27.54%
|
||||
| | |
|
||||
n1997 | 1| 36| 11.80%
|
||||
| | |
|
||||
n1996 | 1| 35| 11.48%
|
||||
| | |
|
||||
n1995 | 1| 33| 10.82%
|
||||
| | |
|
||||
n10 | 5| 32| 10.49%
|
||||
| | |
|
||||
n1998 | 1| 32| 10.49%
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 305 Score: 1313492
|
||||
|
||||
Constraints cover 621 paths, 182 nets, and 471 connections (64.2% coverage)
|
||||
|
||||
|
||||
Peak memory: 57921536 bytes, TRCE: 2363392 bytes, DLYMAN: 0 bytes
|
||||
CPU_TIME_REPORT: 0 secs
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
802
CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v
Normal file
802
CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v
Normal file
@ -0,0 +1,802 @@
|
||||
// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454
|
||||
// Netlist written on Tue Aug 15 05:03:26 2023
|
||||
//
|
||||
// Verilog Description of module RAM2GS
|
||||
//
|
||||
|
||||
module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE,
|
||||
LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS,
|
||||
nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14])
|
||||
input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12])
|
||||
input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18])
|
||||
input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
|
||||
output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13])
|
||||
input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
|
||||
input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12])
|
||||
output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12])
|
||||
output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22])
|
||||
output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
|
||||
output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17])
|
||||
input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12])
|
||||
output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17])
|
||||
output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49])
|
||||
output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28])
|
||||
output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39])
|
||||
output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21])
|
||||
output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14])
|
||||
output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19])
|
||||
output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19])
|
||||
output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19])
|
||||
input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14])
|
||||
|
||||
wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12])
|
||||
wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13])
|
||||
wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
|
||||
wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12])
|
||||
wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13])
|
||||
wire nCRAS_c__inv /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
|
||||
|
||||
wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2,
|
||||
RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, LED_c,
|
||||
Din_c_7, Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1,
|
||||
Din_c_0;
|
||||
wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16])
|
||||
|
||||
wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6,
|
||||
MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0,
|
||||
nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c,
|
||||
nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0;
|
||||
wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16])
|
||||
|
||||
wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3,
|
||||
RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c;
|
||||
wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15])
|
||||
|
||||
wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted,
|
||||
CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI,
|
||||
CmdUFMCS, InitReady, Ready, n10;
|
||||
wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15])
|
||||
|
||||
wire RA11_N_184, PHI2_N_120_enable_8, n2036, n1765, n1893, n7,
|
||||
n917, n4, n2277, RCKE_N_132, nRowColSel_N_35, nRWE_N_182,
|
||||
nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, nRCS_N_146,
|
||||
n15, n2260, nRCS_N_142, n2362, nRCS_N_141, nRCAS_N_166,
|
||||
nRWE_N_178, n2180, nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176,
|
||||
n14, n6, n13, n1993, n2254, Ready_N_296, RCLK_c_enable_28,
|
||||
nRCS_N_137, Ready_N_292, nRCS_N_136, nRRAS_N_156, nRCAS_N_161,
|
||||
nRWE_N_171, n2220, RCKEEN_N_121, n15_adj_1, n2371, ADSubmitted_N_246,
|
||||
CmdEnable_N_248, C1Submitted_N_237, PHI2_N_120_enable_3, n2174,
|
||||
n6_adj_2, Cmdn8MEGEN_N_264, XOR8MEG_N_110, n2204, n1996, n6_adj_3,
|
||||
RCLK_c_enable_10, n2191, n2208, n22, n8MEGEN_N_91, UFMCLK_N_224,
|
||||
UFMSDI_N_231, n26, nUFMCS_N_199, n2055, PHI2_N_120_enable_2,
|
||||
n1999, n2287, n726, n727, n728, n729, n730, n732, n733,
|
||||
n734, n735, n736, n737, n738, n2267, n1398, n2183, n1995,
|
||||
PHI2_N_120_enable_1, n1060, n1408, n2228, n2447, n1406,
|
||||
PHI2_N_120_enable_6, n2225, n827, n2370, n1277, n15_adj_4,
|
||||
Dout_c, n78, n79, n80, n81, n82, n83, n84, n85, n86,
|
||||
n87, n88, n89, n90, n91, n92, n93, n94, n95, n2382,
|
||||
RCLK_c_enable_15, n9, n2369, n7_adj_5, n13_adj_6, n2381,
|
||||
n2210, n2380, n2227, n2368, PHI2_N_120_enable_7, n12, n1994,
|
||||
RCLK_c_enable_27, n2367, n1407, n2379, n2378, n2377, n2366,
|
||||
n2365, n2376, n1998, n2375, n4_adj_7, n2374, RCLK_c_enable_6,
|
||||
Dout_0, Dout_1, n984, Dout_2, n8, Dout_3, Dout_4, n1314,
|
||||
Dout_5, Dout_6, RCLK_c_enable_16, n2363, n13_adj_8, n2000,
|
||||
n2373, RCLK_c_enable_5, n1992, n1997, n2372, n64;
|
||||
|
||||
VHI i2 (.Z(VCC_net));
|
||||
INV i2046 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12])
|
||||
FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam PHI2r2_377.GSR = "ENABLED";
|
||||
LUT4 nRCAS_I_43_4_lut (.A(nRCS_N_142), .B(RASr2), .C(nRowColSel_N_35),
|
||||
.D(CBR), .Z(nRCAS_N_166)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(186[13] 231[7])
|
||||
defparam nRCAS_I_43_4_lut.init = 16'h3afa;
|
||||
LUT4 nRCAS_I_0_452_3_lut_4_lut (.A(n2371), .B(nRCAS_N_165), .C(Ready),
|
||||
.D(nRCAS_N_166), .Z(nRCAS_N_161)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
|
||||
defparam nRCAS_I_0_452_3_lut_4_lut.init = 16'hfe0e;
|
||||
LUT4 nRWE_I_0_455_4_lut (.A(n1765), .B(nRWE_N_178), .C(Ready), .D(n2371),
|
||||
.Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
|
||||
defparam nRWE_I_0_455_4_lut.init = 16'hcfc5;
|
||||
FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam PHI2r3_378.GSR = "ENABLED";
|
||||
FD1S3AX RASr_379 (.D(nCRAS_c__inv), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam RASr_379.GSR = "ENABLED";
|
||||
FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam RASr2_380.GSR = "ENABLED";
|
||||
FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam RASr3_381.GSR = "ENABLED";
|
||||
FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam CASr_382.GSR = "ENABLED";
|
||||
FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam CASr2_383.GSR = "ENABLED";
|
||||
FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam CASr3_384.GSR = "ENABLED";
|
||||
FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2380), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
|
||||
defparam RA11_385.GSR = "ENABLED";
|
||||
CCU2D FS_610_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1998),
|
||||
.COUT(n1999), .S0(n82), .S1(n81)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_15.INIT0 = 16'hfaaa;
|
||||
defparam FS_610_add_4_15.INIT1 = 16'hfaaa;
|
||||
defparam FS_610_add_4_15.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_15.INJECT1_1 = "NO";
|
||||
FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i0.GSR = "ENABLED";
|
||||
FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
|
||||
defparam WRD_i0.GSR = "ENABLED";
|
||||
FD1S3AX FWEr_389 (.D(n2373), .CK(nCRAS_c__inv), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam FWEr_389.GSR = "ENABLED";
|
||||
FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_c__inv), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam CBR_390.GSR = "ENABLED";
|
||||
FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5])
|
||||
defparam RCKE_395.GSR = "ENABLED";
|
||||
FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_6), .CK(RCLK_c),
|
||||
.Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam nRCS_396.GSR = "ENABLED";
|
||||
LUT4 i1477_2_lut (.A(nRWE_N_177), .B(nRCAS_N_165), .Z(n1765)) /* synthesis lut_function=(A+(B)) */ ;
|
||||
defparam i1477_2_lut.init = 16'heeee;
|
||||
FD1P3AX nRowColSel_402 (.D(n917), .SP(RCLK_c_enable_5), .CK(RCLK_c),
|
||||
.Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam nRowColSel_402.GSR = "ENABLED";
|
||||
CCU2D FS_610_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1997),
|
||||
.COUT(n1998), .S0(n84), .S1(n83)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_13.INIT0 = 16'hfaaa;
|
||||
defparam FS_610_add_4_13.INIT1 = 16'hfaaa;
|
||||
defparam FS_610_add_4_13.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_13.INJECT1_1 = "NO";
|
||||
LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_296), .Z(n6_adj_3)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam i2_2_lut.init = 16'h8888;
|
||||
FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_1),
|
||||
.CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
|
||||
defparam CmdEnable_405.GSR = "ENABLED";
|
||||
LUT4 i4_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n6_adj_2),
|
||||
.Z(n2204)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
|
||||
defparam i4_4_lut.init = 16'h4000;
|
||||
FD1P3IX ADSubmitted_407 (.D(ADSubmitted_N_246), .SP(PHI2_N_120_enable_2),
|
||||
.CD(C1Submitted_N_237), .CK(PHI2_N_120), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
|
||||
defparam ADSubmitted_407.GSR = "ENABLED";
|
||||
LUT4 i26_4_lut (.A(n2183), .B(n2191), .C(Din_c_5), .D(n2254), .Z(n15_adj_1)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;
|
||||
defparam i26_4_lut.init = 16'hc0ca;
|
||||
LUT4 i1_2_lut_3_lut_4_lut (.A(n2369), .B(n26), .C(n2204), .D(nFWE_c),
|
||||
.Z(n2220)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;
|
||||
defparam i1_2_lut_3_lut_4_lut.init = 16'h0020;
|
||||
FD1P3AY nRRAS_397 (.D(nRRAS_N_156), .SP(RCLK_c_enable_6), .CK(RCLK_c),
|
||||
.Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam nRRAS_397.GSR = "ENABLED";
|
||||
LUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8])
|
||||
defparam nRWE_I_50_1_lut.init = 16'h5555;
|
||||
BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
|
||||
FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_6), .CK(RCLK_c),
|
||||
.Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam nRCAS_398.GSR = "ENABLED";
|
||||
FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_5), .CK(RCLK_c),
|
||||
.Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam nRWE_399.GSR = "ENABLED";
|
||||
FD1S3JX RA10_400 (.D(n2036), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam RA10_400.GSR = "ENABLED";
|
||||
FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_6), .CK(RCLK_c),
|
||||
.Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam RCKEEN_401.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i0.GSR = "ENABLED";
|
||||
FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RBA__i1.GSR = "ENABLED";
|
||||
LUT4 i1_4_lut (.A(Din_c_5), .B(n2220), .C(Din_c_4), .D(Din_c_3),
|
||||
.Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(A (B (C (D)))+!A (B)) */ ;
|
||||
defparam i1_4_lut.init = 16'hc444;
|
||||
LUT4 i29_3_lut (.A(InitReady), .B(n15_adj_4), .C(Ready), .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
|
||||
defparam i29_3_lut.init = 16'hcaca;
|
||||
LUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4),
|
||||
.D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7])
|
||||
defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c;
|
||||
LUT4 i1956_2_lut (.A(MAin_c_0), .B(Din_c_2), .Z(n2254)) /* synthesis lut_function=(A+(B)) */ ;
|
||||
defparam i1956_2_lut.init = 16'heeee;
|
||||
FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i0.GSR = "ENABLED";
|
||||
CCU2D FS_610_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1995),
|
||||
.COUT(n1996), .S0(n88), .S1(n87)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_9.INIT0 = 16'hfaaa;
|
||||
defparam FS_610_add_4_9.INIT1 = 16'hfaaa;
|
||||
defparam FS_610_add_4_9.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_9.INJECT1_1 = "NO";
|
||||
FD1S3JX C1Submitted_406 (.D(n1398), .CK(PHI2_N_120), .PD(C1Submitted_N_237),
|
||||
.Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
|
||||
defparam C1Submitted_406.GSR = "ENABLED";
|
||||
FD1P3AY nUFMCS_415 (.D(nUFMCS_N_199), .SP(RCLK_c_enable_10), .CK(RCLK_c),
|
||||
.Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
|
||||
defparam nUFMCS_415.GSR = "ENABLED";
|
||||
LUT4 i2_4_lut (.A(n2220), .B(Din_c_4), .C(Din_c_3), .D(Din_c_5),
|
||||
.Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(A (B (C+!(D)))) */ ;
|
||||
defparam i2_4_lut.init = 16'h8088;
|
||||
FD1S3AX S_FSM_i1 (.D(n2374), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
|
||||
defparam S_FSM_i1.GSR = "ENABLED";
|
||||
CCU2D FS_610_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1994),
|
||||
.COUT(n1995), .S0(n90), .S1(n89)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_7.INIT0 = 16'hfaaa;
|
||||
defparam FS_610_add_4_7.INIT1 = 16'hfaaa;
|
||||
defparam FS_610_add_4_7.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_7.INJECT1_1 = "NO";
|
||||
LUT4 i1_2_lut (.A(Din_c_6), .B(Din_c_3), .Z(n2183)) /* synthesis lut_function=(!((B)+!A)) */ ;
|
||||
defparam i1_2_lut.init = 16'h2222;
|
||||
LUT4 i1_2_lut_rep_15_4_lut (.A(FS[10]), .B(FS[11]), .C(n2368), .D(InitReady),
|
||||
.Z(RCLK_c_enable_16)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
|
||||
defparam i1_2_lut_rep_15_4_lut.init = 16'h0008;
|
||||
CCU2D FS_610_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1992),
|
||||
.COUT(n1993), .S0(n94), .S1(n93)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_3.INIT0 = 16'hfaaa;
|
||||
defparam FS_610_add_4_3.INIT1 = 16'hfaaa;
|
||||
defparam FS_610_add_4_3.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_3.INJECT1_1 = "NO";
|
||||
LUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51])
|
||||
defparam RA11_I_54_3_lut.init = 16'hc6c6;
|
||||
LUT4 i9_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n9)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;
|
||||
defparam i9_2_lut_3_lut.init = 16'h1f1f;
|
||||
LUT4 i1491_2_lut_rep_30 (.A(RCKE_c), .B(RASr2), .Z(n2379)) /* synthesis lut_function=(A+(B)) */ ;
|
||||
defparam i1491_2_lut_rep_30.init = 16'heeee;
|
||||
LUT4 nRCS_I_31_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35),
|
||||
.D(nRCS_N_142), .Z(nRCS_N_141)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ;
|
||||
defparam nRCS_I_31_3_lut_4_lut.init = 16'h1f10;
|
||||
FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_10), .CD(n2366),
|
||||
.CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
|
||||
defparam UFMCLK_416.GSR = "ENABLED";
|
||||
LUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel),
|
||||
.Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca;
|
||||
LUT4 i3_4_lut (.A(Din_c_2), .B(Din_c_3), .C(Din_c_6), .D(MAin_c_0),
|
||||
.Z(n2191)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
|
||||
defparam i3_4_lut.init = 16'h0800;
|
||||
LUT4 i1_2_lut_rep_21_3_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_0),
|
||||
.Z(n2370)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
|
||||
defparam i1_2_lut_rep_21_3_lut.init = 16'h2020;
|
||||
LUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel),
|
||||
.Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca;
|
||||
LUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel),
|
||||
.Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca;
|
||||
LUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel),
|
||||
.Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca;
|
||||
LUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel),
|
||||
.Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca;
|
||||
CCU2D FS_610_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1992),
|
||||
.S1(n95)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_1.INIT0 = 16'hF000;
|
||||
defparam FS_610_add_4_1.INIT1 = 16'h0555;
|
||||
defparam FS_610_add_4_1.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_1.INJECT1_1 = "NO";
|
||||
LUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel),
|
||||
.Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca;
|
||||
FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam PHI2r_376.GSR = "ENABLED";
|
||||
LUT4 i1962_4_lut (.A(Din_c_4), .B(Din_c_1), .C(n1314), .D(LEDEN),
|
||||
.Z(n2260)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
|
||||
defparam i1962_4_lut.init = 16'hfefa;
|
||||
LUT4 i1423_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_182)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(168[14] 184[8])
|
||||
defparam i1423_2_lut.init = 16'hdddd;
|
||||
LUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel),
|
||||
.Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca;
|
||||
FD1S3IX S_FSM_i3 (.D(n1406), .CK(RCLK_c), .CD(n1407), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
|
||||
defparam S_FSM_i3.GSR = "ENABLED";
|
||||
FD1S3IX S_FSM_i4 (.D(n827), .CK(RCLK_c), .CD(n2374), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
|
||||
defparam S_FSM_i4.GSR = "ENABLED";
|
||||
LUT4 i1_2_lut_3_lut_4_lut_adj_1 (.A(Din_c_7), .B(Din_c_1), .C(Din_c_4),
|
||||
.D(Din_c_0), .Z(n2208)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
|
||||
defparam i1_2_lut_3_lut_4_lut_adj_1.init = 16'h0200;
|
||||
LUT4 MAin_c_0_bdd_4_lut (.A(n2369), .B(n26), .C(nFWE_c), .D(MAin_c_1),
|
||||
.Z(PHI2_N_120_enable_2)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
|
||||
defparam MAin_c_0_bdd_4_lut.init = 16'h0200;
|
||||
FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_10), .CD(n2366),
|
||||
.CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
|
||||
defparam UFMSDI_417.GSR = "ENABLED";
|
||||
LUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel),
|
||||
.Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca;
|
||||
LUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel),
|
||||
.Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca;
|
||||
LUT4 i1448_4_lut (.A(n13_adj_6), .B(n64), .C(CmdUFMCS), .D(InitReady),
|
||||
.Z(nUFMCS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C+!(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(345[12] 409[6])
|
||||
defparam i1448_4_lut.init = 16'h3fbb;
|
||||
LUT4 i2_3_lut_rep_18_4_lut (.A(n10), .B(n2375), .C(FS[11]), .D(FS[10]),
|
||||
.Z(n2367)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
|
||||
defparam i2_3_lut_rep_18_4_lut.init = 16'h1000;
|
||||
LUT4 i3_4_lut_adj_2 (.A(nRCS_N_139), .B(InitReady), .C(nRowColSel_N_35),
|
||||
.D(RASr2), .Z(nRCS_N_137)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
|
||||
defparam i3_4_lut_adj_2.init = 16'hbfff;
|
||||
LUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel),
|
||||
.Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54])
|
||||
defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca;
|
||||
LUT4 i1416_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46])
|
||||
defparam i1416_2_lut.init = 16'hbbbb;
|
||||
LUT4 i2001_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ;
|
||||
defparam i2001_2_lut.init = 16'h7777;
|
||||
LUT4 i2_3_lut_4_lut (.A(n2363), .B(MAin_c_1), .C(n2208), .D(n15_adj_1),
|
||||
.Z(CmdEnable_N_248)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
|
||||
defparam i2_3_lut_4_lut.init = 16'h4000;
|
||||
LUT4 i2005_3_lut_rep_17_4_lut (.A(n10), .B(n2375), .C(InitReady),
|
||||
.D(FS[11]), .Z(n2366)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;
|
||||
defparam i2005_3_lut_rep_17_4_lut.init = 16'h0001;
|
||||
FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
|
||||
defparam Bank_i0.GSR = "ENABLED";
|
||||
LUT4 i1427_4_lut (.A(nRCS_N_146), .B(nRowColSel_N_34), .C(n2378),
|
||||
.D(nRowColSel_N_33), .Z(nRCS_N_142)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7])
|
||||
defparam i1427_4_lut.init = 16'hfcdd;
|
||||
LUT4 i3_3_lut_4_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_6), .D(Din_c_4),
|
||||
.Z(n8)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
|
||||
defparam i3_3_lut_4_lut.init = 16'h0002;
|
||||
LUT4 i1_2_lut_adj_3 (.A(FS[10]), .B(n13_adj_6), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i1_2_lut_adj_3.init = 16'h8888;
|
||||
LUT4 i1119_1_lut (.A(nRowColSel_N_35), .Z(n1408)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
|
||||
defparam i1119_1_lut.init = 16'h5555;
|
||||
LUT4 nRCS_N_146_bdd_4_lut (.A(nRCS_N_146), .B(n1060), .C(nRWE_N_182),
|
||||
.D(nRowColSel_N_35), .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ;
|
||||
defparam nRCS_N_146_bdd_4_lut.init = 16'hf0dd;
|
||||
LUT4 i11_3_lut_rep_20 (.A(MAin_c_2), .B(n22), .C(MAin_c_5), .Z(n2369)) /* synthesis lut_function=(A (B (C))) */ ;
|
||||
defparam i11_3_lut_rep_20.init = 16'h8080;
|
||||
LUT4 i13_2_lut_rep_16_4_lut (.A(MAin_c_2), .B(n22), .C(MAin_c_5),
|
||||
.D(n26), .Z(n2365)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;
|
||||
defparam i13_2_lut_rep_16_4_lut.init = 16'hff7f;
|
||||
GSR GSR_INST (.GSR(VCC_net));
|
||||
LUT4 i1_4_lut_adj_4 (.A(n2180), .B(n2225), .C(n8), .D(n2382), .Z(ADSubmitted_N_246)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
|
||||
defparam i1_4_lut_adj_4.init = 16'h2000;
|
||||
LUT4 i6_4_lut (.A(FS[11]), .B(n12), .C(FS[14]), .D(FS[17]), .Z(n13_adj_6)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i6_4_lut.init = 16'h8000;
|
||||
LUT4 i8_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]),
|
||||
.Z(n22)) /* synthesis lut_function=(A (B (C (D)))) */ ;
|
||||
defparam i8_4_lut.init = 16'h8000;
|
||||
LUT4 i1_2_lut_3_lut_4_lut_adj_5 (.A(n2369), .B(n26), .C(MAin_c_0),
|
||||
.D(MAin_c_1), .Z(n2225)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;
|
||||
defparam i1_2_lut_3_lut_4_lut_adj_5.init = 16'hdfff;
|
||||
LUT4 i5_4_lut (.A(FS[13]), .B(FS[12]), .C(FS[15]), .D(FS[16]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i5_4_lut.init = 16'h8000;
|
||||
LUT4 i12_4_lut (.A(Bank[2]), .B(n2277), .C(n2287), .D(Bank[5]),
|
||||
.Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
|
||||
defparam i12_4_lut.init = 16'hbfff;
|
||||
LUT4 i2_3_lut_4_lut_adj_6 (.A(n2369), .B(n26), .C(MAin_c_0), .D(MAin_c_1),
|
||||
.Z(n1277)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;
|
||||
defparam i2_3_lut_4_lut_adj_6.init = 16'hffdf;
|
||||
LUT4 i637_1_lut_rep_31 (.A(Ready), .Z(n2380)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam i637_1_lut_rep_31.init = 16'h5555;
|
||||
LUT4 i1573_4_lut (.A(n2367), .B(n2377), .C(InitReady), .D(n4_adj_7),
|
||||
.Z(RCLK_c_enable_15)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15])
|
||||
defparam i1573_4_lut.init = 16'hcac0;
|
||||
LUT4 i3_4_lut_adj_7 (.A(FS[17]), .B(FS[13]), .C(FS[15]), .D(FS[16]),
|
||||
.Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i3_4_lut_adj_7.init = 16'hfffe;
|
||||
LUT4 i786_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n1060)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7])
|
||||
defparam i786_2_lut.init = 16'heeee;
|
||||
LUT4 i1_4_lut_adj_8 (.A(FS[4]), .B(n15), .C(n13), .D(n14), .Z(n4_adj_7)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
|
||||
defparam i1_4_lut_adj_8.init = 16'h0002;
|
||||
LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_139), .B(n2381), .C(Ready), .D(nRCAS_N_165),
|
||||
.Z(n2036)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb;
|
||||
LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n1060), .C(nRowColSel_N_32),
|
||||
.D(nRowColSel_N_35), .Z(RCLK_c_enable_5)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd;
|
||||
CCU2D FS_610_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1996),
|
||||
.COUT(n1997), .S0(n86), .S1(n85)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_11.INIT0 = 16'hfaaa;
|
||||
defparam FS_610_add_4_11.INIT1 = 16'hfaaa;
|
||||
defparam FS_610_add_4_11.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_11.INJECT1_1 = "NO";
|
||||
LUT4 i1603_3_lut (.A(n1893), .B(CmdUFMCLK), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15])
|
||||
defparam i1603_3_lut.init = 16'hcaca;
|
||||
LUT4 i1979_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]),
|
||||
.Z(n2277)) /* synthesis lut_function=(A (B (C (D)))) */ ;
|
||||
defparam i1979_4_lut.init = 16'h8000;
|
||||
FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i15.GSR = "ENABLED";
|
||||
LUT4 i771_2_lut_rep_23_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2372)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam i771_2_lut_rep_23_2_lut.init = 16'hdddd;
|
||||
LUT4 i6_4_lut_adj_9 (.A(FS[5]), .B(FS[7]), .C(FS[1]), .D(FS[2]),
|
||||
.Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
|
||||
defparam i6_4_lut_adj_9.init = 16'hfffe;
|
||||
LUT4 i1970_4_lut (.A(FS[4]), .B(n13_adj_6), .C(n2267), .D(FS[1]),
|
||||
.Z(n1893)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15])
|
||||
defparam i1970_4_lut.init = 16'h3a0a;
|
||||
LUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam i1_2_lut_2_lut.init = 16'hdddd;
|
||||
PFUMX i30 (.BLUT(n13_adj_8), .ALUT(n9), .C0(nRowColSel_N_35), .Z(n15_adj_4));
|
||||
FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i14.GSR = "ENABLED";
|
||||
FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i13.GSR = "ENABLED";
|
||||
LUT4 i1989_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2287)) /* synthesis lut_function=(A (B)) */ ;
|
||||
defparam i1989_2_lut.init = 16'h8888;
|
||||
LUT4 i2_3_lut_rep_32 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35),
|
||||
.Z(n2381)) /* synthesis lut_function=(A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20])
|
||||
defparam i2_3_lut_rep_32.init = 16'h8080;
|
||||
LUT4 i1_2_lut_rep_22_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35),
|
||||
.D(nRCS_N_139), .Z(n2371)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20])
|
||||
defparam i1_2_lut_rep_22_4_lut.init = 16'hff7f;
|
||||
FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i12.GSR = "ENABLED";
|
||||
FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_3), .CK(PHI2_N_120),
|
||||
.Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
|
||||
defparam XOR8MEG_408.GSR = "ENABLED";
|
||||
FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_15), .CK(RCLK_c),
|
||||
.Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
|
||||
defparam n8MEGEN_418.GSR = "ENABLED";
|
||||
CCU2D FS_610_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2000),
|
||||
.S0(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_19.INIT0 = 16'hfaaa;
|
||||
defparam FS_610_add_4_19.INIT1 = 16'h0000;
|
||||
defparam FS_610_add_4_19.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_19.INJECT1_1 = "NO";
|
||||
FD1P3AX LEDEN_419 (.D(n2447), .SP(RCLK_c_enable_16), .CK(RCLK_c),
|
||||
.Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5])
|
||||
defparam LEDEN_419.GSR = "ENABLED";
|
||||
FD1P3AX Ready_404 (.D(n2447), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam Ready_404.GSR = "ENABLED";
|
||||
FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120),
|
||||
.Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
|
||||
defparam CmdUFMCLK_413.GSR = "ENABLED";
|
||||
FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120),
|
||||
.Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
|
||||
defparam CmdUFMSDI_414.GSR = "ENABLED";
|
||||
FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_6),
|
||||
.CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
|
||||
defparam Cmdn8MEGEN_410.GSR = "ENABLED";
|
||||
FD1P3AX CmdSubmitted_411 (.D(n2447), .SP(PHI2_N_120_enable_7), .CK(PHI2_N_120),
|
||||
.Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
|
||||
defparam CmdSubmitted_411.GSR = "ENABLED";
|
||||
FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120),
|
||||
.Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5])
|
||||
defparam CmdUFMCS_412.GSR = "ENABLED";
|
||||
FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i11.GSR = "ENABLED";
|
||||
LUT4 i2008_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35),
|
||||
.D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20])
|
||||
defparam i2008_2_lut_4_lut.init = 16'h0080;
|
||||
LUT4 i1404_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(15[12:17])
|
||||
defparam i1404_4_lut.init = 16'hcfc8;
|
||||
LUT4 i1118_1_lut (.A(nRowColSel_N_34), .Z(n1407)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
|
||||
defparam i1118_1_lut.init = 16'h5555;
|
||||
FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i10.GSR = "ENABLED";
|
||||
LUT4 i1_2_lut_adj_10 (.A(RASr2), .B(nRowColSel_N_32), .Z(n1406)) /* synthesis lut_function=(!((B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5])
|
||||
defparam i1_2_lut_adj_10.init = 16'h2222;
|
||||
LUT4 i1439_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n827)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
|
||||
defparam i1439_2_lut.init = 16'heeee;
|
||||
FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i9.GSR = "ENABLED";
|
||||
LUT4 i1432_4_lut (.A(FWEr), .B(n2372), .C(n1060), .D(n2376), .Z(n917)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5])
|
||||
defparam i1432_4_lut.init = 16'h3032;
|
||||
LUT4 i1_2_lut_rep_33 (.A(Din_c_0), .B(Din_c_2), .Z(n2382)) /* synthesis lut_function=(A (B)) */ ;
|
||||
defparam i1_2_lut_rep_33.init = 16'h8888;
|
||||
LUT4 i1_4_lut_4_lut (.A(CBR), .B(n2227), .C(FWEr), .D(nRowColSel_N_34),
|
||||
.Z(n13_adj_8)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31])
|
||||
defparam i1_4_lut_4_lut.init = 16'h5540;
|
||||
LUT4 i4_2_lut (.A(FS[8]), .B(FS[0]), .Z(n13)) /* synthesis lut_function=(A+(B)) */ ;
|
||||
defparam i4_2_lut.init = 16'heeee;
|
||||
LUT4 i1589_4_lut (.A(n2174), .B(CmdUFMSDI), .C(InitReady), .D(n4),
|
||||
.Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15])
|
||||
defparam i1589_4_lut.init = 16'hcac0;
|
||||
LUT4 i2_1_lut_rep_24 (.A(nFWE_c), .Z(n2373)) /* synthesis lut_function=(!(A)) */ ;
|
||||
defparam i2_1_lut_rep_24.init = 16'h5555;
|
||||
LUT4 i2_3_lut_4_lut_adj_11 (.A(Din_c_0), .B(Din_c_2), .C(n2260), .D(Din_c_3),
|
||||
.Z(XOR8MEG_N_110)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
|
||||
defparam i2_3_lut_4_lut_adj_11.init = 16'h0008;
|
||||
FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i8.GSR = "ENABLED";
|
||||
FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i7.GSR = "ENABLED";
|
||||
FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i6.GSR = "ENABLED";
|
||||
FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i5.GSR = "ENABLED";
|
||||
FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i4.GSR = "ENABLED";
|
||||
FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i3.GSR = "ENABLED";
|
||||
FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i2.GSR = "ENABLED";
|
||||
FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_27), .CK(RCLK_c),
|
||||
.Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15])
|
||||
defparam IS_FSM__i1.GSR = "ENABLED";
|
||||
FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RBA__i2.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i17.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i16.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i15.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i14.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i13.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i12.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i11.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i10.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i9.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i8.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i7.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i6.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i5.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i4.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i3.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i2.GSR = "ENABLED";
|
||||
FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610__i1.GSR = "ENABLED";
|
||||
FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
|
||||
defparam WRD_i7.GSR = "ENABLED";
|
||||
FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
|
||||
defparam WRD_i6.GSR = "ENABLED";
|
||||
FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
|
||||
defparam WRD_i5.GSR = "ENABLED";
|
||||
FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
|
||||
defparam WRD_i4.GSR = "ENABLED";
|
||||
FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
|
||||
defparam WRD_i3.GSR = "ENABLED";
|
||||
FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
|
||||
defparam WRD_i2.GSR = "ENABLED";
|
||||
FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5])
|
||||
defparam WRD_i1.GSR = "ENABLED";
|
||||
FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i9.GSR = "ENABLED";
|
||||
FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i8.GSR = "ENABLED";
|
||||
FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i7.GSR = "ENABLED";
|
||||
FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i6.GSR = "ENABLED";
|
||||
FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i5.GSR = "ENABLED";
|
||||
FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i4.GSR = "ENABLED";
|
||||
FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i3.GSR = "ENABLED";
|
||||
FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i2.GSR = "ENABLED";
|
||||
FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam RowA_i1.GSR = "ENABLED";
|
||||
FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
|
||||
defparam Bank_i7.GSR = "ENABLED";
|
||||
LUT4 i2_3_lut_3_lut (.A(nFWE_c), .B(Din_c_5), .C(Din_c_3), .Z(n2180)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
|
||||
defparam i2_3_lut_3_lut.init = 16'h4040;
|
||||
LUT4 i1_2_lut_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), .Z(n6_adj_2)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31])
|
||||
defparam i1_2_lut_3_lut.init = 16'h1010;
|
||||
LUT4 RASr2_I_0_1_lut_rep_25 (.A(RASr2), .Z(n2374)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46])
|
||||
defparam RASr2_I_0_1_lut_rep_25.init = 16'h5555;
|
||||
LUT4 i1_4_lut_4_lut_adj_12 (.A(RASr2), .B(n6_adj_3), .C(nRowColSel_N_32),
|
||||
.D(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46])
|
||||
defparam i1_4_lut_4_lut_adj_12.init = 16'hff40;
|
||||
LUT4 i1_4_lut_adj_13 (.A(Din_c_2), .B(n2055), .C(MAin_c_0), .D(n2362),
|
||||
.Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
|
||||
defparam i1_4_lut_adj_13.init = 16'h0004;
|
||||
FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
|
||||
defparam Bank_i6.GSR = "ENABLED";
|
||||
FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
|
||||
defparam Bank_i5.GSR = "ENABLED";
|
||||
FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
|
||||
defparam Bank_i4.GSR = "ENABLED";
|
||||
FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
|
||||
defparam Bank_i3.GSR = "ENABLED";
|
||||
FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
|
||||
defparam Bank_i2.GSR = "ENABLED";
|
||||
FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5])
|
||||
defparam Bank_i1.GSR = "ENABLED";
|
||||
CCU2D FS_610_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1993),
|
||||
.COUT(n1994), .S0(n92), .S1(n91)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_5.INIT0 = 16'hfaaa;
|
||||
defparam FS_610_add_4_5.INIT1 = 16'hfaaa;
|
||||
defparam FS_610_add_4_5.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_5.INJECT1_1 = "NO";
|
||||
BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
|
||||
LUT4 i2_3_lut_4_lut_adj_14 (.A(n2369), .B(n26), .C(n2180), .D(n2204),
|
||||
.Z(PHI2_N_120_enable_8)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
|
||||
defparam i2_3_lut_4_lut_adj_14.init = 16'h2000;
|
||||
BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
|
||||
BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
|
||||
BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
|
||||
BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
|
||||
LUT4 i1_2_lut_3_lut_adj_15 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5),
|
||||
.Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31])
|
||||
defparam i1_2_lut_3_lut_adj_15.init = 16'hfefe;
|
||||
BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
|
||||
BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16])
|
||||
OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19])
|
||||
OB LED_pad (.I(LED_c), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12])
|
||||
OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22])
|
||||
OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22])
|
||||
OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18])
|
||||
OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17])
|
||||
OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17])
|
||||
OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49])
|
||||
OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28])
|
||||
OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39])
|
||||
OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21])
|
||||
OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14])
|
||||
OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19])
|
||||
OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19])
|
||||
OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19])
|
||||
IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12])
|
||||
IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18])
|
||||
IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18])
|
||||
IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18])
|
||||
IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
|
||||
IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
|
||||
IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
|
||||
IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
|
||||
IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
|
||||
IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
|
||||
IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
|
||||
IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17])
|
||||
IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13])
|
||||
IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
|
||||
IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12])
|
||||
IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12])
|
||||
IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14])
|
||||
CCU2D FS_610_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
|
||||
.A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1999),
|
||||
.COUT(n2000), .S0(n80), .S1(n79)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam FS_610_add_4_17.INIT0 = 16'hfaaa;
|
||||
defparam FS_610_add_4_17.INIT1 = 16'hfaaa;
|
||||
defparam FS_610_add_4_17.INJECT1_0 = "NO";
|
||||
defparam FS_610_add_4_17.INJECT1_1 = "NO";
|
||||
LUT4 i1_2_lut_rep_14_3_lut (.A(n2369), .B(n26), .C(nFWE_c), .Z(n2363)) /* synthesis lut_function=((B+(C))+!A) */ ;
|
||||
defparam i1_2_lut_rep_14_3_lut.init = 16'hfdfd;
|
||||
LUT4 i1_2_lut_rep_13_3_lut (.A(n2369), .B(n26), .C(MAin_c_1), .Z(n2362)) /* synthesis lut_function=((B+!(C))+!A) */ ;
|
||||
defparam i1_2_lut_rep_13_3_lut.init = 16'hdfdf;
|
||||
LUT4 i2010_3_lut_3_lut (.A(nCRAS_c), .B(LEDEN), .C(CBR), .Z(LED_c)) /* synthesis lut_function=(A+((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[17:23])
|
||||
defparam i2010_3_lut_3_lut.init = 16'hfbfb;
|
||||
LUT4 i5_3_lut (.A(FS[3]), .B(FS[9]), .C(FS[6]), .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ;
|
||||
defparam i5_3_lut.init = 16'hfefe;
|
||||
LUT4 i4_4_lut_adj_16 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32),
|
||||
.D(n6), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
|
||||
defparam i4_4_lut_adj_16.init = 16'hfffe;
|
||||
LUT4 i4_4_lut_adj_17 (.A(n7), .B(FS[8]), .C(FS[10]), .D(n10), .Z(n2174)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i4_4_lut_adj_17.init = 16'h0002;
|
||||
LUT4 i34_4_lut (.A(n7_adj_5), .B(ADSubmitted), .C(C1Submitted_N_237),
|
||||
.D(n2363), .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;
|
||||
defparam i34_4_lut.init = 16'hc0c5;
|
||||
LUT4 i13_3_lut (.A(MAin_c_0), .B(n2210), .C(MAin_c_1), .Z(n7_adj_5)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ;
|
||||
defparam i13_3_lut.init = 16'hc5c5;
|
||||
LUT4 i1_2_lut_4_lut (.A(FS[11]), .B(n2368), .C(InitReady), .D(FS[10]),
|
||||
.Z(n64)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
|
||||
defparam i1_2_lut_4_lut.init = 16'hfffe;
|
||||
LUT4 nRCS_N_137_I_0_4_lut (.A(nRCS_N_137), .B(n2379), .C(Ready), .D(nRowColSel_N_35),
|
||||
.Z(nRRAS_N_156)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
|
||||
defparam nRCS_N_137_I_0_4_lut.init = 16'h3afa;
|
||||
LUT4 i3_4_lut_adj_18 (.A(Din_c_5), .B(n2228), .C(n2183), .D(n2370),
|
||||
.Z(n2055)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24])
|
||||
defparam i3_4_lut_adj_18.init = 16'h1000;
|
||||
LUT4 i1930_2_lut (.A(nFWE_c), .B(Din_c_4), .Z(n2228)) /* synthesis lut_function=(A+(B)) */ ;
|
||||
defparam i1930_2_lut.init = 16'heeee;
|
||||
LUT4 i1110_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n2365), .C(C1Submitted),
|
||||
.D(MAin_c_1), .Z(n1398)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ;
|
||||
defparam i1110_2_lut_3_lut_4_lut.init = 16'he0f0;
|
||||
LUT4 i1_2_lut_adj_19 (.A(FS[11]), .B(FS[6]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i1_2_lut_adj_19.init = 16'h8888;
|
||||
LUT4 i2_4_lut_adj_20 (.A(n2375), .B(FS[7]), .C(FS[9]), .D(FS[5]),
|
||||
.Z(n7)) /* synthesis lut_function=(!(A+(B (C)+!B !(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i2_4_lut_adj_20.init = 16'h1404;
|
||||
LUT4 i1417_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ;
|
||||
defparam i1417_2_lut.init = 16'heeee;
|
||||
LUT4 i2_4_lut_adj_21 (.A(n2228), .B(CmdEnable), .C(n1277), .D(n1314),
|
||||
.Z(PHI2_N_120_enable_3)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
|
||||
defparam i2_4_lut_adj_21.init = 16'h0004;
|
||||
LUT4 i3_4_lut_adj_22 (.A(Din_c_5), .B(n2191), .C(C1Submitted), .D(n2208),
|
||||
.Z(n2210)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
|
||||
defparam i3_4_lut_adj_22.init = 16'h0800;
|
||||
LUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n2227)) /* synthesis lut_function=(A+!(B)) */ ;
|
||||
defparam i1_2_lut_adj_23.init = 16'hbbbb;
|
||||
FD1P3AX InitReady_394 (.D(n2447), .SP(RCLK_c_enable_28), .CK(RCLK_c),
|
||||
.Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5])
|
||||
defparam InitReady_394.GSR = "ENABLED";
|
||||
LUT4 nRCS_I_0_448_3_lut (.A(nRCS_N_137), .B(nRCS_N_141), .C(Ready),
|
||||
.Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6])
|
||||
defparam nRCS_I_0_448_3_lut.init = 16'hcaca;
|
||||
LUT4 i1969_2_lut_3_lut_4_lut (.A(FS[12]), .B(FS[14]), .C(FS[11]),
|
||||
.D(n10), .Z(n2267)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i1969_2_lut_3_lut_4_lut.init = 16'hffef;
|
||||
LUT4 i1_2_lut_rep_19_3_lut (.A(FS[12]), .B(FS[14]), .C(n10), .Z(n2368)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i1_2_lut_rep_19_3_lut.init = 16'hfefe;
|
||||
LUT4 i2_3_lut_4_lut_adj_24 (.A(CBR), .B(CASr3), .C(FWEr), .D(CASr2),
|
||||
.Z(nRCS_N_146)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam i2_3_lut_4_lut_adj_24.init = 16'h1000;
|
||||
LUT4 i3_2_lut_rep_26 (.A(FS[12]), .B(FS[14]), .Z(n2375)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13])
|
||||
defparam i3_2_lut_rep_26.init = 16'heeee;
|
||||
LUT4 i1_2_lut_rep_27 (.A(CBR), .B(CASr3), .Z(n2376)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5])
|
||||
defparam i1_2_lut_rep_27.init = 16'heeee;
|
||||
LUT4 i2_3_lut_rep_28 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), .Z(n2377)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47])
|
||||
defparam i2_3_lut_rep_28.init = 16'h2020;
|
||||
INV i2044 (.A(nCRAS_c), .Z(nCRAS_c__inv)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20])
|
||||
FD1S3IX S_FSM_i2 (.D(n1406), .CK(RCLK_c), .CD(n1408), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16])
|
||||
defparam S_FSM_i2.GSR = "ENABLED";
|
||||
INV i2045 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13])
|
||||
VLO i1 (.Z(GND_net));
|
||||
TSALL TSALL_INST (.TSALL(GND_net));
|
||||
PUR PUR_INST (.PUR(VCC_net));
|
||||
defparam PUR_INST.RST_PULSE = 1;
|
||||
LUT4 i1_2_lut_4_lut_adj_25 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted),
|
||||
.D(InitReady), .Z(RCLK_c_enable_10)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47])
|
||||
defparam i1_2_lut_4_lut_adj_25.init = 16'h20ff;
|
||||
LUT4 i1_2_lut_rep_29 (.A(FWEr), .B(CBR), .Z(n2378)) /* synthesis lut_function=(A+(B)) */ ;
|
||||
defparam i1_2_lut_rep_29.init = 16'heeee;
|
||||
LUT4 m1_lut (.Z(n2447)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
|
||||
defparam m1_lut.init = 16'hffff;
|
||||
LUT4 n8MEGEN_I_14_3_lut_4_lut (.A(InitReady), .B(n2367), .C(UFMSDO_c),
|
||||
.D(Cmdn8MEGEN), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (D)+!A !(B (C)+!B !(D))) */ ;
|
||||
defparam n8MEGEN_I_14_3_lut_4_lut.init = 16'hbf04;
|
||||
|
||||
endmodule
|
||||
//
|
||||
// Verilog Description of module TSALL
|
||||
// module not written out since it is a black-box.
|
||||
//
|
||||
|
||||
//
|
||||
// Verilog Description of module PUR
|
||||
// module not written out since it is a black-box.
|
||||
//
|
||||
|
||||
1111
CPLD/LCMXO2-1200HC/impl1/automake.log
Normal file
1111
CPLD/LCMXO2-1200HC/impl1/automake.log
Normal file
File diff suppressed because it is too large
Load Diff
9
CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
Normal file
9
CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
Normal file
File diff suppressed because one or more lines are too long
55
CPLD/LCMXO2-1200HC/impl1/impl1.xcf
Normal file
55
CPLD/LCMXO2-1200HC/impl1/impl1.xcf
Normal file
@ -0,0 +1,55 @@
|
||||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
|
||||
<ispXCF version="3.12">
|
||||
<Comment></Comment>
|
||||
<Chain>
|
||||
<Comm>JTAG</Comm>
|
||||
<Device>
|
||||
<SelectedProg value="TRUE"/>
|
||||
<Pos>1</Pos>
|
||||
<Vendor>Lattice</Vendor>
|
||||
<Family>MachXO2</Family>
|
||||
<Name>LCMXO2-1200HC</Name>
|
||||
<IDCode>0x012ba043</IDCode>
|
||||
<Package>All</Package>
|
||||
<PON>LCMXO2-1200HC</PON>
|
||||
<Bypass>
|
||||
<InstrLen>8</InstrLen>
|
||||
<InstrVal>11111111</InstrVal>
|
||||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed</File>
|
||||
<FileTime>08/15/23 05:01:25</FileTime>
|
||||
<JedecChecksum>0x680B</JedecChecksum>
|
||||
<Operation>FLASH Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<IOState>HighZ</IOState>
|
||||
<PreloadLength>208</PreloadLength>
|
||||
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
|
||||
<TCKFrequency>1.000000 MHz</TCKFrequency>
|
||||
<Usercode>0x00000000</Usercode>
|
||||
<AccessMode>FLASH</AccessMode>
|
||||
</Option>
|
||||
</Device>
|
||||
</Chain>
|
||||
<ProjectOptions>
|
||||
<Program>SEQUENTIAL</Program>
|
||||
<Process>ENTIRED CHAIN</Process>
|
||||
<OperationOverride>No Override</OperationOverride>
|
||||
<StartTAP>TLR</StartTAP>
|
||||
<EndTAP>TLR</EndTAP>
|
||||
<VerifyUsercode value="FALSE"/>
|
||||
<TCKDelay>1</TCKDelay>
|
||||
</ProjectOptions>
|
||||
<CableOptions>
|
||||
<CableName>USB</CableName>
|
||||
<PortAdd>EzUSB-0</PortAdd>
|
||||
<USBID>\\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13#</USBID>
|
||||
<JTAGPinSetting>
|
||||
TRST ABSENT;
|
||||
ISPEN ABSENT;
|
||||
</JTAGPinSetting>
|
||||
</CableOptions>
|
||||
</ispXCF>
|
||||
139
CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior
Normal file
139
CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior
Normal file
@ -0,0 +1,139 @@
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2GS
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Tue Aug 15 05:03:41 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 0.891 4 0.676 4
|
||||
CROW[1] nCRAS F 0.281 4 1.216 4
|
||||
Din[0] PHI2 F 7.907 4 0.089 6
|
||||
Din[0] nCCAS F 1.465 4 0.158 4
|
||||
Din[1] PHI2 F 7.300 4 1.026 4
|
||||
Din[1] nCCAS F 1.035 4 0.527 4
|
||||
Din[2] PHI2 F 6.237 4 1.467 4
|
||||
Din[2] nCCAS F 1.719 4 -0.108 M
|
||||
Din[3] PHI2 F 6.623 4 0.176 6
|
||||
Din[3] nCCAS F 0.339 4 0.916 4
|
||||
Din[4] PHI2 F 6.902 4 1.033 4
|
||||
Din[4] nCCAS F 0.687 4 0.951 4
|
||||
Din[5] PHI2 F 6.837 4 1.369 4
|
||||
Din[5] nCCAS F 2.810 4 -0.220 M
|
||||
Din[6] PHI2 F 7.648 4 -0.050 M
|
||||
Din[6] nCCAS F 1.281 4 0.266 4
|
||||
Din[7] PHI2 F 7.823 4 -0.159 M
|
||||
Din[7] nCCAS F 1.810 4 -0.096 M
|
||||
MAin[0] PHI2 F 6.751 4 -0.273 M
|
||||
MAin[0] nCRAS F 1.765 4 -0.033 4
|
||||
MAin[1] PHI2 F 5.718 4 0.117 M
|
||||
MAin[1] nCRAS F 1.814 4 -0.051 M
|
||||
MAin[2] PHI2 F 5.759 4 -0.021 M
|
||||
MAin[2] nCRAS F 1.323 4 0.309 4
|
||||
MAin[3] PHI2 F 6.165 4 -0.235 M
|
||||
MAin[3] nCRAS F 0.694 4 0.836 4
|
||||
MAin[4] PHI2 F 5.236 4 -0.147 M
|
||||
MAin[4] nCRAS F 0.730 4 0.835 4
|
||||
MAin[5] PHI2 F 6.024 4 0.135 M
|
||||
MAin[5] nCRAS F 0.734 4 0.868 4
|
||||
MAin[6] PHI2 F 5.689 4 -0.277 M
|
||||
MAin[6] nCRAS F 0.288 4 1.210 4
|
||||
MAin[7] PHI2 F 6.398 4 -0.307 M
|
||||
MAin[7] nCRAS F 1.215 4 0.401 4
|
||||
MAin[8] nCRAS F 0.817 4 0.727 4
|
||||
MAin[9] nCRAS F 0.941 4 0.601 4
|
||||
PHI2 RCLK R 0.771 4 1.143 4
|
||||
UFMSDO RCLK R -0.238 M 2.305 4
|
||||
nCCAS RCLK R 1.651 4 0.388 4
|
||||
nCCAS nCRAS F 5.028 4 -0.828 M
|
||||
nCRAS RCLK R 0.593 4 1.309 4
|
||||
nFWE PHI2 F 5.741 4 0.781 4
|
||||
nFWE nCRAS F 0.578 4 0.996 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 14.758 4 4.129 M
|
||||
LED nCRAS F 12.396 4 3.434 M
|
||||
RA[0] RCLK R 13.780 4 3.894 M
|
||||
RA[0] nCRAS F 11.795 4 3.277 M
|
||||
RA[10] RCLK R 12.425 4 3.587 M
|
||||
RA[11] PHI2 R 10.432 4 3.084 M
|
||||
RA[1] RCLK R 15.081 4 4.198 M
|
||||
RA[1] nCRAS F 12.364 4 3.447 M
|
||||
RA[2] RCLK R 14.518 4 4.082 M
|
||||
RA[2] nCRAS F 11.696 4 3.275 M
|
||||
RA[3] RCLK R 13.789 4 3.897 M
|
||||
RA[3] nCRAS F 12.223 4 3.392 M
|
||||
RA[4] RCLK R 15.175 4 4.228 M
|
||||
RA[4] nCRAS F 12.424 4 3.464 M
|
||||
RA[5] RCLK R 13.789 4 3.897 M
|
||||
RA[5] nCRAS F 12.359 4 3.437 M
|
||||
RA[6] RCLK R 15.420 4 4.299 M
|
||||
RA[6] nCRAS F 12.865 4 3.560 M
|
||||
RA[7] RCLK R 14.672 4 4.127 M
|
||||
RA[7] nCRAS F 12.253 4 3.386 M
|
||||
RA[8] RCLK R 14.952 4 4.191 M
|
||||
RA[8] nCRAS F 12.244 4 3.383 M
|
||||
RA[9] RCLK R 14.092 4 3.978 M
|
||||
RA[9] nCRAS F 13.164 4 3.653 M
|
||||
RBA[0] nCRAS F 10.278 4 2.970 M
|
||||
RBA[1] nCRAS F 10.474 4 3.030 M
|
||||
RCKE RCLK R 12.407 4 3.610 M
|
||||
RDQMH RCLK R 13.754 4 3.857 M
|
||||
RDQML RCLK R 13.482 4 3.833 M
|
||||
RD[0] nCCAS F 10.515 4 3.076 M
|
||||
RD[1] nCCAS F 10.118 4 2.965 M
|
||||
RD[2] nCCAS F 9.759 4 2.886 M
|
||||
RD[3] nCCAS F 9.798 4 2.878 M
|
||||
RD[4] nCCAS F 10.979 4 3.178 M
|
||||
RD[5] nCCAS F 11.063 4 3.207 M
|
||||
RD[6] nCCAS F 10.317 4 3.018 M
|
||||
RD[7] nCCAS F 10.232 4 2.986 M
|
||||
UFMCLK RCLK R 12.402 4 3.606 M
|
||||
UFMSDI RCLK R 11.975 4 3.501 M
|
||||
nRCAS RCLK R 12.350 4 3.564 M
|
||||
nRCS RCLK R 11.923 4 3.459 M
|
||||
nRRAS RCLK R 11.995 4 3.494 M
|
||||
nRWE RCLK R 11.975 4 3.501 M
|
||||
nUFMCS RCLK R 11.818 4 3.434 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
13
CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd
Normal file
13
CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd
Normal file
@ -0,0 +1,13 @@
|
||||
[ActiveSupport TRCE]
|
||||
; Setup Analysis
|
||||
Fmax_0 = 174.216 MHz (299.401 MHz);
|
||||
Fmax_1 = 67.833 MHz (99.079 MHz);
|
||||
Failed = 2 (Total 2);
|
||||
Clock_ports = 4;
|
||||
Clock_nets = 4;
|
||||
; Hold Analysis
|
||||
Fmax_0 = 0.304 ns (0.000 ns);
|
||||
Fmax_1 = 0.379 ns (0.000 ns);
|
||||
Failed = 0 (Total 2);
|
||||
Clock_ports = 4;
|
||||
Clock_nets = 4;
|
||||
239
CPLD/LCMXO2-1200HC/impl1/synthesis.log
Normal file
239
CPLD/LCMXO2-1200HC/impl1/synthesis.log
Normal file
@ -0,0 +1,239 @@
|
||||
synthesis: version Diamond (64-bit) 3.12.1.454
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:25 2023
|
||||
|
||||
|
||||
Command Line: synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
Synthesis options:
|
||||
The -a option is MachXO2.
|
||||
The -s option is 4.
|
||||
The -t option is TQFP100.
|
||||
The -d option is LCMXO2-1200HC.
|
||||
Using package TQFP100.
|
||||
Using performance grade 4.
|
||||
|
||||
|
||||
##########################################################
|
||||
|
||||
### Lattice Family : MachXO2
|
||||
|
||||
### Device : LCMXO2-1200HC
|
||||
|
||||
### Package : TQFP100
|
||||
|
||||
### Speed : 4
|
||||
|
||||
##########################################################
|
||||
|
||||
|
||||
|
||||
INFO - synthesis: User-Selected Strategy Settings
|
||||
Optimization goal = Balanced
|
||||
Top-level module name = RAM2GS.
|
||||
Target frequency = 200.000000 MHz.
|
||||
Maximum fanout = 1000.
|
||||
Timing path count = 3
|
||||
BRAM utilization = 100.000000 %
|
||||
DSP usage = true
|
||||
DSP utilization = 100.000000 %
|
||||
fsm_encoding_style = auto
|
||||
resolve_mixed_drivers = 0
|
||||
fix_gated_clocks = 1
|
||||
|
||||
Mux style = Auto
|
||||
Use Carry Chain = true
|
||||
carry_chain_length = 0
|
||||
Loop Limit = 1950.
|
||||
Use IO Insertion = TRUE
|
||||
Use IO Reg = AUTO
|
||||
|
||||
Resource Sharing = TRUE
|
||||
Propagate Constants = TRUE
|
||||
Remove Duplicate Registers = TRUE
|
||||
force_gsr = auto
|
||||
ROM style = auto
|
||||
RAM style = auto
|
||||
The -comp option is FALSE.
|
||||
The -syn option is FALSE.
|
||||
-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
|
||||
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
|
||||
-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added)
|
||||
-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
|
||||
Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
|
||||
NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd
|
||||
-sdc option: SDC file input not used.
|
||||
-lpf option: Output file option is ON.
|
||||
Hardtimer checking is enabled (default). The -dt option is not used.
|
||||
The -r option is OFF. [ Remove LOC Properties is OFF. ]
|
||||
Technology check ok...
|
||||
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Compile design.
|
||||
Compile Design Begin
|
||||
Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Top module name (Verilog): RAM2GS
|
||||
INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
|
||||
WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
|
||||
WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
|
||||
WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Top-level module name = RAM2GS.
|
||||
INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
0000 -> 0000000000000001
|
||||
|
||||
0001 -> 0000000000000010
|
||||
|
||||
0010 -> 0000000000000100
|
||||
|
||||
0011 -> 0000000000001000
|
||||
|
||||
0100 -> 0000000000010000
|
||||
|
||||
0101 -> 0000000000100000
|
||||
|
||||
0110 -> 0000000001000000
|
||||
|
||||
0111 -> 0000000010000000
|
||||
|
||||
1000 -> 0000000100000000
|
||||
|
||||
1001 -> 0000001000000000
|
||||
|
||||
1010 -> 0000010000000000
|
||||
|
||||
1011 -> 0000100000000000
|
||||
|
||||
1100 -> 0001000000000000
|
||||
|
||||
1101 -> 0010000000000000
|
||||
|
||||
1110 -> 0100000000000000
|
||||
|
||||
1111 -> 1000000000000000
|
||||
|
||||
INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
00 -> 0001
|
||||
|
||||
01 -> 0010
|
||||
|
||||
10 -> 0100
|
||||
|
||||
11 -> 1000
|
||||
|
||||
|
||||
|
||||
|
||||
GSR will not be inferred because no asynchronous signal was found in the netlist.
|
||||
WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
|
||||
Applying 200.000000 MHz constraint to all clocks
|
||||
|
||||
WARNING - synthesis: No user .sdc file.
|
||||
Results of NGD DRC are available in RAM2GS_drc.log.
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
All blocks are expanded and NGD expansion is successful.
|
||||
Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd.
|
||||
|
||||
################### Begin Area Report (RAM2GS)######################
|
||||
Number of register bits => 102 of 1520 (6 % )
|
||||
BB => 8
|
||||
CCU2D => 10
|
||||
FD1P3AX => 29
|
||||
FD1P3AY => 5
|
||||
FD1P3IX => 3
|
||||
FD1S3AX => 47
|
||||
FD1S3IX => 14
|
||||
FD1S3JX => 4
|
||||
GSR => 1
|
||||
IB => 26
|
||||
INV => 3
|
||||
LUT4 => 122
|
||||
OB => 33
|
||||
PFUMX => 1
|
||||
################### End Area Report ##################
|
||||
|
||||
################### Begin BlackBox Report ######################
|
||||
TSALL => 1
|
||||
################### End BlackBox Report ##################
|
||||
|
||||
################### Begin Clock Report ######################
|
||||
Clock Nets
|
||||
Number of Clocks: 4
|
||||
Net : RCLK_c, loads : 62
|
||||
Net : PHI2_c, loads : 11
|
||||
Net : nCCAS_c, loads : 2
|
||||
Net : nCRAS_c, loads : 2
|
||||
Clock Enable Nets
|
||||
Number of Clock Enables: 14
|
||||
Top 10 highest fanout Clock Enables:
|
||||
Net : RCLK_c_enable_27, loads : 16
|
||||
Net : RCLK_c_enable_6, loads : 4
|
||||
Net : PHI2_N_120_enable_8, loads : 3
|
||||
Net : RCLK_c_enable_10, loads : 3
|
||||
Net : RCLK_c_enable_5, loads : 2
|
||||
Net : PHI2_N_120_enable_3, loads : 1
|
||||
Net : Ready_N_292, loads : 1
|
||||
Net : PHI2_N_120_enable_2, loads : 1
|
||||
Net : RCLK_c_enable_15, loads : 1
|
||||
Net : PHI2_N_120_enable_6, loads : 1
|
||||
Highest fanout non-clock nets
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net : RCLK_c_enable_27, loads : 16
|
||||
Net : InitReady, loads : 15
|
||||
Net : nCRAS_c__inv, loads : 15
|
||||
Net : RASr2, loads : 14
|
||||
Net : nRowColSel_N_35, loads : 13
|
||||
Net : n2380, loads : 13
|
||||
Net : nRowColSel, loads : 12
|
||||
Net : Ready, loads : 12
|
||||
Net : Din_c_4, loads : 10
|
||||
Net : MAin_c_1, loads : 10
|
||||
################### End Clock Report ##################
|
||||
|
||||
Timing Report Summary
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 constraints not met.
|
||||
|
||||
|
||||
Peak Memory Usage: 55.238 MB
|
||||
|
||||
--------------------------------------------------------------
|
||||
Elapsed CPU time for LSE flow : 0.891 secs
|
||||
--------------------------------------------------------------
|
||||
304
CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html
Normal file
304
CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html
Normal file
@ -0,0 +1,304 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Synthesis and Ngdbuild Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Syn"></A><B><U><big>Synthesis and Ngdbuild Report</big></U></B>
|
||||
synthesis: version Diamond (64-bit) 3.12.1.454
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:25 2023
|
||||
|
||||
|
||||
Command Line: synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
Synthesis options:
|
||||
The -a option is MachXO2.
|
||||
The -s option is 4.
|
||||
The -t option is TQFP100.
|
||||
The -d option is LCMXO2-1200HC.
|
||||
Using package TQFP100.
|
||||
Using performance grade 4.
|
||||
|
||||
|
||||
##########################################################
|
||||
|
||||
### Lattice Family : MachXO2
|
||||
|
||||
### Device : LCMXO2-1200HC
|
||||
|
||||
### Package : TQFP100
|
||||
|
||||
### Speed : 4
|
||||
|
||||
##########################################################
|
||||
|
||||
|
||||
|
||||
INFO - synthesis: User-Selected Strategy Settings
|
||||
Optimization goal = Balanced
|
||||
Top-level module name = RAM2GS.
|
||||
Target frequency = 200.000000 MHz.
|
||||
Maximum fanout = 1000.
|
||||
Timing path count = 3
|
||||
BRAM utilization = 100.000000 %
|
||||
DSP usage = true
|
||||
DSP utilization = 100.000000 %
|
||||
fsm_encoding_style = auto
|
||||
resolve_mixed_drivers = 0
|
||||
fix_gated_clocks = 1
|
||||
|
||||
Mux style = Auto
|
||||
Use Carry Chain = true
|
||||
carry_chain_length = 0
|
||||
Loop Limit = 1950.
|
||||
Use IO Insertion = TRUE
|
||||
Use IO Reg = AUTO
|
||||
|
||||
Resource Sharing = TRUE
|
||||
Propagate Constants = TRUE
|
||||
Remove Duplicate Registers = TRUE
|
||||
force_gsr = auto
|
||||
ROM style = auto
|
||||
RAM style = auto
|
||||
The -comp option is FALSE.
|
||||
The -syn option is FALSE.
|
||||
-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
|
||||
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
|
||||
-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added)
|
||||
-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
|
||||
Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
|
||||
NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd
|
||||
-sdc option: SDC file input not used.
|
||||
-lpf option: Output file option is ON.
|
||||
Hardtimer checking is enabled (default). The -dt option is not used.
|
||||
The -r option is OFF. [ Remove LOC Properties is OFF. ]
|
||||
Technology check ok...
|
||||
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Compile design.
|
||||
Compile Design Begin
|
||||
Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Top module name (Verilog): RAM2GS
|
||||
INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
|
||||
WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
|
||||
WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
|
||||
WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Top-level module name = RAM2GS.
|
||||
INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
0000 -> 0000000000000001
|
||||
|
||||
0001 -> 0000000000000010
|
||||
|
||||
0010 -> 0000000000000100
|
||||
|
||||
0011 -> 0000000000001000
|
||||
|
||||
0100 -> 0000000000010000
|
||||
|
||||
0101 -> 0000000000100000
|
||||
|
||||
0110 -> 0000000001000000
|
||||
|
||||
0111 -> 0000000010000000
|
||||
|
||||
1000 -> 0000000100000000
|
||||
|
||||
1001 -> 0000001000000000
|
||||
|
||||
1010 -> 0000010000000000
|
||||
|
||||
1011 -> 0000100000000000
|
||||
|
||||
1100 -> 0001000000000000
|
||||
|
||||
1101 -> 0010000000000000
|
||||
|
||||
1110 -> 0100000000000000
|
||||
|
||||
1111 -> 1000000000000000
|
||||
|
||||
INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
00 -> 0001
|
||||
|
||||
01 -> 0010
|
||||
|
||||
10 -> 0100
|
||||
|
||||
11 -> 1000
|
||||
|
||||
|
||||
|
||||
|
||||
GSR will not be inferred because no asynchronous signal was found in the netlist.
|
||||
WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
|
||||
Applying 200.000000 MHz constraint to all clocks
|
||||
|
||||
WARNING - synthesis: No user .sdc file.
|
||||
Results of NGD DRC are available in RAM2GS_drc.log.
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
All blocks are expanded and NGD expansion is successful.
|
||||
Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd.
|
||||
|
||||
################### Begin Area Report (RAM2GS)######################
|
||||
Number of register bits => 102 of 1520 (6 % )
|
||||
BB => 8
|
||||
CCU2D => 10
|
||||
FD1P3AX => 29
|
||||
FD1P3AY => 5
|
||||
FD1P3IX => 3
|
||||
FD1S3AX => 47
|
||||
FD1S3IX => 14
|
||||
FD1S3JX => 4
|
||||
GSR => 1
|
||||
IB => 26
|
||||
INV => 3
|
||||
LUT4 => 122
|
||||
OB => 33
|
||||
PFUMX => 1
|
||||
################### End Area Report ##################
|
||||
|
||||
################### Begin BlackBox Report ######################
|
||||
TSALL => 1
|
||||
################### End BlackBox Report ##################
|
||||
|
||||
################### Begin Clock Report ######################
|
||||
Clock Nets
|
||||
Number of Clocks: 4
|
||||
Net : RCLK_c, loads : 62
|
||||
Net : PHI2_c, loads : 11
|
||||
Net : nCCAS_c, loads : 2
|
||||
Net : nCRAS_c, loads : 2
|
||||
Clock Enable Nets
|
||||
Number of Clock Enables: 14
|
||||
Top 10 highest fanout Clock Enables:
|
||||
Net : RCLK_c_enable_27, loads : 16
|
||||
Net : RCLK_c_enable_6, loads : 4
|
||||
Net : PHI2_N_120_enable_8, loads : 3
|
||||
Net : RCLK_c_enable_10, loads : 3
|
||||
Net : RCLK_c_enable_5, loads : 2
|
||||
Net : PHI2_N_120_enable_3, loads : 1
|
||||
Net : Ready_N_292, loads : 1
|
||||
Net : PHI2_N_120_enable_2, loads : 1
|
||||
Net : RCLK_c_enable_15, loads : 1
|
||||
Net : PHI2_N_120_enable_6, loads : 1
|
||||
Highest fanout non-clock nets
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net : RCLK_c_enable_27, loads : 16
|
||||
Net : InitReady, loads : 15
|
||||
Net : nCRAS_c__inv, loads : 15
|
||||
Net : RASr2, loads : 14
|
||||
Net : nRowColSel_N_35, loads : 13
|
||||
Net : n2380, loads : 13
|
||||
Net : nRowColSel, loads : 12
|
||||
Net : Ready, loads : 12
|
||||
Net : Din_c_4, loads : 10
|
||||
Net : MAin_c_1, loads : 10
|
||||
################### End Clock Report ##################
|
||||
|
||||
<A name="lse_trs"></A><B><U><big>Timing Report Summary</big></U></B>
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 constraints not met.
|
||||
|
||||
|
||||
Peak Memory Usage: 55.238 MB
|
||||
|
||||
--------------------------------------------------------------
|
||||
Elapsed CPU time for LSE flow : 0.891 secs
|
||||
--------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
250
CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list
Normal file
250
CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list
Normal file
@ -0,0 +1,250 @@
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v
|
||||
250
CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file
Normal file
250
CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file
Normal file
@ -0,0 +1,250 @@
|
||||
LSE_CPS_ID_1 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]"
|
||||
LSE_CPS_ID_2 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_3 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:186[13] 231[7]"
|
||||
LSE_CPS_ID_4 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]"
|
||||
LSE_CPS_ID_5 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]"
|
||||
LSE_CPS_ID_6 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_7 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_8 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_9 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_10 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_11 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_12 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_13 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]"
|
||||
LSE_CPS_ID_14 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_15 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_16 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]"
|
||||
LSE_CPS_ID_17 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_18 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_19 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:141[9] 144[5]"
|
||||
LSE_CPS_ID_20 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_21 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_22 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_23 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_24 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]"
|
||||
LSE_CPS_ID_25 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]"
|
||||
LSE_CPS_ID_26 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_27 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:255[14] 262[8]"
|
||||
LSE_CPS_ID_28 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]"
|
||||
LSE_CPS_ID_29 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_30 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_31 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_32 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_33 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_34 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_35 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]"
|
||||
LSE_CPS_ID_36 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:321[13] 335[7]"
|
||||
LSE_CPS_ID_37 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_38 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_39 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]"
|
||||
LSE_CPS_ID_40 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]"
|
||||
LSE_CPS_ID_41 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]"
|
||||
LSE_CPS_ID_42 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_43 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_44 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:99[22:51]"
|
||||
LSE_CPS_ID_45 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]"
|
||||
LSE_CPS_ID_46 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_47 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]"
|
||||
LSE_CPS_ID_48 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_49 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_50 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_51 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_52 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_53 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_54 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_55 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:168[14] 184[8]"
|
||||
LSE_CPS_ID_56 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_57 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]"
|
||||
LSE_CPS_ID_58 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]"
|
||||
LSE_CPS_ID_59 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]"
|
||||
LSE_CPS_ID_60 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]"
|
||||
LSE_CPS_ID_61 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_62 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_63 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:345[12] 409[6]"
|
||||
LSE_CPS_ID_64 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]"
|
||||
LSE_CPS_ID_65 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:58[17:46]"
|
||||
LSE_CPS_ID_66 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]"
|
||||
LSE_CPS_ID_67 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]"
|
||||
LSE_CPS_ID_68 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]"
|
||||
LSE_CPS_ID_69 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_70 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]"
|
||||
LSE_CPS_ID_71 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]"
|
||||
LSE_CPS_ID_72 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_73 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_74 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_75 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]"
|
||||
LSE_CPS_ID_76 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_77 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]"
|
||||
LSE_CPS_ID_78 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_79 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_80 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_81 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]"
|
||||
LSE_CPS_ID_82 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_83 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_84 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:86[13:15]"
|
||||
LSE_CPS_ID_85 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_86 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_87 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_88 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]"
|
||||
LSE_CPS_ID_89 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]"
|
||||
LSE_CPS_ID_90 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_91 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]"
|
||||
LSE_CPS_ID_92 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]"
|
||||
LSE_CPS_ID_93 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_94 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]"
|
||||
LSE_CPS_ID_95 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_96 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]"
|
||||
LSE_CPS_ID_97 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]"
|
||||
LSE_CPS_ID_98 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]"
|
||||
LSE_CPS_ID_99 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]"
|
||||
LSE_CPS_ID_100 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]"
|
||||
LSE_CPS_ID_101 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_102 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]"
|
||||
LSE_CPS_ID_103 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:15[12:17]"
|
||||
LSE_CPS_ID_104 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]"
|
||||
LSE_CPS_ID_105 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_106 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]"
|
||||
LSE_CPS_ID_107 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]"
|
||||
LSE_CPS_ID_108 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_109 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]"
|
||||
LSE_CPS_ID_110 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[27:31]"
|
||||
LSE_CPS_ID_111 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]"
|
||||
LSE_CPS_ID_112 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_113 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_114 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_115 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_116 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_117 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_118 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_119 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]"
|
||||
LSE_CPS_ID_120 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_121 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_122 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_123 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_124 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_125 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_126 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_127 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_128 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_129 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_130 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_131 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_132 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_133 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_134 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_135 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_136 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_137 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_138 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]"
|
||||
LSE_CPS_ID_139 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]"
|
||||
LSE_CPS_ID_140 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]"
|
||||
LSE_CPS_ID_141 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]"
|
||||
LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]"
|
||||
LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]"
|
||||
LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]"
|
||||
LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]"
|
||||
LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]"
|
||||
LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]"
|
||||
LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]"
|
||||
LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]"
|
||||
LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]"
|
||||
LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]"
|
||||
LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]"
|
||||
LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]"
|
||||
LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]"
|
||||
LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]"
|
||||
LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]"
|
||||
LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]"
|
||||
LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]"
|
||||
LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]"
|
||||
LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]"
|
||||
LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]"
|
||||
LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]"
|
||||
LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]"
|
||||
LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]"
|
||||
LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]"
|
||||
LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]"
|
||||
LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]"
|
||||
LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]"
|
||||
LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]"
|
||||
LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]"
|
||||
LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]"
|
||||
LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]"
|
||||
LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]"
|
||||
LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]"
|
||||
LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]"
|
||||
LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]"
|
||||
LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]"
|
||||
LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]"
|
||||
LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]"
|
||||
LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]"
|
||||
LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]"
|
||||
LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]"
|
||||
LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]"
|
||||
LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]"
|
||||
LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]"
|
||||
LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]"
|
||||
LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]"
|
||||
LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]"
|
||||
LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]"
|
||||
LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]"
|
||||
LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]"
|
||||
LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]"
|
||||
LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]"
|
||||
LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]"
|
||||
LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]"
|
||||
LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]"
|
||||
LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]"
|
||||
LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]"
|
||||
LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]"
|
||||
LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]"
|
||||
LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]"
|
||||
LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[17:23]"
|
||||
LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]"
|
||||
LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]"
|
||||
LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]"
|
||||
LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]"
|
||||
LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]"
|
||||
LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]"
|
||||
LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]"
|
||||
LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]"
|
||||
LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]"
|
||||
LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]"
|
||||
LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]"
|
||||
9
CPLD/LCMXO2-640HC/.run_manager.ini
Normal file
9
CPLD/LCMXO2-640HC/.run_manager.ini
Normal file
@ -0,0 +1,9 @@
|
||||
[Runmanager]
|
||||
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
|
||||
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
|
||||
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
|
||||
|
||||
[impl1%3CStrategy1%3E]
|
||||
isChecked=false
|
||||
isHidden=false
|
||||
isExpanded=false
|
||||
4
CPLD/LCMXO2-640HC/.setting.ini
Normal file
4
CPLD/LCMXO2-640HC/.setting.ini
Normal file
@ -0,0 +1,4 @@
|
||||
[General]
|
||||
Export.auto_tasks=Jedecgen
|
||||
PAR.auto_tasks=PARTrace, IOTiming
|
||||
Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile
|
||||
3
CPLD/LCMXO2-640HC/.spread_sheet.ini
Normal file
3
CPLD/LCMXO2-640HC/.spread_sheet.ini
Normal file
@ -0,0 +1,3 @@
|
||||
[General]
|
||||
COLUMN_POS_INFO_NAME_-1_0=Prioritize
|
||||
COLUMN_POS_INFO_NAME_-1_1=PIO Register
|
||||
76
CPLD/LCMXO2-640HC/.spreadsheet_view.ini
Normal file
76
CPLD/LCMXO2-640HC/.spreadsheet_view.ini
Normal file
@ -0,0 +1,76 @@
|
||||
[General]
|
||||
pin_sort_type=0
|
||||
pin_sort_ascending=true
|
||||
sig_sort_type=0
|
||||
sig_sort_ascending=true
|
||||
active_Sheet=Port Assignments
|
||||
|
||||
[Port%20Assignments]
|
||||
Name="164,0"
|
||||
Group%20By="84,1"
|
||||
Pin="50,2"
|
||||
BANK="62,3"
|
||||
BANK_VCC="90,4"
|
||||
VREF="60,5"
|
||||
IO_TYPE="147,6"
|
||||
PULLMODE="97,7"
|
||||
DRIVE="67,8"
|
||||
SLEWRATE="92,9"
|
||||
CLAMP="71,10"
|
||||
OPENDRAIN="97,11"
|
||||
DIFFRESISTOR="114,12"
|
||||
DIFFDRIVE="92,13"
|
||||
HYSTERESIS="101,14"
|
||||
Outload%20%28pF%29="103,15"
|
||||
MaxSkew="87,16"
|
||||
Clock%20Load%20Only="121,17"
|
||||
SwitchingID="100,18"
|
||||
Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
|
||||
Power%20plane%20PCB%20noise%20%28mV%29="190,20"
|
||||
SSO%20Allowance%28%25%29="138,21"
|
||||
sort_columns="Name,Ascending"
|
||||
|
||||
[Pin%20Assignments]
|
||||
Pin="90,0"
|
||||
Pad%20Name="89,1"
|
||||
Dual%20Function="158,2"
|
||||
Polarity="77,3"
|
||||
BANK="0,4"
|
||||
BANK_VCC="90,5"
|
||||
IO_TYPE="147,6"
|
||||
Signal%20Name="123,7"
|
||||
Signal%20Type="115,8"
|
||||
sort_columns="Pin,Ascending"
|
||||
|
||||
[Clock%20Resource]
|
||||
Clock%20Type="100,ELLIPSIS"
|
||||
Clock%20Name="100,ELLIPSIS"
|
||||
Selection="100,ELLIPSIS"
|
||||
|
||||
[Global%20Preferences]
|
||||
Preference%20Name="231,ELLIPSIS"
|
||||
Preference%20Value="236,ELLIPSIS"
|
||||
|
||||
[Cell%20Mapping]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Din\Dout="100,ELLIPSIS"
|
||||
PIO%20Register="100,ELLIPSIS"
|
||||
|
||||
[Route%20Priority]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Prioritize="100,ELLIPSIS"
|
||||
|
||||
[Timing%20Preferences]
|
||||
Preference%20Name="129,ELLIPSIS"
|
||||
Preference%20Value="105,ELLIPSIS"
|
||||
Preference%20Unit="98,ELLIPSIS"
|
||||
|
||||
[Group]
|
||||
Group%20Type\Name="134,ELLIPSIS"
|
||||
Value="39,ELLIPSIS"
|
||||
|
||||
[Misc%20Preferences]
|
||||
Preference%20Name="117,ELLIPSIS"
|
||||
Preference%20Value="105,ELLIPSIS"
|
||||
1
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl
Normal file
1
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl
Normal file
@ -0,0 +1 @@
|
||||
VERSION=20110520
|
||||
17
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf
Normal file
17
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf
Normal file
@ -0,0 +1,17 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="RAM2GS_LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
|
||||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
|
||||
<Options def_top="RAM2GS"/>
|
||||
<Source name="../RAM2GS-SPI.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RAM2GS"/>
|
||||
</Source>
|
||||
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="RAM2GS_LCMXO2_640HC.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="RAM2GS_LCMXO2_640HC1.sty"/>
|
||||
</BaliProject>
|
||||
68
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
Normal file
68
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf
Normal file
@ -0,0 +1,68 @@
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "RCLK" SITE "62" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "UFMSDO" SITE "27" ;
|
||||
LOCATE COMP "nFWE" SITE "28" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "UFMCLK" SITE "29" ;
|
||||
LOCATE COMP "UFMSDI" SITE "30" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
205
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty
Normal file
205
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty
Normal file
@ -0,0 +1,205 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE strategy>
|
||||
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
|
||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
|
||||
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
82
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html
Normal file
82
CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html
Normal file
@ -0,0 +1,82 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn230815045824"></A><B><U><big>pn230815045824</big></U></B>
|
||||
#Start recording tcl command: 8/15/2023 04:58:13
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC
|
||||
RAM2GS_LCMXO2_1200HC
|
||||
#Start recording tcl command: 8/15/2023 04:58:24
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
|
||||
#Stop recording: 8/15/2023 04:58:24
|
||||
|
||||
|
||||
|
||||
<A name="pn230815050055"></A><B><U><big>pn230815050055</big></U></B>
|
||||
#Start recording tcl command: 8/15/2023 05:00:44
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
#Stop recording: 8/15/2023 05:00:55
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -0,0 +1,9 @@
|
||||
#Start recording tcl command: 8/15/2023 04:58:13
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC
|
||||
RAM2GS_LCMXO2_1200HC
|
||||
#Start recording tcl command: 8/15/2023 04:58:24
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
|
||||
#Stop recording: 8/15/2023 04:58:24
|
||||
@ -0,0 +1,4 @@
|
||||
#Start recording tcl command: 8/15/2023 05:00:44
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
#Stop recording: 8/15/2023 05:00:55
|
||||
3
CPLD/LCMXO2-640HC/hdlparser.log
Normal file
3
CPLD/LCMXO2-640HC/hdlparser.log
Normal file
@ -0,0 +1,3 @@
|
||||
-- all messages logged in file hdlparser.log
|
||||
-- Analyzing Verilog file 'C:/lscc/diamond/3.12/cae_library/synthesis/verilog/machxo2.v' (VERI-1482)
|
||||
-- Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v' (VERI-1482)
|
||||
48
CPLD/LCMXO2-640HC/impl1/.build_status
Normal file
48
CPLD/LCMXO2-640HC/impl1/.build_status
Normal file
@ -0,0 +1,48 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BuildStatus>
|
||||
<Strategy name="Strategy1">
|
||||
<Milestone name="Export" build_result="0" build_time="0">
|
||||
<Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692090221"/>
|
||||
</Milestone>
|
||||
<Milestone name="Map" build_result="2" build_time="1692090205">
|
||||
<Task name="Map" build_result="2" update_result="0" update_time="1692090205"/>
|
||||
<Task name="MapTrace" build_result="2" update_result="0" update_time="1692090205"/>
|
||||
<Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1692090206"/>
|
||||
<Task name="MapVHDLSimFile" build_result="2" update_result="0" update_time="1692090208"/>
|
||||
</Milestone>
|
||||
<Milestone name="PAR" build_result="2" build_time="1692090216">
|
||||
<Task name="PAR" build_result="2" update_result="0" update_time="1692090216"/>
|
||||
<Task name="PARTrace" build_result="2" update_result="0" update_time="1692090216"/>
|
||||
<Task name="IOTiming" build_result="2" update_result="0" update_time="1692090217"/>
|
||||
</Milestone>
|
||||
<Milestone name="Synthesis" build_result="2" build_time="1692090203">
|
||||
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1692090203"/>
|
||||
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1692090221"/>
|
||||
</Milestone>
|
||||
<Milestone name="TOOL_Report" build_result="0" build_time="0">
|
||||
<Task name="HDLE" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="BKM" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Report name=".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" last_build_time="1692090205" last_build_size="67964"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.bgn" last_build_time="1692090221" last_build_size="4423"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ior" last_build_time="1692090217" last_build_size="6867"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.jed" last_build_time="1692090221" last_build_size="177183"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.lsedata" last_build_time="1692090203" last_build_size="237766"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ncd" last_build_time="1692090215" last_build_size="194841"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ngd" last_build_time="1692090203" last_build_size="156242"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.tw1" last_build_time="1692090205" last_build_size="14596"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.twr" last_build_time="1692090216" last_build_size="88279"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_map.ncd" last_build_time="1692090204" last_build_size="137575"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf" last_build_time="1692090207" last_build_size="118434"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvho.vho" last_build_time="1692090207" last_build_size="973589"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf" last_build_time="1692090206" last_build_size="117902"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvo.vo" last_build_time="1692090206" last_build_size="127955"/>
|
||||
</Strategy>
|
||||
</BuildStatus>
|
||||
BIN
CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb
Normal file
BIN
CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb
Normal file
Binary file not shown.
BIN
CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb
Normal file
BIN
CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb
Normal file
Binary file not shown.
BIN
CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb
Normal file
BIN
CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb
Normal file
Binary file not shown.
1
CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
Normal file
1
CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt
Normal file
@ -0,0 +1 @@
|
||||
RAM2GS_rtl.vdb
|
||||
75
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
Normal file
75
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt
Normal file
@ -0,0 +1,75 @@
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Tue Aug 15 05:03:41 2023 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS Dout[7] : 82 : out *
|
||||
NOTE PINS Dout[6] : 78 : out *
|
||||
NOTE PINS Dout[5] : 84 : out *
|
||||
NOTE PINS Dout[4] : 83 : out *
|
||||
NOTE PINS Dout[3] : 85 : out *
|
||||
NOTE PINS Dout[2] : 87 : out *
|
||||
NOTE PINS Dout[1] : 86 : out *
|
||||
NOTE PINS Dout[0] : 76 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS RBA[1] : 60 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 63 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 75 : out *
|
||||
NOTE PINS RA[6] : 68 : out *
|
||||
NOTE PINS RA[5] : 70 : out *
|
||||
NOTE PINS RA[4] : 74 : out *
|
||||
NOTE PINS RA[3] : 71 : out *
|
||||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS nRCS : 57 : out *
|
||||
NOTE PINS RCKE : 53 : out *
|
||||
NOTE PINS nRWE : 49 : out *
|
||||
NOTE PINS nRRAS : 54 : out *
|
||||
NOTE PINS nRCAS : 52 : out *
|
||||
NOTE PINS RDQMH : 51 : out *
|
||||
NOTE PINS RDQML : 48 : out *
|
||||
NOTE PINS nUFMCS : 77 : out *
|
||||
NOTE PINS UFMCLK : 29 : out *
|
||||
NOTE PINS UFMSDI : 30 : out *
|
||||
NOTE PINS PHI2 : 8 : in *
|
||||
NOTE PINS MAin[9] : 32 : in *
|
||||
NOTE PINS MAin[8] : 25 : in *
|
||||
NOTE PINS MAin[7] : 18 : in *
|
||||
NOTE PINS MAin[6] : 24 : in *
|
||||
NOTE PINS MAin[5] : 19 : in *
|
||||
NOTE PINS MAin[4] : 20 : in *
|
||||
NOTE PINS MAin[3] : 21 : in *
|
||||
NOTE PINS MAin[2] : 13 : in *
|
||||
NOTE PINS MAin[1] : 12 : in *
|
||||
NOTE PINS MAin[0] : 14 : in *
|
||||
NOTE PINS CROW[1] : 16 : in *
|
||||
NOTE PINS CROW[0] : 10 : in *
|
||||
NOTE PINS Din[7] : 1 : in *
|
||||
NOTE PINS Din[6] : 2 : in *
|
||||
NOTE PINS Din[5] : 98 : in *
|
||||
NOTE PINS Din[4] : 99 : in *
|
||||
NOTE PINS Din[3] : 97 : in *
|
||||
NOTE PINS Din[2] : 88 : in *
|
||||
NOTE PINS Din[1] : 96 : in *
|
||||
NOTE PINS Din[0] : 3 : in *
|
||||
NOTE PINS nCCAS : 9 : in *
|
||||
NOTE PINS nCRAS : 17 : in *
|
||||
NOTE PINS nFWE : 28 : in *
|
||||
NOTE PINS RCLK : 62 : in *
|
||||
NOTE PINS UFMSDO : 27 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
21
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep
Normal file
21
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep
Normal file
@ -0,0 +1,21 @@
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2GS.TECH
|
||||
Register bits: 102 of 877 (11.631%)
|
||||
I/O cells: 67
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 10 100.0
|
||||
FD1P3AX 29 100.0
|
||||
FD1P3AY 5 100.0
|
||||
FD1P3IX 3 100.0
|
||||
FD1S3AX 47 100.0
|
||||
FD1S3IX 14 100.0
|
||||
FD1S3JX 4 100.0
|
||||
GSR 1 100.0
|
||||
IB 26 100.0
|
||||
INV 3 100.0
|
||||
LUT4 122 100.0
|
||||
OB 33 100.0
|
||||
PFUMX 1 100.0
|
||||
TOTAL 306
|
||||
86
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn
Normal file
86
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn
Normal file
@ -0,0 +1,86 @@
|
||||
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:39 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 191 Pages (128*191 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 0 Page.
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 245 MB
|
||||
BIN
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd
Normal file
BIN
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd
Normal file
Binary file not shown.
281
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad
Normal file
281
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad
Normal file
@ -0,0 +1,281 @@
|
||||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Tue Aug 15 05:03:32 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS25_IN | PL6A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS25_IN | PT6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS25_IN | PT6C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS25_IN | PT6A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS25_IN | PT6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS25_IN | PL2B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS25_IN | PL2A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS25_OUT | PT11D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVCMOS25_OUT | PT9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVCMOS25_OUT | PT9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVCMOS25_OUT | PT9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVCMOS25_OUT | PT10B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVCMOS25_OUT | PT10A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVCMOS25_OUT | PT11A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVCMOS25_OUT | PT10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| LED | 34/2 | LVCMOS25_OUT | PB6C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS25_IN | PL7B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS25_IN | PL7A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS25_IN | PL6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS25_IN | PL7C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS25_IN | PL6C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS25_IN | PL7D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS25_IN | PB6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS25_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS25_OUT | PR3D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS25_OUT | PR6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS25_OUT | PR3C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS25_OUT | PR2C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS25_OUT | PR2D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS25_OUT | PR6C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS25_OUT | PR6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS25_OUT | PR7B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS25_OUT | PR7D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS25_OUT | PB14C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS25_BIDI | PB10A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS25_BIDI | PB10B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS25_BIDI | PB10C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS25_BIDI | PB10D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS25_BIDI | PB12A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS25_BIDI | PB12B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS25_BIDI | PB12C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS25_BIDI | PB12D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| UFMCLK | 29/2 | LVCMOS25_OUT | PB4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| UFMSDI | 30/2 | LVCMOS25_OUT | PB4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| UFMSDO | 27/2 | LVCMOS25_IN | PB4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCCAS | 9/3 | LVCMOS25_IN | PL3C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS25_IN | PL6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 28/2 | LVCMOS25_IN | PB4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS25_OUT | PR7C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS25_OUT | PR6D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS25_OUT | PR7A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS25_OUT | PB14D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
| nUFMCS | 77/0 | LVCMOS25_OUT | PT11C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 2.5V |
|
||||
| 1 | 2.5V |
|
||||
| 2 | 2.5V |
|
||||
| 3 | 2.5V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2A | | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2B | | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3A | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3B | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL3C | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL3D | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | |
|
||||
| 15/3 | unused, PULL:DOWN | | | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL6A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL6B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL6C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL6D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL7D | | | |
|
||||
| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4A | CSSPIN | | |
|
||||
| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4B | | | |
|
||||
| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB4C | | | |
|
||||
| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR7D | | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR7C | | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR7B | | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR7A | | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR6A | | | |
|
||||
| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR3D | | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR3C | | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR3B | | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR3A | | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR2D | | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR2C | | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT11D | DONE | | |
|
||||
| 77/0 | nUFMCS | | LVCMOS25_OUT | PT11C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT10C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT10B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT10A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT6D | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT6C | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT6B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "62";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "UFMCLK" SITE "29";
|
||||
LOCATE COMP "UFMSDI" SITE "30";
|
||||
LOCATE COMP "UFMSDO" SITE "27";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "28";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
LOCATE COMP "nUFMCS" SITE "77";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:34 2023
|
||||
|
||||
231
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
Normal file
231
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
Normal file
@ -0,0 +1,231 @@
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
|
||||
Tue Aug 15 05:03:28 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 67+4(JTAG)/80 89% used
|
||||
67+4(JTAG)/79 90% bonded
|
||||
|
||||
SLICE 75/320 23% used
|
||||
|
||||
|
||||
|
||||
Number of Signals: 285
|
||||
Number of Connections: 674
|
||||
WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
|
||||
|
||||
Pin Constraint Summary:
|
||||
66 out of 67 pins locked (98% locked).
|
||||
|
||||
The following 2 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 40)
|
||||
PHI2_c (driver: PHI2, clk load #: 13)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
.
|
||||
Starting Placer Phase 0.
|
||||
.............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...............
|
||||
Placer score = 121531.
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 119079
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 3 out of 80 (3%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
|
||||
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 2 out of 8 (25%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
67 + 4(JTAG) out of 80 (88.8%) PIO sites used.
|
||||
67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used.
|
||||
Number of PIO comps: 67; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 14 / 19 ( 73%) | 2.5V | - |
|
||||
| 1 | 20 / 20 (100%) | 2.5V | - |
|
||||
| 2 | 16 / 20 ( 80%) | 2.5V | - |
|
||||
| 3 | 17 / 20 ( 85%) | 2.5V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 3 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 674 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=nCCAS_c loads=6 clock_loads=4
|
||||
|
||||
Completed router resource preassignment. Real time: 7 secs
|
||||
|
||||
Start NBR router at 05:03:35 08/15/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:03:35 08/15/23
|
||||
|
||||
Start NBR section for initial routing at 05:03:35 08/15/23
|
||||
Level 1, iteration 1
|
||||
2(0.00%) conflicts; 536(79.53%) untouched conns; 481988 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.914ns/-481.988ns; real time: 7 secs
|
||||
Level 2, iteration 1
|
||||
7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.988ns/-424.953ns; real time: 7 secs
|
||||
Level 3, iteration 1
|
||||
12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -5.118ns/-455.640ns; real time: 7 secs
|
||||
Level 4, iteration 1
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -5.122ns/-465.237ns; real time: 7 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:03:35 08/15/23
|
||||
Level 4, iteration 1
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.992ns/-461.186ns; real time: 7 secs
|
||||
Level 4, iteration 2
|
||||
3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.992ns/-460.933ns; real time: 7 secs
|
||||
Level 4, iteration 3
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.992ns/-461.063ns; real time: 7 secs
|
||||
Level 4, iteration 4
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -4.992ns/-461.063ns; real time: 7 secs
|
||||
Level 4, iteration 5
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs
|
||||
|
||||
Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs
|
||||
|
||||
Start NBR section for re-routing at 05:03:35 08/15/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs
|
||||
|
||||
Start NBR section for post-routing at 05:03:35 08/15/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 260 (38.58%)
|
||||
Estimated worst slack<setup> : -5.122ns
|
||||
Timing score<setup> : 452301
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=nCCAS_c loads=6 clock_loads=4
|
||||
|
||||
Total CPU time 7 secs
|
||||
Total REAL time: 7 secs
|
||||
Completely routed.
|
||||
End of route. 674 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 452301
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = -5.122
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 452.301
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 7 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
@ -0,0 +1,38 @@
|
||||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 2;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 40;
|
||||
; Global primary clock #1
|
||||
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
|
||||
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_1_LOADNUM = 13;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 1;
|
||||
; Global secondary clock #0
|
||||
GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c;
|
||||
GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_SECONDARY_0_LOADNUM = 9;
|
||||
GLOBAL_SECONDARY_0_SIGTYPE = CLK;
|
||||
; I/O Bank 0 Usage
|
||||
BANK_0_USED = 14;
|
||||
BANK_0_AVAIL = 19;
|
||||
BANK_0_VCCIO = 2.5V;
|
||||
BANK_0_VREF1 = NA;
|
||||
; I/O Bank 1 Usage
|
||||
BANK_1_USED = 20;
|
||||
BANK_1_AVAIL = 20;
|
||||
BANK_1_VCCIO = 2.5V;
|
||||
BANK_1_VREF1 = NA;
|
||||
; I/O Bank 2 Usage
|
||||
BANK_2_USED = 16;
|
||||
BANK_2_AVAIL = 20;
|
||||
BANK_2_VCCIO = 2.5V;
|
||||
BANK_2_VREF1 = NA;
|
||||
; I/O Bank 3 Usage
|
||||
BANK_3_USED = 17;
|
||||
BANK_3_AVAIL = 20;
|
||||
BANK_3_VCCIO = 2.5V;
|
||||
BANK_3_VREF1 = NA;
|
||||
@ -0,0 +1,28 @@
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 05:03:28 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 -5.122 452301 0.304 0 07 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
1
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc
Normal file
1
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc
Normal file
@ -0,0 +1 @@
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
1435
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed
Normal file
1435
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed
Normal file
File diff suppressed because it is too large
Load Diff
4
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log
Normal file
4
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log
Normal file
@ -0,0 +1,4 @@
|
||||
---- MParTrce Tool Log File ----
|
||||
|
||||
==== Par Standard Out ====
|
||||
==== End of Par Standard Out ====
|
||||
4
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf
Normal file
4
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf
Normal file
@ -0,0 +1,4 @@
|
||||
#BLOCK ASYNCPATHS;
|
||||
#BLOCK RESETPATHS;
|
||||
|
||||
#FREQUENCY 200.000000 MHz;
|
||||
6331
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata
Normal file
6331
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata
Normal file
File diff suppressed because it is too large
Load Diff
336
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp
Normal file
336
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp
Normal file
@ -0,0 +1,336 @@
|
||||
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:/One
|
||||
Drive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_i
|
||||
mpl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_
|
||||
LCMXO2_640HC.lpf -c 0 -gui -msgset
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 08/15/23 05:03:24
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 102 out of 877 (12%)
|
||||
PFU registers: 102 out of 640 (16%)
|
||||
PIO registers: 0 out of 237 (0%)
|
||||
Number of SLICEs: 75 out of 320 (23%)
|
||||
SLICEs as Logic/ROM: 75 out of 320 (23%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 10 out of 320 (3%)
|
||||
Number of LUT4s: 143 out of 640 (22%)
|
||||
Number used as logic LUTs: 123
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : No
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
|
||||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
|
||||
Number of Clock Enables: 14
|
||||
Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
|
||||
Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/15/23 05:03:24
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
|
||||
Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
|
||||
Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
|
||||
Net Ready_N_292: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 7
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
|
||||
Net Ready: 7 loads, 7 LSLICEs
|
||||
Net nRWE_N_177: 1 loads, 1 LSLICEs
|
||||
Net C1Submitted_N_237: 2 loads, 2 LSLICEs
|
||||
Net n2366: 2 loads, 2 LSLICEs
|
||||
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net Ready: 18 loads
|
||||
Net InitReady: 15 loads
|
||||
Net RASr2: 15 loads
|
||||
Net nRowColSel_N_35: 13 loads
|
||||
Net nRowColSel: 12 loads
|
||||
Net Din_c_4: 10 loads
|
||||
Net MAin_c_1: 10 loads
|
||||
Net Din_c_5: 9 loads
|
||||
Net MAin_c_0: 9 loads
|
||||
Net Din_c_0: 8 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 0
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
No errors or warnings present.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/15/23 05:03:24
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| RD[5] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/15/23 05:03:24
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| RA[0] | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nUFMCS | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| UFMCLK | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| UFMSDI | OUTPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/15/23 05:03:24
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Din[3] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| UFMSDO | INPUT | LVCMOS25 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block i2 undriven or does not drive anything - clipped.
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal PHI2_N_120 was merged into signal PHI2_c
|
||||
Signal n1407 was merged into signal nRowColSel_N_34
|
||||
Signal n2380 was merged into signal Ready
|
||||
Signal n1408 was merged into signal nRowColSel_N_35
|
||||
Signal nRWE_N_176 was merged into signal nRWE_N_177
|
||||
Signal GND_net undriven or does not drive anything - clipped.
|
||||
Signal VCC_net undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped.
|
||||
Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped.
|
||||
Block i2046 was optimized away.
|
||||
Block i1118_1_lut was optimized away.
|
||||
Block i637_1_lut_rep_31 was optimized away.
|
||||
Block i1119_1_lut was optimized away.
|
||||
Block nRWE_I_50_1_lut was optimized away.
|
||||
Block i1 was optimized away.
|
||||
|
||||
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 35 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
9
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt
Normal file
9
CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt
Normal file
@ -0,0 +1,9 @@
|
||||
-v
|
||||
1
|
||||
|
||||
|
||||
-gt
|
||||
|
||||
|
||||
-mapchkpnt 0
|
||||
-sethld
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user