techav
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89ce4cbc1d
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Revert "Preprep for iCE40"
This reverts commit 0b2eb362d8.
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2021-07-25 12:02:03 -05:00 |
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techav
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5b67fdfe53
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Merge branch 'main' of https://github.com/techav-homebrew/SE-VGA into main
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2021-07-25 12:00:29 -05:00 |
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techav
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0e9c2df93c
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Add Compiled CPLD Configuration
Both the .pof for Altera CPLD and .jed for Atmel CPLD
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2021-07-25 11:59:27 -05:00 |
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techav
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eecc0cbe93
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Add Compiled CPLD Configuration
Both the .pof for Altera CPLD and .jed for Atmel CPLD
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2021-06-05 17:57:10 -05:00 |
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techav
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0b2eb362d8
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Preprep for iCE40
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2021-05-23 22:10:04 -05:00 |
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techav
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5d3dd1f0eb
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Update Readme
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2021-05-21 22:44:26 -05:00 |
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techav
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22239fecef
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Add Gerbers
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2021-05-21 22:04:00 -05:00 |
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techav
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b0815fb726
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Merge branch 'main' of https://github.com/techav-homebrew/SE-VGA into main
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2021-05-21 21:47:29 -05:00 |
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techav
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5b1e2ecc72
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CPU Snoop Fixes
Fix for VRAM writes sometimes overlapping VRAM reads
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2021-05-21 21:47:22 -05:00 |
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techav
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bfeba8c649
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Update README.md
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2021-05-20 00:10:00 -05:00 |
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techav
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04faf575f9
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Debugging CPU Bus Snooping
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2021-05-16 12:22:28 -05:00 |
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techav
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207acc2eaa
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First Run
First live tests on actual hardware
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2021-05-14 23:48:34 -05:00 |
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techav
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3fe79659f3
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Pin Assignments
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2021-04-19 21:01:08 -05:00 |
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techav
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85a3cc95d9
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Add Alternate Frame Buffer Support
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2021-04-19 20:45:11 -05:00 |
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techav
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57436785a2
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Documentation Cleanup
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2021-04-18 14:31:05 -05:00 |
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techav
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14e5c8eb39
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Refactor Video Out Sequence
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2021-04-18 13:19:16 -05:00 |
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techav
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995be6b5dc
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Getting ready for a large refactor
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2021-04-18 12:50:43 -05:00 |
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techav
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c4bc1c4be5
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CPU Cycle Improvements 2
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2021-04-18 12:07:42 -05:00 |
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techav
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3b00823d6c
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CPU Cycle Improvements 1
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2021-04-18 10:28:04 -05:00 |
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techav
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7a519feab3
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CPU cycle state machine
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2021-04-17 15:41:53 -05:00 |
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techav
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bbae9212e8
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New output stage
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2021-04-12 22:07:18 -05:00 |
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techav
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89040b43b4
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First compile
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2021-04-11 23:46:29 -05:00 |
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techav
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0e5df6ce76
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partial draft 2
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2021-04-07 22:50:46 -05:00 |
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techav
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77a0a23e1a
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partial draft 1
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2021-04-06 23:15:48 -05:00 |
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techav
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eaf6747995
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Initial commit
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2021-04-06 19:38:45 -05:00 |