Macintosh-HW
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SE-VGA
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Commit Graph

  • e37c0d1857 Clean out old compiled logic Rev3 techav 2023-07-14 15:39:14 -0500
  • 07cf12ddf9 Clean out old gerbers techav 2023-07-14 15:38:34 -0500
  • 73c3f7bdfd Upload new schematic plot techav 2023-07-14 15:36:11 -0500
  • 44a3700dc4 Add initial PCB render techav 2023-07-14 15:31:38 -0500
  • 7169786caa Add CC-BY-SA license and initial Rev3 Readme techav 2023-07-14 15:25:57 -0500
  • a806219b67 Cleanup for DRC techav 2023-07-14 13:04:30 -0500
  • 9abd2f0997 Multiplex CPU bus and add 24bpp output techav 2023-07-13 21:24:12 -0500
  • e86cd941ca R3 PCB layout first draft techav 2023-07-01 02:08:46 -0500
  • f15cd37581 R3 Initial schematic complete, start routing techav 2023-06-30 00:05:36 -0500
  • a351ec4477 Rev3 Initial Schematic techav 2023-06-29 15:34:40 -0500
  • 4302d72405 Cleanup old logic main techav 2021-10-22 22:37:15 -0500
  • fca75c2c4c Update readme techav 2021-10-22 22:36:03 -0500
  • 42f59513e1
         Merge pull request #1 from techav-homebrew/XGA techav 2021-10-22 22:24:59 -0500
  • a9b119fb6d Mostly working techav 2021-10-22 22:18:44 -0500
  • 1137244a39 Rewrite again techav 2021-10-17 03:41:04 -0500
  • 3c12b07c70 Another fresh start techav-homebrew 2021-10-17 01:25:27 -0500
  • 7e2413150f Cleanup techav 2021-10-17 01:24:22 -0500
  • 4be7d63105 Fixed image overwrite issues techav 2021-10-12 23:28:59 -0500
  • 5377d05895 Rebuilt state machine again techav 2021-10-11 21:25:28 -0500
  • 6f2f67ef05 New State Machine techav 2021-10-11 16:25:40 -0500
  • 373b0ec9b5 Debugging VRAM Write Timing techav 2021-10-09 14:47:53 -0500
  • 97b0b72794 VIA snooping techav-homebrew 2021-10-07 21:35:29 -0500
  • 3669e3a66b CPU Snoop First Draft techav-homebrew 2021-10-07 21:17:36 -0500
  • 90d5384b90 Starting new cpu snoop techav 2021-10-07 18:54:47 -0500
  • 4f08c1f6fc Start logic rebuild for XGA techav 2021-08-04 23:40:16 -0500
  • c4b11b0a4b Change multiplier part techav 2021-07-26 22:23:40 -0500
  • 51da925261 XGA Board Rev techav 2021-07-25 18:11:49 -0500
  • 89ce4cbc1d Revert "Preprep for iCE40" v0.1.0 techav 2021-07-25 12:02:03 -0500
  • 5b67fdfe53 Merge branch 'main' of https://github.com/techav-homebrew/SE-VGA into main techav 2021-07-25 12:00:29 -0500
  • 0e9c2df93c Add Compiled CPLD Configuration techav 2021-06-05 17:57:10 -0500
  • eecc0cbe93 Add Compiled CPLD Configuration techav 2021-06-05 17:57:10 -0500
  • 0b2eb362d8 Preprep for iCE40 techav 2021-05-23 22:10:04 -0500
  • 5d3dd1f0eb Update Readme techav 2021-05-21 22:44:26 -0500
  • 22239fecef Add Gerbers techav 2021-05-21 22:04:00 -0500
  • b0815fb726 Merge branch 'main' of https://github.com/techav-homebrew/SE-VGA into main techav 2021-05-21 21:47:29 -0500
  • 5b1e2ecc72 CPU Snoop Fixes techav 2021-05-21 21:47:22 -0500
  • bfeba8c649
         Update README.md techav 2021-05-20 00:10:00 -0500
  • 04faf575f9 Debugging CPU Bus Snooping techav 2021-05-16 12:22:28 -0500
  • 207acc2eaa First Run techav 2021-05-14 23:48:34 -0500
  • 3fe79659f3 Pin Assignments techav 2021-04-19 21:01:08 -0500
  • 85a3cc95d9 Add Alternate Frame Buffer Support techav 2021-04-19 20:45:11 -0500
  • 57436785a2 Documentation Cleanup techav 2021-04-18 14:31:05 -0500
  • 14e5c8eb39 Refactor Video Out Sequence techav 2021-04-18 13:19:16 -0500
  • 995be6b5dc Getting ready for a large refactor techav 2021-04-18 12:50:43 -0500
  • c4bc1c4be5 CPU Cycle Improvements 2 techav 2021-04-18 12:07:42 -0500
  • 3b00823d6c CPU Cycle Improvements 1 techav 2021-04-18 10:28:04 -0500
  • 7a519feab3 CPU cycle state machine techav 2021-04-17 15:41:53 -0500
  • bbae9212e8 New output stage techav 2021-04-12 22:07:18 -0500
  • 89040b43b4 First compile techav 2021-04-11 23:46:29 -0500
  • 0e5df6ce76 partial draft 2 techav 2021-04-07 22:50:46 -0500
  • 77a0a23e1a partial draft 1 techav 2021-04-06 23:15:48 -0500
  • eaf6747995
         Initial commit techav 2021-04-06 19:38:45 -0500