Warp-SE/cpld/XC95144XL/WarpSE_html/fit/ascii.htm

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cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
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Design Name: WarpSE Date: 4-17-2023, 2:26AM
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Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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123/144 ( 85%) 479 /720 ( 67%) 286/432 ( 66%) 99 /144 ( 69%) 70 /81 ( 86%)
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** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 30/54 46/90 11/11*
FB2 16/18 21/54 20/90 8/10
FB3 15/18 41/54 81/90 10/10*
FB4 13/18 43/54 50/90 10/10*
FB5 13/18 33/54 81/90 8/10
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FB6 18/18* 36/54 68/90 10/10*
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FB7 18/18* 41/54 52/90 7/10
FB8 12/18 41/54 81/90 6/10
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----- ----- ----- -----
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123/144 286/432 479/720 70/81
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* - Resource is exhausted
** Global Control Resources **
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Signal 'C16M' mapped onto global clock net GCK1.
Signal 'C8M' mapped onto global clock net GCK2.
Signal 'FCLK' mapped onto global clock net GCK3.
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Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
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Input : 32 32 | I/O : 64 73
Output : 34 34 | GCK/IO : 3 3
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Bidirectional : 1 1 | GTS/IO : 3 4
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GCK : 3 3 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
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Total 70 70
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** Power Data **
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There are 123 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'WarpSE.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'C16M' based upon the LOC
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constraint 'P22'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'C8M' based upon the LOC
constraint 'P23'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'FCLK' based upon the LOC
constraint 'P27'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'C20MEN'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<1>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<2>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<3>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'nBG_IOB'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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************************* Summary of Mapped Logic ************************
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** 35 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
nDTACK_FSB 9 17 FB3_9 28 I/O O STD FAST RESET
nROMWE 1 2 FB3_17 34 I/O O STD FAST
nAoutOE 2 4 FB4_2 87 I/O O STD FAST SET
nDoutOE 2 5 FB4_5 89 I/O O STD FAST
nDinOE 3 6 FB4_6 90 I/O O STD FAST
nRES 1 1 FB4_8 91 I/O I/O STD FAST
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nVPA_FSB 3 11 FB4_11 93 I/O O STD FAST RESET
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nROMCS 2 5 FB5_2 35 I/O O STD FAST
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nCAS 14 16 FB5_5 36 I/O O STD FAST RESET
nOE 3 5 FB5_6 37 I/O O STD FAST RESET
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RA<4> 2 3 FB5_9 40 I/O O STD FAST
RA<3> 2 3 FB5_11 41 I/O O STD FAST
RA<5> 2 3 FB5_12 42 I/O O STD FAST
RA<2> 2 3 FB5_14 43 I/O O STD FAST
RA<6> 2 3 FB5_15 46 I/O O STD FAST
nVMA_IOB 3 8 FB6_2 74 I/O O STD FAST RESET
nLDS_IOB 6 10 FB6_9 79 I/O O STD FAST RESET
nUDS_IOB 6 10 FB6_11 80 I/O O STD FAST RESET
nAS_IOB 4 9 FB6_12 81 I/O O STD FAST RESET
nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET
nADoutLE0 1 2 FB6_15 85 I/O O STD FAST
nDinLE 1 2 FB6_17 86 I/O O STD FAST RESET
RA<1> 2 3 FB7_2 50 I/O O STD FAST
RA<7> 2 3 FB7_5 52 I/O O STD FAST
RA<0> 2 3 FB7_6 53 I/O O STD FAST
RA<8> 2 3 FB7_8 54 I/O O STD FAST
RA<10> 2 3 FB7_9 55 I/O O STD FAST
RA<9> 2 3 FB7_11 56 I/O O STD FAST
C25MEN 0 0 FB7_12 58 I/O O STD FAST
RA<11> 2 3 FB8_2 63 I/O O STD FAST
nRAS 3 7 FB8_5 64 I/O O STD FAST
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nRAMLWE 1 3 FB8_6 65 I/O O STD FAST
nRAMUWE 1 3 FB8_8 66 I/O O STD FAST
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nBERR_FSB 3 5 FB8_12 70 I/O O STD FAST RESET
nBR_IOB 2 4 FB8_15 72 I/O O STD FAST RESET
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** 88 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
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ram/RS_FSM_FFd3 1 2 FB1_1 STD RESET
ram/RS_FSM_FFd2 1 1 FB1_2 STD RESET
ram/RS_FSM_FFd1 1 1 FB1_3 STD RESET
ram/RASrf 1 2 FB1_4 STD RESET
cnt/Er<1> 1 1 FB1_5 STD RESET
ram/RefDone 2 6 FB1_6 STD RESET
ram/RS_FSM_FFd4 2 3 FB1_7 STD RESET
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iobs/IOU1 2 2 FB1_8 STD RESET
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iobs/IOL1 2 2 FB1_9 STD RESET
cnt/TimerTC 2 6 FB1_10 STD RESET
cnt/Timer<0> 2 4 FB1_11 STD RESET
cnt/IS_FSM_FFd2 2 6 FB1_12 STD RESET
RefUrg 2 5 FB1_13 STD RESET
RefReq 2 6 FB1_14 STD RESET
cnt/Timer<1> 4 5 FB1_15 STD RESET
cnt/Timer<3> 5 7 FB1_16 STD RESET
cnt/Timer<2> 5 6 FB1_17 STD RESET
ram/RS_FSM_FFd6 9 11 FB1_18 STD RESET
ram/DTACKr 1 1 FB2_3 STD RESET
iobs/IODONEr 1 1 FB2_4 STD RESET
iobs/IOACTr 1 1 FB2_5 STD RESET
iobm/VPAr 1 1 FB2_6 STD RESET
iobm/IOWRREQr 1 1 FB2_7 STD RESET
iobm/IOS_FSM_FFd5 1 1 FB2_8 STD RESET
iobm/IOS_FSM_FFd4 1 1 FB2_9 STD RESET
iobm/IOS_FSM_FFd1 1 1 FB2_10 STD RESET
iobm/IORDREQr 1 1 FB2_11 STD RESET
iobm/Er 1 1 FB2_12 STD RESET
iobm/C8Mr 1 1 FB2_13 STD RESET
cnt/nIPL2r 1 1 FB2_14 STD RESET
cnt/Er<0> 1 1 FB2_15 STD RESET
iobm/IOS_FSM_FFd2 2 4 FB2_16 STD RESET
IOBERR 2 2 FB2_17 STD RESET
iobm/ES<2> 3 5 FB2_18 STD RESET
QoSReady 18 25 FB3_1 STD RESET
IONPReady 5 16 FB3_2 STD RESET
iobs/Clear1 1 2 FB3_3 STD RESET
ALE0S 1 1 FB3_4 STD RESET
iobs/TS_FSM_FFd1 2 3 FB3_5 STD RESET
cs/nOverlay 3 8 FB3_6 STD RESET
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Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
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cnt/WS<3> 3 6 FB3_7 STD RESET
cnt/WS<2> 3 5 FB3_8 STD RESET
cnt/WS<1> 3 4 FB3_10 STD RESET
ram/RS_FSM_FFd5 2 7 FB3_11 STD RESET
iobs/Load1 8 17 FB3_12 STD RESET
IORDREQ 9 15 FB3_14 STD RESET
iobs/Sent 13 18 FB3_15 STD RESET
ram/BACTr 1 2 FB4_7 STD RESET
nRESout 1 2 FB4_9 STD RESET
fsb/ASrf 1 1 FB4_10 STD RESET
cnt/WS<0> 1 3 FB4_12 STD RESET
cnt/LTimerTC 1 12 FB4_13 STD RESET
$OpTx$$OpTx$FX_DC$346_INV$533 1 2 FB4_14 STD
cnt/LTimer<1> 11 24 FB4_16 STD RESET
cnt/LTimer<0> 22 34 FB4_18 STD RESET
ram/RS_FSM_FFd7 13 13 FB5_1 STD SET
ram/RASEN 11 16 FB5_7 STD RESET
ram/RASEL 4 14 FB5_10 STD RESET
ram/RASrr 12 18 FB5_13 STD RESET
RAMReady 12 17 FB5_18 STD RESET
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iobm/IOS_FSM_FFd6 2 5 FB6_1 STD RESET
iobm/IOS_FSM_FFd7 3 6 FB6_3 STD SET
iobm/IOS_FSM_FFd3 3 5 FB6_4 STD RESET
iobm/ES<0> 3 6 FB6_5 STD RESET
iobm/ES<3> 4 6 FB6_6 STD RESET
iobm/ES<1> 4 6 FB6_7 STD RESET
iobm/DoutOE 4 8 FB6_8 STD RESET
IODONE 4 8 FB6_10 STD RESET
iobm/IOS0 5 12 FB6_13 STD RESET
ALE0M 5 11 FB6_16 STD RESET
IOACT 8 14 FB6_18 STD RESET
cnt/LTimer<9> 3 15 FB7_1 STD RESET
cnt/LTimer<8> 3 14 FB7_3 STD RESET
cnt/LTimer<7> 3 13 FB7_4 STD RESET
cnt/LTimer<6> 3 12 FB7_7 STD RESET
cnt/LTimer<5> 3 11 FB7_10 STD RESET
cnt/LTimer<4> 3 10 FB7_13 STD RESET
cnt/LTimer<3> 3 9 FB7_14 STD RESET
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cnt/LTimer<2> 3 8 FB7_15 STD RESET
cnt/LTimer<11> 3 17 FB7_16 STD RESET
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Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
cnt/LTimer<10> 3 16 FB7_17 STD RESET
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2 10 36 FB7_18 STD
IOL0 16 21 FB8_1 STD RESET
iobs/TS_FSM_FFd2 13 19 FB8_3 STD RESET
IOWRREQ 15 21 FB8_9 STD RESET
IOU0 16 21 FB8_14 STD RESET
cnt/IS_FSM_FFd1 1 7 FB8_16 STD RESET
iobs/IORW1 8 18 FB8_17 STD RESET
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** 35 Inputs **
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Signal Loc Pin Pin Pin
Name No. Type Use
A_FSB<13> FB1_2 11 I/O I
A_FSB<14> FB1_3 12 I/O I
A_FSB<15> FB1_5 13 I/O I
A_FSB<16> FB1_6 14 I/O I
A_FSB<17> FB1_8 15 I/O I
A_FSB<18> FB1_9 16 I/O I
A_FSB<19> FB1_11 17 I/O I
A_FSB<20> FB1_12 18 I/O I
A_FSB<21> FB1_14 19 I/O I
A_FSB<22> FB1_15 20 I/O I
C16M FB1_17 22 GCK/I/O GCK
A_FSB<5> FB2_6 2 GTS/I/O I
A_FSB<6> FB2_8 3 GTS/I/O I
A_FSB<7> FB2_9 4 GTS/I/O I
A_FSB<8> FB2_11 6 I/O I
A_FSB<9> FB2_12 7 I/O I
A_FSB<10> FB2_14 8 I/O I
A_FSB<11> FB2_15 9 I/O I
A_FSB<12> FB2_17 10 I/O I
C8M FB3_2 23 GCK/I/O GCK/I
A_FSB<23> FB3_5 24 I/O I
E FB3_6 25 I/O I
FCLK FB3_8 27 GCK/I/O GCK
nWE_FSB FB3_11 29 I/O I
nLDS_FSB FB3_12 30 I/O I
nAS_FSB FB3_14 32 I/O I
nUDS_FSB FB3_15 33 I/O I
nIPL2 FB4_9 92 I/O I
A_FSB<1> FB4_12 94 I/O I
A_FSB<2> FB4_14 95 I/O I
A_FSB<3> FB4_15 96 I/O I
A_FSB<4> FB4_17 97 I/O I
nBERR_IOB FB6_5 76 I/O I
nVPA_IOB FB6_6 77 I/O I
nDTACK_IOB FB6_8 78 I/O I
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Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
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Number of function block inputs used/remaining: 30/24
Number of signals used by logic mapping into function block: 30
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
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ram/RS_FSM_FFd3 1 0 /\4 0 FB1_1 (b) (b)
ram/RS_FSM_FFd2 1 0 0 4 FB1_2 11 I/O I
ram/RS_FSM_FFd1 1 0 0 4 FB1_3 12 I/O I
ram/RASrf 1 0 0 4 FB1_4 (b) (b)
cnt/Er<1> 1 0 0 4 FB1_5 13 I/O I
ram/RefDone 2 0 0 3 FB1_6 14 I/O I
ram/RS_FSM_FFd4 2 0 0 3 FB1_7 (b) (b)
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iobs/IOU1 2 0 0 3 FB1_8 15 I/O I
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iobs/IOL1 2 0 0 3 FB1_9 16 I/O I
cnt/TimerTC 2 0 0 3 FB1_10 (b) (b)
cnt/Timer<0> 2 0 0 3 FB1_11 17 I/O I
cnt/IS_FSM_FFd2 2 0 0 3 FB1_12 18 I/O I
RefUrg 2 0 0 3 FB1_13 (b) (b)
RefReq 2 0 0 3 FB1_14 19 I/O I
cnt/Timer<1> 4 0 0 1 FB1_15 20 I/O I
cnt/Timer<3> 5 0 0 0 FB1_16 (b) (b)
cnt/Timer<2> 5 0 0 0 FB1_17 22 GCK/I/O GCK
ram/RS_FSM_FFd6 9 4<- 0 0 FB1_18 (b) (b)
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Signals Used by Logic in Function Block
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1: A_FSB<22> 11: cnt/Timer<1> 21: ram/DTACKr
2: A_FSB<23> 12: cnt/Timer<2> 22: ram/RASEN
3: RefReq 13: cnt/Timer<3> 23: ram/RS_FSM_FFd1
4: RefUrg 14: cnt/TimerTC 24: ram/RS_FSM_FFd2
5: cnt/Er<0> 15: fsb/ASrf 25: ram/RS_FSM_FFd3
6: cnt/Er<1> 16: iobs/Load1 26: ram/RS_FSM_FFd4
7: cnt/IS_FSM_FFd1 17: nAS_FSB 27: ram/RS_FSM_FFd5
8: cnt/IS_FSM_FFd2 18: nLDS_FSB 28: ram/RS_FSM_FFd6
9: cnt/LTimerTC 19: nUDS_FSB 29: ram/RS_FSM_FFd7
10: cnt/Timer<0> 20: ram/BACTr 30: ram/RefDone
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
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ram/RS_FSM_FFd3 ....................X....X.............. 2
ram/RS_FSM_FFd2 ...........................X............ 1
ram/RS_FSM_FFd1 .......................X................ 1
ram/RASrf ..........................XX............ 2
cnt/Er<1> ....X................................... 1
ram/RefDone ..XX..................XX...X.X.......... 6
ram/RS_FSM_FFd4 ....................X....XX............. 3
iobs/IOU1 ...............X..X..................... 2
iobs/IOL1 ...............X.X...................... 2
cnt/TimerTC ....XX...XXXX........................... 6
cnt/Timer<0> ....XX...X...X.......................... 4
cnt/IS_FSM_FFd2 ....XXXXX....X.......................... 6
RefUrg ....XX....XXX........................... 5
RefReq ....XX...XXXX........................... 6
cnt/Timer<1> ....XX...XX..X.......................... 5
cnt/Timer<3> ....XX...XXXXX.......................... 7
cnt/Timer<2> ....XX...XXX.X.......................... 6
ram/RS_FSM_FFd6 XXXX..........X.X..X.X..X...XX.......... 11
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0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
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Number of function block inputs used/remaining: 21/33
Number of signals used by logic mapping into function block: 21
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 99 GSR/I/O
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ram/DTACKr 1 0 0 4 FB2_3 (b) (b)
iobs/IODONEr 1 0 0 4 FB2_4 (b) (b)
iobs/IOACTr 1 0 0 4 FB2_5 1 GTS/I/O (b)
iobm/VPAr 1 0 0 4 FB2_6 2 GTS/I/O I
iobm/IOWRREQr 1 0 0 4 FB2_7 (b) (b)
iobm/IOS_FSM_FFd5 1 0 0 4 FB2_8 3 GTS/I/O I
iobm/IOS_FSM_FFd4 1 0 0 4 FB2_9 4 GTS/I/O I
iobm/IOS_FSM_FFd1 1 0 0 4 FB2_10 (b) (b)
iobm/IORDREQr 1 0 0 4 FB2_11 6 I/O I
iobm/Er 1 0 0 4 FB2_12 7 I/O I
iobm/C8Mr 1 0 0 4 FB2_13 (b) (b)
cnt/nIPL2r 1 0 0 4 FB2_14 8 I/O I
cnt/Er<0> 1 0 0 4 FB2_15 9 I/O I
iobm/IOS_FSM_FFd2 2 0 0 3 FB2_16 (b) (b)
IOBERR 2 0 0 3 FB2_17 10 I/O I
iobm/ES<2> 3 0 0 2 FB2_18 (b) (b)
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Signals Used by Logic in Function Block
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1: C8M 8: iobm/C8Mr 15: iobm/IOS_FSM_FFd5
2: E 9: iobm/ES<0> 16: iobm/IOS_FSM_FFd6
3: IOACT 10: iobm/ES<1> 17: nAS_IOB
4: IOBERR 11: iobm/ES<2> 18: nBERR_IOB
5: IODONE 12: iobm/Er 19: nDTACK_FSB
6: IORDREQ 13: iobm/IOS_FSM_FFd2 20: nIPL2
7: IOWRREQ 14: iobm/IOS_FSM_FFd3 21: nVPA_IOB
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
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ram/DTACKr ..................X..................... 1
iobs/IODONEr ....X................................... 1
iobs/IOACTr ..X..................................... 1
iobm/VPAr ....................X................... 1
iobm/IOWRREQr ......X................................. 1
iobm/IOS_FSM_FFd5 ...............X........................ 1
iobm/IOS_FSM_FFd4 ..............X......................... 1
iobm/IOS_FSM_FFd1 ............X........................... 1
iobm/IORDREQr .....X.................................. 1
iobm/Er .X...................................... 1
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iobm/C8Mr X....................................... 1
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cnt/nIPL2r ...................X.................... 1
cnt/Er<0> .X...................................... 1
iobm/IOS_FSM_FFd2 ...XX..X.....X.......................... 4
IOBERR ................XX...................... 2
iobm/ES<2> .X......XXXX............................ 5
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0----+----1----+----2----+----3----+----4
0 0 0 0
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*********************************** FB3 ***********************************
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Number of function block inputs used/remaining: 41/13
Number of signals used by logic mapping into function block: 41
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
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QoSReady 18 13<- 0 0 FB3_1 (b) (b)
IONPReady 5 4<- /\4 0 FB3_2 23 GCK/I/O GCK/I
iobs/Clear1 1 0 /\4 0 FB3_3 (b) (b)
ALE0S 1 0 0 4 FB3_4 (b) (b)
iobs/TS_FSM_FFd1 2 0 0 3 FB3_5 24 I/O I
cs/nOverlay 3 0 \/2 0 FB3_6 25 I/O I
cnt/WS<3> 3 2<- \/4 0 FB3_7 (b) (b)
cnt/WS<2> 3 3<- \/5 0 FB3_8 27 GCK/I/O GCK
nDTACK_FSB 9 9<- /\3 2 FB3_9 28 I/O O
cnt/WS<1> 3 0 \/2 0 FB3_10 (b) (b)
ram/RS_FSM_FFd5 2 2<- \/5 0 FB3_11 29 I/O I
iobs/Load1 8 5<- \/2 0 FB3_12 30 I/O I
2023-04-09 08:19:06 +00:00
(unused) 0 0 \/5 0 FB3_13 (b) (b)
2023-07-13 20:03:30 +00:00
IORDREQ 9 7<- \/3 0 FB3_14 32 I/O I
iobs/Sent 13 8<- 0 0 FB3_15 33 I/O I
(unused) 0 0 /\5 0 FB3_16 (b) (b)
nROMWE 1 0 \/4 0 FB3_17 34 I/O O
2023-04-09 08:19:06 +00:00
(unused) 0 0 \/5 0 FB3_18 (b) (b)
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-07-13 20:03:30 +00:00
1: $OpTx$$OpTx$FX_DC$346_INV$533 15: A_FSB<23> 29: cs/nOverlay
2: A_FSB<10> 16: A_FSB<8> 30: fsb/ASrf
3: A_FSB<11> 17: A_FSB<9> 31: iobs/IOACTr
4: A_FSB<12> 18: IONPReady 32: iobs/IODONEr
5: A_FSB<13> 19: IORDREQ 33: iobs/IORW1
6: A_FSB<14> 20: nRES.PIN 34: iobs/Sent
7: A_FSB<15> 21: QoSReady 35: iobs/TS_FSM_FFd1
8: A_FSB<16> 22: RAMReady 36: iobs/TS_FSM_FFd2
9: A_FSB<17> 23: cnt/LTimer<0> 37: nADoutLE1
10: A_FSB<18> 24: cnt/LTimer<1> 38: nAS_FSB
11: A_FSB<19> 25: cnt/WS<0> 39: nWE_FSB
12: A_FSB<20> 26: cnt/WS<1> 40: ram/RASEN
13: A_FSB<21> 27: cnt/WS<2> 41: ram/RS_FSM_FFd7
14: A_FSB<22> 28: cnt/WS<3>
2022-03-29 08:23:54 +00:00
2023-07-13 20:03:30 +00:00
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
QoSReady XXXXXXXXXXXXXXXXX...X.XXXXXX..........X........... 25
IONPReady ....XX.XXXXXXXX..X...........X.X.X...XX........... 16
iobs/Clear1 ..................................XX.............. 2
ALE0S ...................................X.............. 1
iobs/TS_FSM_FFd1 ..............................X...XX.............. 3
cs/nOverlay ...........XXXX....X........XX.......X............ 8
cnt/WS<3> ........................XXXX.X.......X............ 6
cnt/WS<2> ........................XXX..X.......X............ 5
nDTACK_FSB ....XX.XXXXXXXX..X..XX.......X......XXX........... 17
cnt/WS<1> ........................XX...X.......X............ 4
ram/RS_FSM_FFd5 .............XX.............XX.......X.XX......... 7
iobs/Load1 ....XX.XXXXXXXX..............X...XXXXXX........... 17
IORDREQ ...........XXXX...X.........XXX.XXXXXXX........... 15
iobs/Sent ....XX.XXXXXXXX.............XX...XXXXXX........... 18
nROMWE .....................................XX........... 2
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
2022-03-29 08:23:54 +00:00
*********************************** FB4 ***********************************
2023-07-13 20:03:30 +00:00
Number of function block inputs used/remaining: 43/11
Number of signals used by logic mapping into function block: 43
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-07-13 20:03:30 +00:00
(unused) 0 0 /\5 0 FB4_1 (b) (b)
2023-04-09 08:19:06 +00:00
nAoutOE 2 2<- /\5 0 FB4_2 87 I/O O
2023-07-13 20:03:30 +00:00
(unused) 0 0 /\2 3 FB4_3 (b) (b)
(unused) 0 0 0 5 FB4_4 (b)
2023-04-09 08:19:06 +00:00
nDoutOE 2 0 0 3 FB4_5 89 I/O O
nDinOE 3 0 0 2 FB4_6 90 I/O O
2023-07-13 20:03:30 +00:00
ram/BACTr 1 0 0 4 FB4_7 (b) (b)
2023-04-09 08:19:06 +00:00
nRES 1 0 0 4 FB4_8 91 I/O I/O
2023-07-13 20:03:30 +00:00
nRESout 1 0 0 4 FB4_9 92 I/O I
fsb/ASrf 1 0 0 4 FB4_10 (b) (b)
2023-04-07 06:33:04 +00:00
nVPA_FSB 3 0 0 2 FB4_11 93 I/O O
2023-07-13 20:03:30 +00:00
cnt/WS<0> 1 0 0 4 FB4_12 94 I/O I
cnt/LTimerTC 1 0 0 4 FB4_13 (b) (b)
$OpTx$$OpTx$FX_DC$346_INV$533
1 0 \/3 1 FB4_14 95 I/O I
(unused) 0 0 \/5 0 FB4_15 96 I/O I
cnt/LTimer<1> 11 8<- \/2 0 FB4_16 (b) (b)
(unused) 0 0 \/5 0 FB4_17 97 I/O I
cnt/LTimer<0> 22 17<- 0 0 FB4_18 (b) (b)
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-07-13 20:03:30 +00:00
1: A_FSB<10> 16: A_FSB<9> 30: cnt/LTimer<8>
2: A_FSB<11> 17: IONPReady 31: cnt/LTimer<9>
3: A_FSB<12> 18: cnt/IS_FSM_FFd1 32: cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2
4: A_FSB<13> 19: cnt/IS_FSM_FFd2 33: cnt/WS<0>
5: A_FSB<14> 20: cnt/LTimer<0> 34: fsb/ASrf
6: A_FSB<15> 21: cnt/LTimer<10> 35: iobm/DoutOE
7: A_FSB<16> 22: cnt/LTimer<11> 36: iobm/IORDREQr
8: A_FSB<17> 23: cnt/LTimer<1> 37: iobm/IOS0
9: A_FSB<18> 24: cnt/LTimer<2> 38: iobm/IOWRREQr
10: A_FSB<19> 25: cnt/LTimer<3> 39: nAS_FSB
11: A_FSB<20> 26: cnt/LTimer<4> 40: nAoutOE
12: A_FSB<21> 27: cnt/LTimer<5> 41: nBR_IOB
13: A_FSB<22> 28: cnt/LTimer<6> 42: nRESout
14: A_FSB<23> 29: cnt/LTimer<7> 43: nWE_FSB
15: A_FSB<8>
2023-04-09 08:19:06 +00:00
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
2023-07-13 20:03:30 +00:00
nAoutOE .................XX....................XX......... 4
nDoutOE ..................................XXXX.X.......... 5
nDinOE ..........XXXX........................X...X....... 6
ram/BACTr .................................X....X........... 2
nRES .........................................X........ 1
nRESout .................XX............................... 2
fsb/ASrf ......................................X........... 1
nVPA_FSB ......XXXXXXXX..X................X....X........... 11
cnt/WS<0> ................................XX....X........... 3
cnt/LTimerTC ...................XXXXXXXXXXXX................... 12
$OpTx$$OpTx$FX_DC$346_INV$533
.................................X....X........... 2
cnt/LTimer<1> XXXXXXXXXXXXXXXX.XXX..X........X.X....X...X....... 24
cnt/LTimer<0> XXXXXXXXXXXXXXXX.XXXXXXXXXXXXXXX.X....X...X....... 34
2023-04-09 08:19:06 +00:00
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
2022-03-29 08:23:54 +00:00
*********************************** FB5 ***********************************
2023-07-13 20:03:30 +00:00
Number of function block inputs used/remaining: 33/21
Number of signals used by logic mapping into function block: 33
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-07-13 20:03:30 +00:00
ram/RS_FSM_FFd7 13 8<- 0 0 FB5_1 (b) (b)
nROMCS 2 2<- /\5 0 FB5_2 35 I/O O
(unused) 0 0 /\2 3 FB5_3 (b) (b)
(unused) 0 0 \/5 0 FB5_4 (b) (b)
nCAS 14 9<- 0 0 FB5_5 36 I/O O
nOE 3 2<- /\4 0 FB5_6 37 I/O O
ram/RASEN 11 8<- /\2 0 FB5_7 (b) (b)
(unused) 0 0 /\5 0 FB5_8 39 I/O (b)
RA<4> 2 0 /\3 0 FB5_9 40 I/O O
ram/RASEL 4 0 0 1 FB5_10 (b) (b)
2023-04-07 06:33:04 +00:00
RA<3> 2 0 0 3 FB5_11 41 I/O O
2023-07-13 20:03:30 +00:00
RA<5> 2 0 \/3 0 FB5_12 42 I/O O
ram/RASrr 12 7<- 0 0 FB5_13 (b) (b)
RA<2> 2 1<- /\4 0 FB5_14 43 I/O O
RA<6> 2 0 /\1 2 FB5_15 46 I/O O
(unused) 0 0 \/5 0 FB5_16 (b) (b)
2023-04-09 08:19:06 +00:00
(unused) 0 0 \/5 0 FB5_17 49 I/O (b)
2023-07-13 20:03:30 +00:00
RAMReady 12 10<- \/3 0 FB5_18 (b) (b)
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-07-13 20:03:30 +00:00
1: A_FSB<11> 12: A_FSB<5> 23: ram/RASEL
2: A_FSB<12> 13: A_FSB<7> 24: ram/RASEN
3: A_FSB<13> 14: RAMReady 25: ram/RASrr
4: A_FSB<16> 15: RefReq 26: ram/RS_FSM_FFd1
5: A_FSB<19> 16: RefUrg 27: ram/RS_FSM_FFd2
6: A_FSB<20> 17: cs/nOverlay 28: ram/RS_FSM_FFd3
7: A_FSB<21> 18: fsb/ASrf 29: ram/RS_FSM_FFd4
8: A_FSB<22> 19: nAS_FSB 30: ram/RS_FSM_FFd5
9: A_FSB<23> 20: nWE_FSB 31: ram/RS_FSM_FFd6
10: A_FSB<3> 21: ram/BACTr 32: ram/RS_FSM_FFd7
11: A_FSB<4> 22: ram/DTACKr 33: ram/RefDone
2023-04-09 08:19:06 +00:00
2023-07-13 20:03:30 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ram/RS_FSM_FFd7 .......XX.....XXXXX.X..X.X.X...XX....... 13
nROMCS .....XXXX.......X....................... 5
nCAS .......XX.....XX.XX.XX.X.XXXX.XXX....... 16
nOE .................XXXXX.................. 5
ram/RASEN .......XX.....XX.XX.X..X.XXXXXXXX....... 16
RA<4> X........X............X................. 3
ram/RASEL .......XX.......XXX...XX.XXXXXXX........ 14
RA<3> ....XX................X................. 3
RA<5> .X........X...........X................. 3
ram/RASrr .......XX.....XXXXX.X..XXXXXXXXXX....... 18
RA<2> ...X........X.........X................. 3
RA<6> ..X........X..........X................. 3
RAMReady .......XX....XXX.XX.X..X.XXXXXXXX....... 17
0----+----1----+----2----+----3----+----4
0 0 0 0
2022-03-29 08:23:54 +00:00
*********************************** FB6 ***********************************
2023-04-07 06:33:04 +00:00
Number of function block inputs used/remaining: 36/18
Number of signals used by logic mapping into function block: 36
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-04-07 06:33:04 +00:00
iobm/IOS_FSM_FFd6 2 0 0 3 FB6_1 (b) (b)
2022-03-29 08:23:54 +00:00
nVMA_IOB 3 0 0 2 FB6_2 74 I/O O
2023-04-07 06:33:04 +00:00
iobm/IOS_FSM_FFd7 3 0 0 2 FB6_3 (b) (b)
2023-04-01 08:46:47 +00:00
iobm/IOS_FSM_FFd3 3 0 0 2 FB6_4 (b) (b)
2023-04-07 06:33:04 +00:00
iobm/ES<0> 3 0 0 2 FB6_5 76 I/O I
iobm/ES<3> 4 0 0 1 FB6_6 77 I/O I
iobm/ES<1> 4 0 0 1 FB6_7 (b) (b)
iobm/DoutOE 4 0 \/1 0 FB6_8 78 I/O I
nLDS_IOB 6 1<- 0 0 FB6_9 79 I/O O
IODONE 4 0 \/1 0 FB6_10 (b) (b)
nUDS_IOB 6 1<- 0 0 FB6_11 80 I/O O
nAS_IOB 4 0 0 1 FB6_12 81 I/O O
iobm/IOS0 5 0 0 0 FB6_13 (b) (b)
2022-03-29 08:23:54 +00:00
nADoutLE1 2 0 0 3 FB6_14 82 I/O O
2023-04-01 08:46:47 +00:00
nADoutLE0 1 0 0 4 FB6_15 85 I/O O
2023-04-07 06:33:04 +00:00
ALE0M 5 0 0 0 FB6_16 (b) (b)
nDinLE 1 0 \/3 1 FB6_17 86 I/O O
IOACT 8 3<- 0 0 FB6_18 (b) (b)
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-04-07 06:33:04 +00:00
1: ALE0M 13: iobm/ES<1> 25: iobm/IOS_FSM_FFd7
2: ALE0S 14: iobm/ES<2> 26: iobm/IOWRREQr
3: E 15: iobm/ES<3> 27: iobm/VPAr
4: IOACT 16: iobm/Er 28: iobs/Clear1
5: IOBERR 17: iobm/IORDREQr 29: iobs/Load1
6: IODONE 18: iobm/IOS0 30: nADoutLE1
7: IOL0 19: iobm/IOS_FSM_FFd1 31: nAS_IOB
8: IOU0 20: iobm/IOS_FSM_FFd2 32: nAoutOE
9: nRES.PIN 21: iobm/IOS_FSM_FFd3 33: nDTACK_IOB
10: iobm/C8Mr 22: iobm/IOS_FSM_FFd4 34: nLDS_IOB
11: iobm/DoutOE 23: iobm/IOS_FSM_FFd5 35: nUDS_IOB
12: iobm/ES<0> 24: iobm/IOS_FSM_FFd6 36: nVMA_IOB
2022-03-29 08:23:54 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
2023-04-07 06:33:04 +00:00
iobm/IOS_FSM_FFd6 .........X......X.......XX.....X........ 5
nVMA_IOB ...X.......XXXX...........X....X...X.... 8
iobm/IOS_FSM_FFd7 .........X......X.X.....XX.....X........ 6
iobm/IOS_FSM_FFd3 ....XX...X..........XX.................. 5
iobm/ES<0> ..X........XXXXX........................ 6
iobm/ES<3> ..X........XXXXX........................ 6
iobm/ES<1> ..X........XXXXX........................ 6
iobm/DoutOE .........XX.........XXXXXX.............. 8
nLDS_IOB ......X..X......X...XXXXX......X.X...... 10
IODONE ........X..XXXX...............X.X..X.... 8
nUDS_IOB .......X.X......X...XXXXX......X..X..... 10
nAS_IOB .........X......X...XXXXXX.....X........ 9
iobm/IOS0 .........X......XXXXXXXXXX.....X........ 12
nADoutLE1 ...........................XXX.......... 3
2023-03-26 08:33:59 +00:00
nADoutLE0 XX...................................... 2
2023-04-07 06:33:04 +00:00
ALE0M X...............X.XXXXXXXX.....X........ 11
nDinLE ....................XX.................. 2
IOACT ...XXX...X......X.XXXXXXXX.....X........ 14
2022-03-29 08:23:54 +00:00
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
2023-04-09 08:19:06 +00:00
Number of function block inputs used/remaining: 41/13
Number of signals used by logic mapping into function block: 41
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-04-09 08:19:06 +00:00
cnt/LTimer<9> 3 1<- /\3 0 FB7_1 (b) (b)
RA<1> 2 0 /\1 2 FB7_2 50 I/O O
cnt/LTimer<8> 3 0 0 2 FB7_3 (b) (b)
cnt/LTimer<7> 3 0 0 2 FB7_4 (b) (b)
2023-03-22 01:11:58 +00:00
RA<7> 2 0 0 3 FB7_5 52 I/O O
2022-03-29 08:23:54 +00:00
RA<0> 2 0 0 3 FB7_6 53 I/O O
2023-04-09 08:19:06 +00:00
cnt/LTimer<6> 3 0 0 2 FB7_7 (b) (b)
2023-04-07 06:33:04 +00:00
RA<8> 2 0 0 3 FB7_8 54 I/O O
RA<10> 2 0 0 3 FB7_9 55 I/O O
2023-04-09 08:19:06 +00:00
cnt/LTimer<5> 3 0 0 2 FB7_10 (b) (b)
2023-03-22 01:11:58 +00:00
RA<9> 2 0 0 3 FB7_11 56 I/O O
C25MEN 0 0 0 5 FB7_12 58 I/O O
2023-04-09 08:19:06 +00:00
cnt/LTimer<4> 3 0 0 2 FB7_13 (b) (b)
cnt/LTimer<3> 3 0 0 2 FB7_14 59 I/O (b)
cnt/LTimer<2> 3 0 0 2 FB7_15 60 I/O (b)
cnt/LTimer<11> 3 0 0 2 FB7_16 (b) (b)
cnt/LTimer<10> 3 0 \/2 0 FB7_17 61 I/O (b)
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2
10 5<- 0 0 FB7_18 (b) (b)
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-07-13 20:03:30 +00:00
1: A_FSB<10> 15: A_FSB<23> 29: cnt/LTimer<2>
2: A_FSB<11> 16: A_FSB<2> 30: cnt/LTimer<3>
3: A_FSB<12> 17: A_FSB<6> 31: cnt/LTimer<4>
4: A_FSB<13> 18: A_FSB<7> 32: cnt/LTimer<5>
5: A_FSB<14> 19: A_FSB<8> 33: cnt/LTimer<6>
6: A_FSB<15> 20: A_FSB<9> 34: cnt/LTimer<7>
7: A_FSB<16> 21: cnt/Er<0> 35: cnt/LTimer<8>
8: A_FSB<17> 22: cnt/Er<1> 36: cnt/LTimer<9>
9: A_FSB<18> 23: cnt/IS_FSM_FFd1 37: cnt/TimerTC
10: A_FSB<19> 24: cnt/IS_FSM_FFd2 38: fsb/ASrf
11: A_FSB<1> 25: cnt/LTimer<0> 39: nAS_FSB
12: A_FSB<20> 26: cnt/LTimer<10> 40: nWE_FSB
13: A_FSB<21> 27: cnt/LTimer<11> 41: ram/RASEL
14: A_FSB<22> 28: cnt/LTimer<1>
2023-04-09 08:19:06 +00:00
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
2023-07-13 20:03:30 +00:00
cnt/LTimer<9> ....................XXXXX..XXXXXXXXXX............. 15
2023-04-09 08:19:06 +00:00
RA<1> X..............X........................X......... 3
2023-07-13 20:03:30 +00:00
cnt/LTimer<8> ....................XXXXX..XXXXXXXX.X............. 14
cnt/LTimer<7> ....................XXXXX..XXXXXXX..X............. 13
2023-04-09 08:19:06 +00:00
RA<7> ....X...........X.......................X......... 3
RA<0> ..........X........X....................X......... 3
2023-07-13 20:03:30 +00:00
cnt/LTimer<6> ....................XXXXX..XXXXXX...X............. 12
2023-04-09 08:19:06 +00:00
RA<8> ........X...X...........................X......... 3
RA<10> .......X.........X......................X......... 3
2023-07-13 20:03:30 +00:00
cnt/LTimer<5> ....................XXXXX..XXXXX....X............. 11
2023-04-09 08:19:06 +00:00
RA<9> .....X............X.....................X......... 3
C25MEN .................................................. 0
2023-07-13 20:03:30 +00:00
cnt/LTimer<4> ....................XXXXX..XXXX.....X............. 10
cnt/LTimer<3> ....................XXXXX..XXX......X............. 9
cnt/LTimer<2> ....................XXXXX..XX.......X............. 8
2023-04-09 08:19:06 +00:00
cnt/LTimer<11> ....................XXXXXXXXXXXXXXXXX............. 17
2023-07-13 20:03:30 +00:00
cnt/LTimer<10> ....................XXXXXX.XXXXXXXXXX............. 16
2023-04-09 08:19:06 +00:00
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2
XXXXXXXXXX.XXXX...XXXXXXXXXXXXXXXXXXXXXX.......... 36
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
2022-03-29 08:23:54 +00:00
*********************************** FB8 ***********************************
2023-04-09 08:19:06 +00:00
Number of function block inputs used/remaining: 41/13
Number of signals used by logic mapping into function block: 41
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
2023-04-09 08:19:06 +00:00
IOL0 16 11<- 0 0 FB8_1 (b) (b)
RA<11> 2 2<- /\5 0 FB8_2 63 I/O O
iobs/TS_FSM_FFd2 13 10<- /\2 0 FB8_3 (b) (b)
(unused) 0 0 /\5 0 FB8_4 (b) (b)
nRAS 3 3<- /\5 0 FB8_5 64 I/O O
nRAMLWE 1 0 /\3 1 FB8_6 65 I/O O
2023-04-07 06:33:04 +00:00
(unused) 0 0 \/1 4 FB8_7 (b) (b)
nRAMUWE 1 1<- \/5 0 FB8_8 66 I/O O
IOWRREQ 15 10<- 0 0 FB8_9 67 I/O (b)
(unused) 0 0 /\5 0 FB8_10 (b) (b)
2023-04-09 08:19:06 +00:00
(unused) 0 0 \/1 4 FB8_11 68 I/O (b)
nBERR_FSB 3 1<- \/3 0 FB8_12 70 I/O O
(unused) 0 0 \/5 0 FB8_13 (b) (b)
IOU0 16 11<- 0 0 FB8_14 71 I/O (b)
2023-04-07 06:33:04 +00:00
nBR_IOB 2 0 /\3 0 FB8_15 72 I/O O
2023-04-09 08:19:06 +00:00
cnt/IS_FSM_FFd1 1 0 \/4 0 FB8_16 (b) (b)
iobs/IORW1 8 4<- \/1 0 FB8_17 73 I/O (b)
(unused) 0 0 \/5 0 FB8_18 (b) (b)
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
2023-07-13 20:03:30 +00:00
1: A_FSB<13> 15: cnt/Er<0> 29: iobs/TS_FSM_FFd1
2: A_FSB<14> 16: cnt/Er<1> 30: iobs/TS_FSM_FFd2
3: A_FSB<16> 17: cnt/IS_FSM_FFd1 31: nADoutLE1
4: A_FSB<17> 18: cnt/IS_FSM_FFd2 32: nAS_FSB
5: A_FSB<18> 19: cnt/LTimerTC 33: nBERR_FSB
6: A_FSB<19> 20: cnt/TimerTC 34: nBR_IOB
2023-04-09 08:19:06 +00:00
7: A_FSB<20> 21: cnt/nIPL2r 35: nLDS_FSB
8: A_FSB<21> 22: cs/nOverlay 36: nUDS_FSB
9: A_FSB<22> 23: fsb/ASrf 37: nWE_FSB
2023-07-13 20:03:30 +00:00
10: A_FSB<23> 24: iobs/IOACTr 38: ram/RASEL
11: IOBERR 25: iobs/IOL1 39: ram/RASEN
2023-04-09 08:19:06 +00:00
12: IOL0 26: iobs/IORW1 40: ram/RASrf
13: IOU0 27: iobs/IOU1 41: ram/RASrr
14: IOWRREQ 28: iobs/Sent
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
IOL0 XXXXXXXXXX.X.........XX.X..XXXXX..X.X............. 21
2023-07-13 20:03:30 +00:00
RA<11> .....XX..............................X............ 3
2023-04-09 08:19:06 +00:00
iobs/TS_FSM_FFd2 XXXXXXXXXX...........XXX...XXXXX....X............. 19
2023-07-13 20:03:30 +00:00
nRAS ........XX...........X.........X......XXX......... 7
nRAMLWE ..................................X.XX............ 3
nRAMUWE ...................................XXX............ 3
2023-04-09 08:19:06 +00:00
IOWRREQ XXXXXXXXXX...X.......XXX.X.XXXXX....X............. 21
nBERR_FSB ..........X...........X....X...XX................. 5
IOU0 XXXXXXXXXX..X........XX...XXXXXX...XX............. 21
2023-07-13 20:03:30 +00:00
nBR_IOB ................XX..X............X................ 4
2023-04-09 08:19:06 +00:00
cnt/IS_FSM_FFd1 ..............XXXXXXX............................. 7
iobs/IORW1 XXXXXXXXXX............X..X.XXXXX....X............. 18
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
2022-03-29 08:23:54 +00:00
******************************* Equations ********************************
********** Mapped Logic **********
2023-04-09 08:19:06 +00:00
2023-07-13 20:03:30 +00:00
$OpTx$$OpTx$FX_DC$346_INV$533 <= (nAS_FSB AND NOT fsb/ASrf);
2023-04-09 08:19:06 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0');
2023-04-07 06:33:04 +00:00
ALE0M_D <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND nAoutOE)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
iobm/IOS_FSM_FFd1)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
iobm/IOS_FSM_FFd2)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT ALE0M)
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
NOT iobm/IORDREQr AND NOT iobm/IOWRREQr));
2022-03-29 08:23:54 +00:00
2023-04-01 08:46:47 +00:00
FDCPE_ALE0S: FDCPE port map (ALE0S,iobs/TS_FSM_FFd2,FCLK,'0','0');
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
C25MEN <= '1';
2022-03-29 08:23:54 +00:00
2023-03-25 07:49:44 +00:00
2023-04-01 12:20:02 +00:00
2023-07-13 20:03:30 +00:00
2023-04-01 12:20:02 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0');
2023-04-07 06:33:04 +00:00
IOACT_D <= ((iobm/IOS_FSM_FFd4)
OR (iobm/IOS_FSM_FFd5)
OR (iobm/IOS_FSM_FFd6)
OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3)
OR (iobm/IOS_FSM_FFd7 AND iobm/IOWRREQr AND NOT nAoutOE)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND IOACT AND
NOT iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2)
OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr)
OR (iobm/IOS_FSM_FFd7 AND iobm/IORDREQr AND NOT nAoutOE));
FDCPE_IOBERR: FDCPE port map (IOBERR,NOT nBERR_IOB,NOT C8M,nAS_IOB,'0');
FDCPE_IODONE: FDCPE port map (IODONE,IODONE_D,NOT C8M,nAS_IOB,'0');
IODONE_D <= ((NOT nRES.PIN)
OR (NOT nDTACK_IOB)
OR (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
iobm/ES(3)));
FTCPE_IOL0: FTCPE port map (IOL0,IOL0_T,FCLK,'0','0');
IOL0_T <= ((iobs/TS_FSM_FFd1)
2023-04-01 12:20:02 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(19) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(18) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-01 12:20:02 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(17) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND cs/nOverlay AND
2023-04-01 12:20:02 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (iobs/IORW1.EXP)
2023-04-07 06:33:04 +00:00
OR (NOT iobs/IOL1 AND NOT IOL0 AND NOT nADoutLE1)
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB AND
2023-04-01 12:20:02 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (nLDS_FSB AND NOT IOL0 AND nADoutLE1)
OR (NOT nLDS_FSB AND IOL0 AND nADoutLE1)
OR (iobs/IOL1 AND IOL0 AND NOT nADoutLE1));
FDCPE_IONPReady: FDCPE port map (IONPReady,IONPReady_D,FCLK,'0','0');
IONPReady_D <= ((NOT iobs/Sent AND NOT IONPReady)
OR (NOT IONPReady AND NOT iobs/IODONEr)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT nWE_FSB AND NOT IONPReady)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT nWE_FSB AND NOT IONPReady));
2023-04-07 06:33:04 +00:00
FDCPE_IORDREQ: FDCPE port map (IORDREQ,IORDREQ_D,FCLK,'0','0');
2023-07-13 20:03:30 +00:00
IORDREQ_D <= ((iobs/Load1.EXP)
OR (iobs/TS_FSM_FFd2 AND NOT IORDREQ)
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT nWE_FSB AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT iobs/IORW1 AND NOT iobs/TS_FSM_FFd2 AND NOT nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/TS_FSM_FFd2 AND
nADoutLE1)
OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
2023-07-13 20:03:30 +00:00
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr));
2023-04-07 06:33:04 +00:00
FTCPE_IOU0: FTCPE port map (IOU0,IOU0_T,FCLK,'0','0');
IOU0_T <= ((iobs/TS_FSM_FFd1)
2023-04-09 08:19:06 +00:00
OR (nBERR_FSB_OBUF.EXP)
2023-04-07 06:33:04 +00:00
OR (NOT iobs/IOU1 AND NOT IOU0 AND NOT nADoutLE1)
2023-04-01 08:46:47 +00:00
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
2023-03-26 08:33:59 +00:00
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20) AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(18) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(17) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16) AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (nUDS_FSB AND NOT IOU0 AND nADoutLE1)
OR (NOT nUDS_FSB AND IOU0 AND nADoutLE1)
OR (iobs/IOU1 AND IOU0 AND NOT nADoutLE1));
FDCPE_IOWRREQ: FDCPE port map (IOWRREQ,IOWRREQ_D,FCLK,'0','0');
IOWRREQ_D <= ((A_FSB(22) AND A_FSB(21) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (A_FSB(22) AND NOT iobs/Sent AND NOT cs/nOverlay AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(22) AND NOT iobs/Sent AND NOT cs/nOverlay AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
2023-04-09 08:19:06 +00:00
A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
2023-04-09 08:19:06 +00:00
A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
2023-04-09 08:19:06 +00:00
A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
2023-04-09 08:19:06 +00:00
A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2 AND IOWRREQ)
OR (iobs/TS_FSM_FFd2 AND NOT iobs/IOACTr AND IOWRREQ)
OR (NOT iobs/IORW1 AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND
NOT nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nWE_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1));
2023-03-25 07:49:44 +00:00
2023-04-09 08:19:06 +00:00
FDCPE_QoSReady: FDCPE port map (QoSReady,QoSReady_D,FCLK,'0','0');
QoSReady_D <= ((A_FSB(22) AND NOT A_FSB(17) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND NOT A_FSB(16) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND NOT A_FSB(13) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND NOT A_FSB(14) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533)
OR (nROMWE_OBUF.EXP)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(21) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(19) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(18) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(15) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(12) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533)
OR (A_FSB(23) AND NOT $OpTx$$OpTx$FX_DC$346_INV$533)
2023-04-09 08:19:06 +00:00
OR (NOT cnt/LTimer(0) AND NOT cnt/LTimer(1))
2023-07-13 20:03:30 +00:00
OR (NOT nWE_FSB AND NOT $OpTx$$OpTx$FX_DC$346_INV$533)
OR (QoSReady AND NOT $OpTx$$OpTx$FX_DC$346_INV$533)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(20) AND
2023-07-13 20:03:30 +00:00
NOT $OpTx$$OpTx$FX_DC$346_INV$533));
2023-04-09 08:19:06 +00:00
2022-03-29 08:23:54 +00:00
2023-04-07 06:33:04 +00:00
RA(0) <= ((ram/RASEL AND A_FSB(1))
OR (NOT ram/RASEL AND A_FSB(9)));
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
RA(1) <= ((A_FSB(10) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(2)));
2022-03-29 08:23:54 +00:00
2023-07-13 20:03:30 +00:00
RA(2) <= ((ram/RASEL AND A_FSB(7))
OR (A_FSB(16) AND NOT ram/RASEL));
2022-03-29 08:23:54 +00:00
2023-04-07 06:33:04 +00:00
RA(3) <= ((A_FSB(20) AND ram/RASEL)
OR (A_FSB(19) AND NOT ram/RASEL));
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
RA(4) <= ((A_FSB(11) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(3)));
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
RA(5) <= ((A_FSB(12) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(4)));
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
RA(6) <= ((A_FSB(13) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(5)));
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
RA(7) <= ((A_FSB(14) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(6)));
2022-03-29 08:23:54 +00:00
2023-03-22 01:11:58 +00:00
2023-04-07 06:33:04 +00:00
RA(8) <= ((A_FSB(21) AND ram/RASEL)
OR (A_FSB(18) AND NOT ram/RASEL));
2023-03-22 01:11:58 +00:00
2023-04-09 08:19:06 +00:00
RA(9) <= ((A_FSB(15) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(8)));
2023-03-22 01:11:58 +00:00
2023-04-07 06:33:04 +00:00
RA(10) <= ((A_FSB(17) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(7)));
2023-03-22 01:11:58 +00:00
2023-04-07 06:33:04 +00:00
RA(11) <= ((A_FSB(20) AND ram/RASEL)
OR (A_FSB(19) AND NOT ram/RASEL));
2023-03-22 01:11:58 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_RAMReady: FDCPE port map (RAMReady,RAMReady_D,FCLK,'0','0');
2023-07-13 20:03:30 +00:00
RAMReady_D <= ((EXP20_.EXP)
OR (NOT ram/RS_FSM_FFd7 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd5 AND NOT RAMReady)
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd7 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd4 AND
NOT ram/RS_FSM_FFd5)
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd7 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd4 AND
NOT ram/RS_FSM_FFd5)
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd7 AND
NOT ram/RASEN AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd4 AND
NOT ram/RS_FSM_FFd5)
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd7 AND
ram/RS_FSM_FFd3 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd4 AND
NOT ram/RS_FSM_FFd5)
OR (NOT ram/RS_FSM_FFd7 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd5 AND
ram/RS_FSM_FFd6)
OR (NOT ram/RS_FSM_FFd7 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd5 AND
ram/RS_FSM_FFd2));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE);
2023-04-09 08:19:06 +00:00
RefReq_D <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
cnt/Timer(3));
2023-03-26 08:33:59 +00:00
RefReq_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
FDCPE_RefUrg: FDCPE port map (RefUrg,RefUrg_D,FCLK,'0','0',RefUrg_CE);
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RefUrg_D <= (NOT cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3));
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RefUrg_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
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FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0');
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FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0');
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FTCPE_cnt/IS_FSM_FFd1: FTCPE port map (cnt/IS_FSM_FFd1,cnt/IS_FSM_FFd1_T,FCLK,'0','0');
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cnt/IS_FSM_FFd1_T <= (cnt/TimerTC AND NOT cnt/IS_FSM_FFd1 AND cnt/IS_FSM_FFd2 AND
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NOT cnt/Er(0) AND cnt/nIPL2r AND cnt/Er(1) AND cnt/LTimerTC);
FTCPE_cnt/IS_FSM_FFd2: FTCPE port map (cnt/IS_FSM_FFd2,cnt/IS_FSM_FFd2_T,FCLK,'0','0');
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cnt/IS_FSM_FFd2_T <= ((cnt/TimerTC AND cnt/IS_FSM_FFd1 AND cnt/IS_FSM_FFd2 AND
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NOT cnt/Er(0) AND cnt/Er(1) AND cnt/LTimerTC)
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OR (cnt/TimerTC AND NOT cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
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NOT cnt/Er(0) AND cnt/Er(1) AND cnt/LTimerTC));
FDCPE_cnt/LTimer0: FDCPE port map (cnt/LTimer(0),cnt/LTimer_D(0),FCLK,'0','0');
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cnt/LTimer_D(0) <= ((nAoutOE_OBUF.EXP)
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OR (NOT cnt/LTimer(0) AND cnt/LTimer(10) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/LTimer(8) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/LTimer(9) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/LTimer(11) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
A_FSB(8) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
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OR (cnt/LTimer(1).EXP)
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OR (NOT cnt/LTimer(0) AND cnt/LTimer(3) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/LTimer(4) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/LTimer(5) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/LTimer(6) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/LTimer(7) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (cnt/LTimer(0) AND
NOT cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/LTimer(1) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/LTimer(2) AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND NOT cnt/IS_FSM_FFd1 AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT cnt/LTimer(0) AND cnt/IS_FSM_FFd2 AND
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2));
FDCPE_cnt/LTimer1: FDCPE port map (cnt/LTimer(1),cnt/LTimer_D(1),FCLK,'0','0');
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cnt/LTimer_D(1) <= (($OpTx$$OpTx$FX_DC$346_INV$533.EXP)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
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A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
A_FSB(9) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
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A_FSB(8) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
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NOT nWE_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND A_FSB(8) AND
fsb/ASrf AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
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A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
A_FSB(9) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
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NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
A_FSB(8) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
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OR (NOT cnt/LTimer(0) AND NOT cnt/LTimer(1))
OR (NOT cnt/LTimer(1) AND
NOT cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
OR (cnt/LTimer(0) AND cnt/LTimer(1) AND
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cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2));
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FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0');
cnt/LTimer_T(2) <= ((cnt/LTimer(2) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/TimerTC AND
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NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND cnt/Er(1))
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/TimerTC AND
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cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)));
FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0');
cnt/LTimer_T(3) <= ((cnt/LTimer(3) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/TimerTC AND NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND cnt/Er(1))
OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/TimerTC AND cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)));
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FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0');
cnt/LTimer_T(4) <= ((cnt/LTimer(4) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/TimerTC AND NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND
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cnt/Er(1))
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/TimerTC AND cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND
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cnt/Er(1)));
FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0');
cnt/LTimer_T(5) <= ((cnt/LTimer(5) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/TimerTC AND NOT cnt/IS_FSM_FFd1 AND
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NOT cnt/Er(0) AND cnt/Er(1))
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/TimerTC AND cnt/IS_FSM_FFd2 AND
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NOT cnt/Er(0) AND cnt/Er(1)));
FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0');
cnt/LTimer_T(6) <= ((cnt/LTimer(6) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/TimerTC AND
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NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND cnt/Er(1))
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/TimerTC AND
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cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)));
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FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0');
cnt/LTimer_T(7) <= ((cnt/LTimer(7) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/TimerTC AND NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND cnt/Er(1))
OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/TimerTC AND cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)));
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FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0');
cnt/LTimer_T(8) <= ((cnt/LTimer(8) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/TimerTC AND NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND
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cnt/Er(1))
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/TimerTC AND cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND
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cnt/Er(1)));
FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0');
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cnt/LTimer_T(9) <= ((cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/TimerTC AND cnt/IS_FSM_FFd2 AND
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NOT cnt/Er(0) AND cnt/Er(1))
OR (cnt/LTimer(9) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/TimerTC AND NOT cnt/IS_FSM_FFd1 AND
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NOT cnt/Er(0) AND cnt/Er(1)));
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2023-04-09 08:19:06 +00:00
FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0');
cnt/LTimer_T(10) <= ((cnt/LTimer(10) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND cnt/TimerTC AND
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NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND cnt/Er(1))
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND cnt/TimerTC AND
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cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)));
FTCPE_cnt/LTimer11: FTCPE port map (cnt/LTimer(11),cnt/LTimer_T(11),FCLK,'0','0');
cnt/LTimer_T(11) <= ((cnt/LTimer(11) AND cnt/IS_FSM_FFd1 AND
NOT cnt/IS_FSM_FFd2)
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OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(10) AND
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND
cnt/TimerTC AND NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND cnt/Er(1))
OR (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(10) AND
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND
cnt/TimerTC AND cnt/IS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)));
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FDCPE_cnt/LTimerTC: FDCPE port map (cnt/LTimerTC,cnt/LTimerTC_D,FCLK,'0','0');
cnt/LTimerTC_D <= (NOT cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(10) AND
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND
cnt/LTimer(11));
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2 <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND A_FSB(9) AND
fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
NOT nWE_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND A_FSB(9) AND
fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
NOT nWE_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND A_FSB(8) AND
fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND A_FSB(8) AND
fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
A_FSB(9))
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OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1))
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OR (NOT cnt/LTimer(0) AND NOT cnt/LTimer(1) AND NOT cnt/LTimer(10) AND
NOT cnt/LTimer(2) AND NOT cnt/LTimer(3) AND NOT cnt/LTimer(4) AND NOT cnt/LTimer(5) AND
NOT cnt/LTimer(6) AND NOT cnt/LTimer(7) AND NOT cnt/LTimer(8) AND NOT cnt/LTimer(9) AND
NOT cnt/LTimer(11) AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
A_FSB(9))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
A_FSB(8))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
A_FSB(8)));
2023-03-26 08:33:59 +00:00
FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0));
2023-07-13 20:03:30 +00:00
cnt/Timer_T(0) <= (NOT cnt/Timer(0) AND cnt/TimerTC AND NOT cnt/Er(0) AND
cnt/Er(1));
2023-03-26 08:33:59 +00:00
cnt/Timer_CE(0) <= (NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/Timer1: FDCPE port map (cnt/Timer(1),cnt/Timer_D(1),FCLK,'0','0',cnt/Timer_CE(1));
2023-03-27 14:17:22 +00:00
cnt/Timer_D(1) <= ((cnt/Timer(0) AND cnt/Timer(1))
OR (NOT cnt/Timer(0) AND NOT cnt/Timer(1))
2023-07-13 20:03:30 +00:00
OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
2023-03-26 08:33:59 +00:00
cnt/Timer_CE(1) <= (NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/Timer2: FDCPE port map (cnt/Timer(2),cnt/Timer_D(2),FCLK,'0','0',cnt/Timer_CE(2));
2023-03-27 14:17:22 +00:00
cnt/Timer_D(2) <= ((NOT cnt/Timer(0) AND NOT cnt/Timer(2))
2023-03-26 08:33:59 +00:00
OR (NOT cnt/Timer(1) AND NOT cnt/Timer(2))
2023-07-13 20:03:30 +00:00
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2))
OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
2023-03-26 08:33:59 +00:00
cnt/Timer_CE(2) <= (NOT cnt/Er(0) AND cnt/Er(1));
2023-04-09 08:19:06 +00:00
FTCPE_cnt/Timer3: FTCPE port map (cnt/Timer(3),cnt/Timer_T(3),FCLK,'0','0',cnt/Timer_CE(3));
2023-07-13 20:03:30 +00:00
cnt/Timer_T(3) <= ((cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
NOT cnt/TimerTC)
2023-04-09 08:19:06 +00:00
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
cnt/Er(0))
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
2023-07-13 20:03:30 +00:00
NOT cnt/Er(1))
OR (cnt/Timer(3) AND cnt/TimerTC AND NOT cnt/Er(0) AND
cnt/Er(1)));
2023-04-09 08:19:06 +00:00
cnt/Timer_CE(3) <= (NOT cnt/Er(0) AND cnt/Er(1));
2023-07-13 20:03:30 +00:00
FDCPE_cnt/TimerTC: FDCPE port map (cnt/TimerTC,cnt/TimerTC_D,FCLK,'0','0',cnt/TimerTC_CE);
cnt/TimerTC_D <= (cnt/Timer(0) AND NOT cnt/Timer(1) AND NOT cnt/Timer(2) AND
cnt/Timer(3));
cnt/TimerTC_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
2023-04-09 08:19:06 +00:00
FTCPE_cnt/WS0: FTCPE port map (cnt/WS(0),cnt/WS_T(0),FCLK,'0','0');
cnt/WS_T(0) <= (nAS_FSB AND NOT cnt/WS(0) AND NOT fsb/ASrf);
FDCPE_cnt/WS1: FDCPE port map (cnt/WS(1),cnt/WS_D(1),FCLK,'0','0');
cnt/WS_D(1) <= ((nAS_FSB AND NOT fsb/ASrf)
2023-07-13 20:03:30 +00:00
OR (cnt/WS(0) AND cnt/WS(1))
OR (NOT cnt/WS(0) AND NOT cnt/WS(1)));
2023-04-09 08:19:06 +00:00
FTCPE_cnt/WS2: FTCPE port map (cnt/WS(2),cnt/WS_T(2),FCLK,'0','0');
cnt/WS_T(2) <= ((nAS_FSB AND cnt/WS(2) AND NOT fsb/ASrf)
OR (NOT nAS_FSB AND cnt/WS(0) AND cnt/WS(1))
OR (cnt/WS(0) AND cnt/WS(1) AND fsb/ASrf));
FTCPE_cnt/WS3: FTCPE port map (cnt/WS(3),cnt/WS_T(3),FCLK,'0','0');
2023-07-13 20:03:30 +00:00
cnt/WS_T(3) <= ((NOT nAS_FSB AND cnt/WS(0) AND cnt/WS(1) AND cnt/WS(2))
OR (cnt/WS(0) AND cnt/WS(1) AND cnt/WS(2) AND fsb/ASrf)
OR (nAS_FSB AND cnt/WS(3) AND NOT fsb/ASrf));
2023-03-26 08:33:59 +00:00
FDCPE_cnt/nIPL2r: FDCPE port map (cnt/nIPL2r,nIPL2,FCLK,'0','0');
2023-04-01 08:46:47 +00:00
FTCPE_cs/nOverlay: FTCPE port map (cs/nOverlay,cs/nOverlay_T,FCLK,'0','0');
cs/nOverlay_T <= ((NOT nRES.PIN AND cs/nOverlay AND nAS_FSB AND NOT fsb/ASrf)
2023-07-13 20:03:30 +00:00
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay AND NOT nAS_FSB)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay AND fsb/ASrf));
2023-03-26 08:33:59 +00:00
2023-04-01 08:46:47 +00:00
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT FCLK,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/C8Mr: FDCPE port map (iobm/C8Mr,C8M,C16M,'0','0');
FTCPE_iobm/DoutOE: FTCPE port map (iobm/DoutOE,iobm/DoutOE_T,C16M,'0','0');
iobm/DoutOE_T <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND NOT iobm/DoutOE AND
iobm/IOWRREQr)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
iobm/DoutOE)
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
iobm/DoutOE)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND iobm/DoutOE AND NOT iobm/IOWRREQr));
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),NOT C8M,'0','0');
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT E AND iobm/Er)
OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
NOT iobm/ES(3) AND E)
OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
NOT iobm/ES(3) AND NOT iobm/Er));
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),NOT C8M,'0','0');
2023-03-26 08:33:59 +00:00
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
2023-04-07 06:33:04 +00:00
OR (NOT E AND iobm/Er)
OR (iobm/ES(0) AND NOT iobm/ES(2) AND iobm/ES(3)));
FTCPE_iobm/ES2: FTCPE port map (iobm/ES(2),iobm/ES_T(2),NOT C8M,'0','0');
iobm/ES_T(2) <= ((iobm/ES(0) AND iobm/ES(1) AND E)
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/Er)
OR (iobm/ES(2) AND NOT E AND iobm/Er));
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),NOT C8M,'0','0');
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT E AND iobm/Er)
OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND E)
OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND NOT iobm/Er)
OR (iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
iobm/ES(3)));
2023-03-26 08:33:59 +00:00
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0');
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IORDREQr: FDCPE port map (iobm/IORDREQr,IORDREQ,C16M,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IOS0: FDCPE port map (iobm/IOS0,iobm/IOS0_D,C16M,'0','0');
iobm/IOS0_D <= ((iobm/IOS_FSM_FFd1)
OR (iobm/IOS_FSM_FFd7 AND iobm/C8Mr)
OR (iobm/IOS_FSM_FFd7 AND nAoutOE)
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IORDREQr AND
NOT iobm/IOWRREQr)
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
NOT iobm/IOS_FSM_FFd2 AND iobm/IOS0));
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,C16M,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-01 08:46:47 +00:00
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,C16M,'0','0');
2023-04-07 06:33:04 +00:00
iobm/IOS_FSM_FFd2_D <= ((IOBERR AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr)
OR (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr));
2023-03-26 08:33:59 +00:00
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0');
2023-04-07 06:33:04 +00:00
iobm/IOS_FSM_FFd3_D <= ((iobm/IOS_FSM_FFd4)
OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr)
OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3));
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,C16M,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,C16M,'0','0');
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd6_D,C16M,'0','0');
iobm/IOS_FSM_FFd6_D <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IORDREQr AND
NOT nAoutOE)
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IOWRREQr AND
NOT nAoutOE));
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,C16M,'0','0');
iobm/IOS_FSM_FFd7_D <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd1)
OR (NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd1 AND iobm/IORDREQr AND
NOT nAoutOE)
OR (NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd1 AND iobm/IOWRREQr AND
NOT nAoutOE));
FDCPE_iobm/IOWRREQr: FDCPE port map (iobm/IOWRREQr,IOWRREQ,C16M,'0','0');
FDCPE_iobm/VPAr: FDCPE port map (iobm/VPAr,NOT nVPA_IOB,NOT C8M,'0','0');
2023-03-26 08:33:59 +00:00
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
iobs/Clear1_D <= (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2);
2023-03-26 08:33:59 +00:00
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
FDCPE_iobs/IODONEr: FDCPE port map (iobs/IODONEr,IODONE,FCLK,'0','0');
2023-04-01 08:46:47 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1);
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
iobs/IORW1_T <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND
fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND
fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND
fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND
fsb/ASrf AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
iobs/TS_FSM_FFd1 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
iobs/TS_FSM_FFd1 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND
iobs/TS_FSM_FFd2 AND nADoutLE1));
2023-03-26 08:33:59 +00:00
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1);
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
iobs/Load1_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-13 20:03:30 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd1 AND
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-13 20:03:30 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND
2023-04-09 08:19:06 +00:00
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd2 AND
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd1 AND
nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND iobs/TS_FSM_FFd2 AND
nADoutLE1));
2023-04-01 12:20:02 +00:00
FTCPE_iobs/Sent: FTCPE port map (iobs/Sent,iobs/Sent_T,FCLK,'0','0');
2023-07-13 20:03:30 +00:00
iobs/Sent_T <= ((A_FSB(22) AND A_FSB(21) AND NOT iobs/Sent AND
2023-04-09 08:19:06 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
2023-04-01 12:20:02 +00:00
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Sent AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND NOT iobs/Sent AND NOT cs/nOverlay AND NOT nAS_FSB AND
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-01 12:20:02 +00:00
OR (A_FSB(22) AND NOT iobs/Sent AND NOT cs/nOverlay AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-07-13 20:03:30 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND
NOT iobs/Sent AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
2023-07-13 20:03:30 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
NOT iobs/Sent AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
2023-04-01 12:20:02 +00:00
OR (iobs/Sent AND nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nAS_FSB AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND
NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Sent AND NOT nAS_FSB AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Sent AND NOT nAS_FSB AND
2023-04-07 06:33:04 +00:00
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
2023-04-01 08:46:47 +00:00
FDCPE_iobs/TS_FSM_FFd1: FDCPE port map (iobs/TS_FSM_FFd1,iobs/TS_FSM_FFd1_D,FCLK,'0','0');
iobs/TS_FSM_FFd1_D <= ((iobs/TS_FSM_FFd2)
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr));
FDCPE_iobs/TS_FSM_FFd2: FDCPE port map (iobs/TS_FSM_FFd2,iobs/TS_FSM_FFd2_D,FCLK,'0','0');
2023-04-09 08:19:06 +00:00
iobs/TS_FSM_FFd2_D <= ((nRAS_OBUF.EXP)
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT fsb/ASrf AND
nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
2023-04-01 12:20:02 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-09 08:19:06 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20) AND
2023-04-01 12:20:02 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16) AND
2023-04-01 12:20:02 +00:00
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB AND
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
2023-04-07 06:33:04 +00:00
OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
2023-04-01 08:46:47 +00:00
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)
2023-04-09 08:19:06 +00:00
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
2023-03-26 08:33:59 +00:00
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0');
nADoutLE1_D <= ((iobs/Load1)
OR (NOT iobs/Clear1 AND NOT nADoutLE1));
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0');
2023-04-07 06:33:04 +00:00
nAS_IOB <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IORDREQr AND
NOT iobm/IOWRREQr));
2023-03-26 08:33:59 +00:00
nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z';
nAS_IOB_OE <= NOT nAoutOE;
FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0');
2023-04-09 08:19:06 +00:00
nAoutOE_D <= ((NOT nBR_IOB AND cnt/IS_FSM_FFd1 AND cnt/IS_FSM_FFd2)
OR (cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND NOT nAoutOE));
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_nBERR_FSB: FDCPE port map (nBERR_FSB,nBERR_FSB_D,FCLK,'0','0');
2023-04-09 08:19:06 +00:00
nBERR_FSB_D <= ((NOT IOBERR AND nBERR_FSB)
OR (NOT iobs/Sent AND nBERR_FSB)
2023-04-07 06:33:04 +00:00
OR (nAS_FSB AND NOT fsb/ASrf));
2023-03-26 08:33:59 +00:00
FTCPE_nBR_IOB: FTCPE port map (nBR_IOB,nBR_IOB_T,FCLK,'0','0');
2023-04-09 08:19:06 +00:00
nBR_IOB_T <= ((nBR_IOB AND NOT cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2)
OR (NOT nBR_IOB AND NOT cnt/IS_FSM_FFd1 AND cnt/IS_FSM_FFd2 AND
NOT cnt/nIPL2r));
2023-03-26 08:33:59 +00:00
2023-07-13 20:03:30 +00:00
FDCPE_nCAS: FDCPE port map (nCAS,nCAS_D,NOT FCLK,'0','0');
nCAS_D <= ((ram/RS_FSM_FFd1)
OR (ram/RS_FSM_FFd2)
OR (ram/RefDone AND ram/RS_FSM_FFd7)
OR (ram/RefDone AND ram/RS_FSM_FFd3)
OR (ram/RS_FSM_FFd4 AND ram/DTACKr)
OR (NOT RefUrg AND NOT RefReq AND ram/RS_FSM_FFd7)
OR (NOT RefUrg AND ram/RS_FSM_FFd7 AND ram/BACTr)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT RefUrg AND
ram/RS_FSM_FFd7)
OR (NOT RefUrg AND nAS_FSB AND ram/RS_FSM_FFd7 AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
ram/RS_FSM_FFd7 AND ram/RASEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND ram/RS_FSM_FFd7 AND
ram/RASEN AND fsb/ASrf)
OR (NOT RefUrg AND ram/RS_FSM_FFd3)
OR (NOT RefUrg AND ram/RS_FSM_FFd6)
OR (ram/RefDone AND ram/RS_FSM_FFd6));
2023-03-26 08:33:59 +00:00
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0','0');
2023-07-13 20:03:30 +00:00
nDTACK_FSB_D <= ((cnt/WS(3).EXP)
2023-04-07 06:33:04 +00:00
OR (A_FSB(23) AND NOT IONPReady)
2023-07-13 20:03:30 +00:00
OR (NOT IONPReady AND NOT QoSReady)
2023-04-01 08:46:47 +00:00
OR (nAS_FSB AND NOT fsb/ASrf)
2023-04-07 06:33:04 +00:00
OR (A_FSB(22) AND A_FSB(21) AND NOT IONPReady)
2023-04-09 08:19:06 +00:00
OR (A_FSB(22) AND A_FSB(20) AND NOT IONPReady));
2023-03-22 01:11:58 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0');
2023-04-07 06:33:04 +00:00
nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
2022-03-29 08:23:54 +00:00
2023-03-27 14:17:22 +00:00
nDinOE <= NOT (((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
2023-04-01 12:20:02 +00:00
OR (A_FSB(22) AND A_FSB(21) AND nWE_FSB AND NOT nAS_FSB)
OR (A_FSB(22) AND A_FSB(20) AND nWE_FSB AND NOT nAS_FSB)));
2023-03-22 01:11:58 +00:00
2022-03-29 08:23:54 +00:00
2023-04-09 08:19:06 +00:00
nDoutOE <= NOT (((iobm/DoutOE AND NOT nAoutOE)
OR (NOT iobm/IORDREQr AND iobm/IOS0 AND NOT iobm/IOWRREQr AND
NOT nAoutOE)));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0');
2023-04-07 06:33:04 +00:00
nLDS_IOB <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND IOL0 AND
iobm/IORDREQr)
OR (iobm/IOS_FSM_FFd3 AND IOL0)
OR (iobm/IOS_FSM_FFd4 AND IOL0)
OR (iobm/IOS_FSM_FFd5 AND IOL0)
OR (NOT nLDS_IOB AND iobm/IOS_FSM_FFd6 AND IOL0));
2023-03-26 08:33:59 +00:00
nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z';
nLDS_IOB_OE <= NOT nAoutOE;
2022-03-29 08:23:54 +00:00
2023-07-13 20:03:30 +00:00
FDCPE_nOE: FDCPE port map (nOE,nOE_D,FCLK,'0','0');
nOE_D <= ((NOT nWE_FSB)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (ram/DTACKr AND ram/BACTr));
2022-03-29 08:23:54 +00:00
2023-07-13 20:03:30 +00:00
nRAMLWE <= NOT ((NOT nWE_FSB AND NOT nLDS_FSB AND ram/RASEL));
2022-03-29 08:23:54 +00:00
2023-07-13 20:03:30 +00:00
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND ram/RASEL));
2022-03-29 08:23:54 +00:00
2023-04-01 12:20:02 +00:00
2023-07-13 20:03:30 +00:00
nRAS <= NOT (((ram/RASrr)
OR (ram/RASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
ram/RASEN)));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
nRES_I <= '0';
nRES <= nRES_I when nRES_OE = '1' else 'Z';
nRES_OE <= NOT nRESout;
2023-03-22 01:11:58 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0');
2023-04-09 08:19:06 +00:00
nRESout_D <= (cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2);
2023-03-22 01:11:58 +00:00
2022-03-29 08:23:54 +00:00
2023-03-27 14:17:22 +00:00
nROMCS <= NOT (((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20))
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND NOT cs/nOverlay)));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
nROMWE <= NOT ((NOT nWE_FSB AND NOT nAS_FSB));
2022-03-29 08:23:54 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0');
2023-04-07 06:33:04 +00:00
nUDS_IOB <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND IOU0 AND
iobm/IORDREQr)
OR (iobm/IOS_FSM_FFd3 AND IOU0)
OR (iobm/IOS_FSM_FFd4 AND IOU0)
OR (iobm/IOS_FSM_FFd5 AND IOU0)
OR (NOT nUDS_IOB AND iobm/IOS_FSM_FFd6 AND IOU0));
2023-03-26 08:33:59 +00:00
nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z';
nUDS_IOB_OE <= NOT nAoutOE;
2022-03-29 08:23:54 +00:00
2023-04-07 06:33:04 +00:00
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,C8M,'0','0');
nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
NOT iobm/ES(3))
OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(2) AND NOT iobm/ES(1) AND
NOT iobm/ES(3) AND IOACT AND iobm/VPAr));
2023-03-26 08:33:59 +00:00
nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z';
nVMA_IOB_OE <= NOT nAoutOE;
2022-03-29 08:23:54 +00:00
2023-04-07 06:33:04 +00:00
FDCPE_nVPA_FSB: FDCPE port map (nVPA_FSB,nVPA_FSB_D,FCLK,'0',nAS_FSB);
nVPA_FSB_D <= ((A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND IONPReady AND
2023-07-13 20:03:30 +00:00
NOT nAS_FSB)
2023-04-07 06:33:04 +00:00
OR (A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
2023-04-09 08:19:06 +00:00
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND IONPReady AND
2023-07-13 20:03:30 +00:00
fsb/ASrf));
2023-03-26 08:33:59 +00:00
2023-07-13 20:03:30 +00:00
FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,FCLK,'0','0');
ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
2023-03-26 08:33:59 +00:00
2023-07-13 20:03:30 +00:00
FDCPE_ram/DTACKr: FDCPE port map (ram/DTACKr,NOT nDTACK_FSB,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
2023-07-13 20:03:30 +00:00
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,FCLK,'0','0');
ram/RASEL_D <= ((ram/RS_FSM_FFd5)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
ram/RS_FSM_FFd7 AND ram/RASEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
ram/RS_FSM_FFd7 AND ram/RASEN AND fsb/ASrf)
OR (ram/RASEL AND NOT ram/RS_FSM_FFd7 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd6 AND
NOT ram/RS_FSM_FFd2));
FDCPE_ram/RASEN: FDCPE port map (ram/RASEN,ram/RASEN_D,FCLK,'0','0');
ram/RASEN_D <= ((ram/RS_FSM_FFd1)
OR (RA_4_OBUF.EXP)
OR (ram/RefDone AND ram/RS_FSM_FFd7)
OR (ram/RefDone AND ram/RS_FSM_FFd3)
OR (NOT RefUrg AND NOT RefReq AND ram/RS_FSM_FFd7)
OR (NOT RefUrg AND ram/RS_FSM_FFd7 AND ram/BACTr)
OR (NOT RefUrg AND nAS_FSB AND ram/RS_FSM_FFd7 AND NOT fsb/ASrf)
OR (NOT RefUrg AND ram/RS_FSM_FFd3)
OR (NOT ram/RS_FSM_FFd7 AND NOT ram/RS_FSM_FFd3 AND ram/RASEN AND
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6 AND
NOT ram/RS_FSM_FFd2));
FDCPE_ram/RASrf: FDCPE port map (ram/RASrf,ram/RASrf_D,NOT FCLK,'0','0');
ram/RASrf_D <= (NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6);
2023-04-07 06:33:04 +00:00
FDCPE_ram/RASrr: FDCPE port map (ram/RASrr,ram/RASrr_D,FCLK,'0','0');
2023-07-13 20:03:30 +00:00
ram/RASrr_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
ram/RS_FSM_FFd7 AND ram/RASEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
ram/RS_FSM_FFd7 AND ram/RASEN AND fsb/ASrf)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
ram/RS_FSM_FFd7 AND NOT ram/BACTr)
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
ram/RS_FSM_FFd7 AND NOT ram/BACTr)
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
ram/RS_FSM_FFd7 AND NOT ram/BACTr AND fsb/ASrf)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
ram/RS_FSM_FFd7 AND NOT ram/BACTr AND fsb/ASrf)
OR (NOT ram/RS_FSM_FFd7 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd5 AND
NOT ram/RS_FSM_FFd6 AND NOT ram/RS_FSM_FFd2 AND ram/RASrr)
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd3)
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd7)
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd7)
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd7 AND
NOT ram/RASEN)
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
ram/RS_FSM_FFd7 AND NOT fsb/ASrf));
2023-04-07 06:33:04 +00:00
FDCPE_ram/RS_FSM_FFd1: FDCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd2,FCLK,'0','0');
2023-07-13 20:03:30 +00:00
FDCPE_ram/RS_FSM_FFd2: FDCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd6,FCLK,'0','0');
2023-04-07 06:33:04 +00:00
2023-07-13 20:03:30 +00:00
FDCPE_ram/RS_FSM_FFd3: FDCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_D,FCLK,'0','0');
ram/RS_FSM_FFd3_D <= (ram/RS_FSM_FFd4 AND ram/DTACKr);
2023-04-07 06:33:04 +00:00
FDCPE_ram/RS_FSM_FFd4: FDCPE port map (ram/RS_FSM_FFd4,ram/RS_FSM_FFd4_D,FCLK,'0','0');
2023-07-13 20:03:30 +00:00
ram/RS_FSM_FFd4_D <= ((ram/RS_FSM_FFd5)
OR (ram/RS_FSM_FFd4 AND NOT ram/DTACKr));
2023-04-07 06:33:04 +00:00
2023-07-13 20:03:30 +00:00
FDCPE_ram/RS_FSM_FFd5: FDCPE port map (ram/RS_FSM_FFd5,ram/RS_FSM_FFd5_D,FCLK,'0','0');
ram/RS_FSM_FFd5_D <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
ram/RS_FSM_FFd7 AND ram/RASEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
ram/RS_FSM_FFd7 AND ram/RASEN AND fsb/ASrf));
2023-04-07 06:33:04 +00:00
FDCPE_ram/RS_FSM_FFd6: FDCPE port map (ram/RS_FSM_FFd6,ram/RS_FSM_FFd6_D,FCLK,'0','0');
2023-07-13 20:03:30 +00:00
ram/RS_FSM_FFd6_D <= ((A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
ram/RS_FSM_FFd7 AND NOT ram/BACTr)
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
ram/RS_FSM_FFd7 AND NOT ram/BACTr AND fsb/ASrf)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
ram/RS_FSM_FFd7 AND NOT ram/BACTr)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
ram/RS_FSM_FFd7 AND NOT ram/BACTr AND fsb/ASrf)
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd3)
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd7)
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
ram/RS_FSM_FFd7)
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd7 AND
NOT ram/RASEN)
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OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
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ram/RS_FSM_FFd7 AND NOT fsb/ASrf));
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FDCPE_ram/RS_FSM_FFd7: FDCPE port map (ram/RS_FSM_FFd7,ram/RS_FSM_FFd7_D,FCLK,'0','0');
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ram/RS_FSM_FFd7_D <= ((A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd3 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd3 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
NOT ram/RS_FSM_FFd3 AND ram/RASEN AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd3 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd3 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd7 AND
NOT ram/RS_FSM_FFd1)
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OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
2023-07-13 20:03:30 +00:00
NOT ram/RS_FSM_FFd1 AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd3 AND ram/RASEN AND NOT ram/RS_FSM_FFd1)
OR (NOT ram/RS_FSM_FFd7 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RS_FSM_FFd1)
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1)
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1)
OR (RefUrg AND cs/nOverlay AND NOT ram/RefDone AND
NOT ram/RS_FSM_FFd1)
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
NOT ram/RS_FSM_FFd1));
2023-03-22 01:11:58 +00:00
2023-03-26 08:33:59 +00:00
FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0');
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ram/RefDone_D <= ((NOT RefUrg AND NOT RefReq)
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OR (NOT ram/RefDone AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd6 AND
NOT ram/RS_FSM_FFd2));
2023-03-22 01:11:58 +00:00
2022-03-29 08:23:54 +00:00
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC95144XL-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 51 VCC
2 A_FSB<5> 52 RA<7>
3 A_FSB<6> 53 RA<0>
4 A_FSB<7> 54 RA<8>
5 VCC 55 RA<10>
6 A_FSB<8> 56 RA<9>
7 A_FSB<9> 57 VCC
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8 A_FSB<10> 58 C25MEN
2023-04-09 08:19:06 +00:00
9 A_FSB<11> 59 KPR
2023-03-22 01:11:58 +00:00
10 A_FSB<12> 60 KPR
11 A_FSB<13> 61 KPR
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12 A_FSB<14> 62 GND
13 A_FSB<15> 63 RA<11>
14 A_FSB<16> 64 nRAS
15 A_FSB<17> 65 nRAMLWE
16 A_FSB<18> 66 nRAMUWE
17 A_FSB<19> 67 KPR
18 A_FSB<20> 68 KPR
19 A_FSB<21> 69 GND
20 A_FSB<22> 70 nBERR_FSB
21 GND 71 KPR
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22 C16M 72 nBR_IOB
2023-03-25 07:49:44 +00:00
23 C8M 73 KPR
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24 A_FSB<23> 74 nVMA_IOB
2023-03-22 01:11:58 +00:00
25 E 75 GND
2022-03-29 08:23:54 +00:00
26 VCC 76 nBERR_IOB
2023-03-22 01:11:58 +00:00
27 FCLK 77 nVPA_IOB
2022-03-29 08:23:54 +00:00
28 nDTACK_FSB 78 nDTACK_IOB
29 nWE_FSB 79 nLDS_IOB
30 nLDS_FSB 80 nUDS_IOB
31 GND 81 nAS_IOB
32 nAS_FSB 82 nADoutLE1
33 nUDS_FSB 83 TDO
34 nROMWE 84 GND
35 nROMCS 85 nADoutLE0
36 nCAS 86 nDinLE
37 nOE 87 nAoutOE
38 VCC 88 VCC
39 KPR 89 nDoutOE
40 RA<4> 90 nDinOE
41 RA<3> 91 nRES
42 RA<5> 92 nIPL2
43 RA<2> 93 nVPA_FSB
44 GND 94 A_FSB<1>
45 TDI 95 A_FSB<2>
46 RA<6> 96 A_FSB<3>
47 TMS 97 A_FSB<4>
48 TCK 98 VCC
49 KPR 99 KPR
50 RA<1> 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
2023-03-26 08:33:59 +00:00
Pterm Limit : 25
2022-03-29 08:23:54 +00:00
</pre>
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