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Warp-SE
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This commit is contained in:
Zane Kaminski 2023-03-20 01:13:11 -04:00
parent fb6b6debcc
commit a2fc4dc4de
16 changed files with 152 additions and 144 deletions
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19
cpld/CNT.v
View File

@ -49,8 +49,8 @@ module CNT(
*/ */
assign RefUrgent = Timer[6]; assign RefUrgent = Timer[6];
always @(posedge C8M) begin always @(posedge C8M) begin
if (Timer[3]) RefREQ <= 1; if (Timer[3]) RefReq <= 1;
else if (TimerTC) RefREQ <= 0; else if (TimerTC) RefReq <= 0;
end end
/* LBACTr - LBACT synchronized to C16M clock domain */ /* LBACTr - LBACT synchronized to C16M clock domain */
@ -59,7 +59,6 @@ module CNT(
/* BERR generation in C8M clock domain */ /* BERR generation in C8M clock domain */
reg BERRArm = 0; reg BERRArm = 0;
reg BERRTimeout = 0;
always @(posedge C8M) begin always @(posedge C8M) begin
if (LBACTr && TimerTC) begin if (LBACTr && TimerTC) begin
BERRArm <= 1; BERRArm <= 1;
@ -72,17 +71,21 @@ module CNT(
/* Long timer counts from 0 to 16384 -- 16385 states == 202.888 ms */ /* Long timer counts from 0 to 16384 -- 16385 states == 202.888 ms */
reg [14:0] LTimer; // Long timer reg [14:0] LTimer; // Long timer
wire LTimerTC <= LTimer[14]; wire LTimerTC = LTimer[14];
always @(posedge C8M) begin always @(posedge C8M) begin
if (LTimerTC) LTimer <= 0; if (LTimerTC) LTimer <= 0;
else LTimer <= LTimer+1; else LTimer <= LTimer+1;
end end
/* IPL2 synchronizer */
reg IPL2r;
always @(posedge C8M) IPL2r <= !nIPL2;
/* Startup sequence control */ /* Startup sequence control */
reg [1:0] PORS = 0; reg [1:0] PORS = 0;
reg Disable = 0; reg Disable = 0;
reg BR_IOB = 0; assign nBR_IOB <= !BR_IOB; reg BR_IOB = 0; assign nBR_IOB = !BR_IOB;
assign nAoutOE <= !AoutOE; assign nAoutOE = !AoutOE;
always @(posedge C8M) begin always @(posedge C8M) begin
case (PORS) case (PORS)
0: begin 0: begin
@ -93,7 +96,7 @@ module CNT(
end 1: begin end 1: begin
AoutOE <= 0; // Tristate PDS address and control AoutOE <= 0; // Tristate PDS address and control
nRESout <= 0; // Hold reset low nRESout <= 0; // Hold reset low
Disable <= Disable | !nIPL2; // No need to synchronize /IPL2 Disable <= Disable | IPL2r;
if (!IPL2r && LTimerTC) begin if (!IPL2r && LTimerTC) begin
BR_IOB <= !Disable; BR_IOB <= !Disable;
PORS <= 2; PORS <= 2;

23
cpld/FSB.v
View File

@ -5,8 +5,8 @@ module FSB(
output BACT, output LBACT, output BACT, output LBACT,
/* Ready inputs */ /* Ready inputs */
input Ready0, input Ready1, input Ready2, input Ready0, input Ready1, input Ready2,
/* BERR inputs */ /* BERR input from IOB slave port */
input BERR0, input BERR1, input IOBS_BERR,
/* Interrupt acknowledge select */ /* Interrupt acknowledge select */
input IACS); input IACS);
@ -17,7 +17,6 @@ module FSB(
/* LBACT - "Long BACT" */ /* LBACT - "Long BACT" */
reg [1:0] BACTCnt = 0; reg [1:0] BACTCnt = 0;
reg LBACT;
always @(posedge FCLK) begin always @(posedge FCLK) begin
if (!BACT) begin if (!BACT) begin
BACTCnt <= 0; BACTCnt <= 0;
@ -46,21 +45,7 @@ module FSB(
end end
/* BERR generation */ /* BERR generation */
reg BERR0r, BERR1r; assign nBERR = ~(~nAS && IOBS_BERR);
always @(posedge FCLK) BERR0r <= BERR0;
always @(posedge FCLK) BERR1r <= BERR1;
reg BERREN = 0;
reg BERRCNT = 0;
always @(posedge FCLK) begin
if (~BACT) begin
BERREN <= 0;
BERRCNT <= 0;
end else begin
BERRCNT <= BERRCNT+1;
BERREN <= BERRCNT==3'b111;
end
end
assign nBERR = ~(~nAS && BERREN && (BERR0r || BERR1r));
/* DTACK/VPA control */ /* DTACK/VPA control */
reg VPA; reg VPA;
@ -69,7 +54,7 @@ module FSB(
if (~BACT) begin if (~BACT) begin
nDTACK <= 1; nDTACK <= 1;
VPA <= 0; VPA <= 0;
end else if (Ready && ~BERR) begin end else if (Ready) begin
nDTACK <= IACS; nDTACK <= IACS;
VPA <= IACS; VPA <= IACS;
end end

4
cpld/IOBM.v
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@ -107,8 +107,8 @@ module IOBM(
end end
/* PDS address and data latch control */ /* PDS address and data latch control */
always @(negedge C16M) begin nDinLE <= IOS==4 || IOS==5; end always @(negedge C16M) begin nDinLE = IOS==4 || IOS==5; end
reg DoutOE = 0; assign nDoutOE <= !(AoutOE && DoutOE); reg DoutOE = 0; assign nDoutOE = !(AoutOE && DoutOE);
always @(posedge C16M) begin always @(posedge C16M) begin
DoutOE <= IOWE && (IOS==1 || IOS==2 || IOS==3 || DoutOE <= IOWE && (IOS==1 || IOS==2 || IOS==3 ||
IOS==4 || IOS==5 || IOS==6); IOS==4 || IOS==5 || IOS==6);

6
cpld/IOBS.v
View File

@ -4,7 +4,7 @@ module IOBS(
/* AS cycle detection */ /* AS cycle detection */
input BACT, input BACT,
/* Select and ready signals */ /* Select and ready signals */
input IOCS, input IOPWCS, output Ready, output reg BERR, input IOCS, input IOPWCS, output IOBS_Ready, output reg IOBS_BERR,
/* Read data OE control */ /* Read data OE control */
output nDinOE, output nDinOE,
/* IOB Master Controller Interface */ /* IOB Master Controller Interface */
@ -109,9 +109,9 @@ module IOBS(
BERR <= 0; BERR <= 0;
end else if (Once && (PS==0 || PS==1) && ~IOACTr && IOPWReady) begin end else if (Once && (PS==0 || PS==1) && ~IOACTr && IOPWReady) begin
IOReady <= ~IOBERR; IOReady <= ~IOBERR;
BERR <= IOBERR; IOBS_BERR <= IOBERR;
end end
end end
assign Ready = ~IOCS || IOReady || (IOPWCS && IOPWReady); assign IOBS_Ready = ~IOCS || IOReady || (IOPWCS && IOPWReady);
endmodule endmodule

20
cpld/WarpSE.v
View File

@ -80,7 +80,7 @@ module WarpSE(
RA[11:0], nRAS, nCAS, RA[11:0], nRAS, nCAS,
nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE); nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
wire Ready_IOBS, BERR_IOBS; wire IOBS_Ready, IOBS_BERR;
wire IOREQ, IOACT, IOBERR; wire IOREQ, IOACT, IOBERR;
wire ALE0S, ALE0M, ALE1; wire ALE0S, ALE0M, ALE1;
assign nADoutLE0 = ~(ALE0S || ALE0M); assign nADoutLE0 = ~(ALE0S || ALE0M);
@ -92,7 +92,7 @@ module WarpSE(
/* AS cycle detection, FSB BERR */ /* AS cycle detection, FSB BERR */
BACT, BACT,
/* Select and ready signals */ /* Select and ready signals */
IOCS, IOPWCS, Ready_IOBS, BERR_IOBS, IOCS, IOPWCS, IOBS_Ready, IOBS_BERR,
/* Read data OE control */ /* Read data OE control */
nDinOE, nDinOE,
/* IOB Master Controller Interface */ /* IOB Master Controller Interface */
@ -102,11 +102,12 @@ module WarpSE(
/* FIFO secondary level control */ /* FIFO secondary level control */
ALE1); ALE1);
wire AoutOE;
wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout; wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
assign nAS_IOB = nAoutOE ? 1'bZ : nAS_IOBout; assign nAS_IOB = AoutOE ? 1'bZ : nAS_IOBout;
assign nLDS_IOB = nAoutOE ? 1'bZ : nLDS_IOBout; assign nLDS_IOB = AoutOE ? 1'bZ : nLDS_IOBout;
assign nUDS_IOB = nAoutOE ? 1'bZ : nUDS_IOBout; assign nUDS_IOB = AoutOE ? 1'bZ : nUDS_IOBout;
assign nVMA_IOB = nAoutOE ? 1'bZ : nVMA_IOBout; assign nVMA_IOB = AoutOE ? 1'bZ : nVMA_IOBout;
IOBM iobm( IOBM iobm(
/* PDS interface */ /* PDS interface */
CLK2X_IOB, CLK_IOB, E_IOB, CLK2X_IOB, CLK_IOB, E_IOB,
@ -119,7 +120,6 @@ module WarpSE(
IOREQ, IOL0, IOU0, IORW0); IOREQ, IOL0, IOU0, IORW0);
wire BERRTimeout; wire BERRTimeout;
wire AoutOE;
CNT cnt( CNT cnt(
/* C8M clock */ /* C8M clock */
C8M, C8M,
@ -142,9 +142,9 @@ module WarpSE(
/* AS cycle detection */ /* AS cycle detection */
BACT, LBACT, BACT, LBACT,
/* Ready and IA inputs */ /* Ready and IA inputs */
Ready_RAM, Ready_IOBS, (!SndRAMCSWR || QoSReady), Ready_RAM, IOBS_Ready, (!SndRAMCSWR || QoSReady),
/* BERR inputs */ /* IOB slabe port BERR input */
(~IOCS && BERRTimeout), BERR_IOBS, IOBS_BERR,
/* Interrupt acknowledge select */ /* Interrupt acknowledge select */
IACS); IACS);

8
cpld/XC95144XL/WarpSE.cmd_log
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@ -25,3 +25,11 @@ taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_rep
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"

2
cpld/XC95144XL/WarpSE.gise
View File

@ -78,7 +78,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1662236554" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1233756204182495024" xil_pn:start_ts="1662236533"> <transform xil_pn:end_ts="1679288302" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1233756204182495024" xil_pn:start_ts="1679288299">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>

47
cpld/XC95144XL/WarpSE.syr
View File

@ -1,16 +1,16 @@
Release 14.7 - xst P.20131013 (nt) Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp --> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.97 secs Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to xst --> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.98 secs Total CPU time to Xst completion: 0.09 secs
--> Reading design: WarpSE.prj --> Reading design: WarpSE.prj
@ -76,36 +76,43 @@ wysiwyg : NO
* HDL Compilation * * HDL Compilation *
========================================================================= =========================================================================
Compiling verilog file "../RAM.v" in library work Compiling verilog file "../RAM.v" in library work
ERROR:HDLCompilers:28 - "../RAM.v" line 63 'BACTr' has not been declared ERROR:HDLCompilers:28 - "../RAM.v" line 38 'BACTr' has not been declared
ERROR:HDLCompilers:26 - "../RAM.v" line 69 unexpected token: ';' ERROR:HDLCompilers:28 - "../RAM.v" line 96 'RefFromRS0Next' has not been declared
ERROR:HDLCompilers:26 - "../RAM.v" line 75 unexpected token: 'begin' ERROR:HDLCompilers:28 - "../RAM.v" line 100 'RAMDIS1' has not been declared
ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting ';', found ')' ERROR:HDLCompilers:28 - "../RAM.v" line 101 'RefFromRS0Pre' has not been declared
ERROR:HDLCompilers:26 - "../RAM.v" line 76 unexpected token: '<=' ERROR:HDLCompilers:28 - "../RAM.v" line 107 'RAMDIS1' has not been declared
Module <RAM> compiled ERROR:HDLCompilers:28 - "../RAM.v" line 113 'RAMDIS1' has not been declared
ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting 'endmodule', found '0' ERROR:HDLCompilers:28 - "../RAM.v" line 118 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 124 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 132 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 139 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 146 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 153 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 160 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 167 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 176 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 184 'RAMDIS1' has not been declared
ERROR:HDLCompilers:28 - "../RAM.v" line 190 'RAMDIS1' has not been declared
Compiling verilog file "../IOBS.v" in library work Compiling verilog file "../IOBS.v" in library work
Module <RAM> compiled
Compiling verilog file "../IOBM.v" in library work Compiling verilog file "../IOBM.v" in library work
Module <IOBS> compiled Module <IOBS> compiled
Compiling verilog file "../FSB.v" in library work Compiling verilog file "../FSB.v" in library work
Module <IOBM> compiled Module <IOBM> compiled
ERROR:HDLCompilers:28 - "../FSB.v" line 59 'BERR' has not been declared ERROR:HDLCompilers:28 - "../FSB.v" line 71 'BERR' has not been declared
Compiling verilog file "../CS.v" in library work Compiling verilog file "../CS.v" in library work
Module <FSB> compiled Module <FSB> compiled
Compiling verilog file "../CNT.v" in library work Compiling verilog file "../CNT.v" in library work
Module <CS> compiled Module <CS> compiled
ERROR:HDLCompilers:28 - "../CNT.v" line 29 'RefREQ' has not been declared
ERROR:HDLCompilers:28 - "../CNT.v" line 30 'RefREQ' has not been declared
ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting ';', found '='
Module <CNT> compiled
ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting 'endmodule', found '0'
Compiling verilog file "../WarpSE.v" in library work Compiling verilog file "../WarpSE.v" in library work
Module <CNT> compiled
Module <WarpSE> compiled Module <WarpSE> compiled
Analysis of file <"WarpSE.prj"> failed. Analysis of file <"WarpSE.prj"> failed.
--> -->
Total memory usage is 190552 kilobytes Total memory usage is 232068 kilobytes
Number of errors : 11 ( 0 filtered) Number of errors : 18 ( 0 filtered)
Number of warnings : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)

52
cpld/XC95144XL/WarpSE_envsettings.html
View File

@ -14,32 +14,32 @@
<tr> <tr>
<td>PATHEXT</td> <td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr> </tr>
<tr> <tr>
<td>Path</td> <td>Path</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem</td> <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem</td>
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem</font></td> <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\altera\13.0sp1\modelsim_ase\win32aloem</td>
</tr> </tr>
<tr> <tr>
<td>XILINX</td> <td>XILINX</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td> <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\ISE\</font></td> <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
</tr> </tr>
<tr> <tr>
<td>XILINX_DSP</td> <td>XILINX_DSP</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE</td> <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\ISE</font></td> <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
</tr> </tr>
<tr> <tr>
<td>XILINX_EDK</td> <td>XILINX_EDK</td>
<td>C:\Xilinx\14.7\ISE_DS\EDK</td> <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\EDK</font></td> <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
</tr> </tr>
<tr> <tr>
<td>XILINX_PLANAHEAD</td> <td>XILINX_PLANAHEAD</td>
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td> <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
<td><font color=gray>C:\Xilinx\14.7\ISE_DS\PlanAhead</font></td> <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
</tr> </tr>
</TABLE> </TABLE>
<A NAME="Synthesis Property Settings"></A> <A NAME="Synthesis Property Settings"></A>
@ -186,28 +186,28 @@
<td><b>Default Value</b></td> <td><b>Default Value</b></td>
</tr> </tr>
<tr> <tr>
<td><font color=gray>-intstyle</font></td> <td>-intstyle</td>
<td><font color=gray>&nbsp;</font></td> <td>&nbsp;</td>
<td><font color=gray>ise</font></td> <td>ise</td>
<td><font color=gray>None</font></td> <td>None</td>
</tr> </tr>
<tr> <tr>
<td><font color=gray>-dd</font></td> <td>-dd</td>
<td><font color=gray>&nbsp;</font></td> <td>&nbsp;</td>
<td><font color=gray>_ngo</font></td> <td>_ngo</td>
<td><font color=gray>None</font></td> <td>None</td>
</tr> </tr>
<tr> <tr>
<td><font color=gray>-p</font></td> <td>-p</td>
<td><font color=gray>&nbsp;</font></td> <td>&nbsp;</td>
<td><font color=gray>xc95144xl-TQ100-10</font></td> <td>xc95144xl-TQ100-10</td>
<td><font color=gray>None</font></td> <td>None</td>
</tr> </tr>
<tr> <tr>
<td><font color=gray>-uc</font></td> <td>-uc</td>
<td><font color=gray>&nbsp;</font></td> <td>&nbsp;</td>
<td><font color=gray>Z:/Warp-SE/cpld/WarpSE-XC95144XL.ucf</font></td> <td>Z:/Warp-SE/cpld/WarpSE-XC95144XL.ucf</td>
<td><font color=gray>None</font></td> <td>None</td>
</tr> </tr>
</TABLE> </TABLE>
<A NAME="Operating System Information"></A> <A NAME="Operating System Information"></A>
@ -223,22 +223,22 @@
<tr> <tr>
<td>CPU Architecture/Speed</td> <td>CPU Architecture/Speed</td>
<td>QEMU Virtual CPU version 2.5+/1000 MHz</td> <td>QEMU Virtual CPU version 2.5+/1000 MHz</td>
<td><font color=gray>QEMU Virtual CPU version 2.5+/1000 MHz</font></td> <td>QEMU Virtual CPU version 2.5+/1000 MHz</td>
</tr> </tr>
<tr> <tr>
<td>Host</td> <td>Host</td>
<td>ZaneMacWin7</td> <td>ZaneMacWin7</td>
<td><font color=gray>ZaneMacWin7</font></td> <td>ZaneMacWin7</td>
</tr> </tr>
<tr> <tr>
<td>OS Name</td> <td>OS Name</td>
<td>Microsoft Windows 7 , 32-bit</td> <td>Microsoft Windows 7 , 32-bit</td>
<td><font color=gray>Microsoft Windows 7 , 32-bit</font></td> <td>Microsoft Windows 7 , 32-bit</td>
</tr> </tr>
<tr> <tr>
<td>OS Release</td> <td>OS Release</td>
<td>Service Pack 1 (build 7601)</td> <td>Service Pack 1 (build 7601)</td>
<td><font color=gray>Service Pack 1 (build 7601)</font></td> <td>Service Pack 1 (build 7601)</td>
</tr> </tr>
</TABLE> </TABLE>
</BODY> </HTML> </BODY> </HTML>

18
cpld/XC95144XL/WarpSE_summary.html
View File

@ -2,18 +2,18 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (09/03/2022 - 16:22:34)</B></TD></TR> <TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status</B></TD></TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>WarpSE.xise</TD> <TD>WarpSE.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>2 Errors</A></TD> <TD> No Errors </TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>WarpSE</TD> <TD>WarpSE</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Synthesized (Failed)</TD> <TD>Translated</TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
@ -21,7 +21,7 @@
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD> <TD>
<font color="red"; face="Arial"><b>X </b></font> <font color="red"; face="Arial"><b>X </b></font>
<A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/*.xmsgs?&DataKey=Error'>11 Errors (11 new)</A></TD> <A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/*.xmsgs?&DataKey=Error'>11 Errors (11 new)</A></TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD> <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
@ -44,7 +44,7 @@
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD> <TD>
<A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\WarpSE_envsettings.html'> <A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE_envsettings.html'>
System Settings</A> System Settings</A>
</TD> </TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
@ -66,9 +66,9 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Sep 3 16:22:35 2022</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Error'>11 Errors (11 new)</A></TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun Mar 19 19:23:24 2023</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Error'>11 Errors (11 new)</A></TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>Mon Mar 28 09:45:45 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sun Mar 19 19:23:24 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Out of Date</TD><TD>Mon Mar 28 09:46:19 2022</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>2 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sun Mar 19 19:23:24 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>2 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE> </TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@ -78,5 +78,5 @@ System Settings</A>
</TABLE> </TABLE>
<br><center><b>Date Generated:</b> 09/03/2022 - 17:36:27</center> <br><center><b>Date Generated:</b> 03/19/2023 - 20:19:43</center>
</BODY></HTML> </BODY></HTML>

20
cpld/XC95144XL/WarpSE_xst.xrpt
View File

@ -1,18 +1,18 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="14.7"> <document OS="nt64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sat Sep 03 16:22:30 2022"> <application stringID="Xst" timeStamp="Mon Mar 20 00:58:20 2023">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt;C:\Xilinx\14.7\ISE_DS\common\lib\nt;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\altera\13.0sp1\modelsim_ase\win32aloem"/> <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\Program Files (x86)\AMD APP\bin\x86_64;C:\Program Files (x86)\AMD APP\bin\x86;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\intelFPGA_lite\19.1\modelsim_ase\win32aloem;C:\altera\13.0sp1\modelsim_ase\win32aloem;C:\Users\Wolf\AppData\Local\GitHubDesktop\bin"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
@ -36,20 +36,16 @@
</row> </row>
</table> </table>
<item stringID="User_EnvOs" value="OS Information"> <item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 32-bit"/> <item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/> <item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
</item> </item>
<item stringID="User_EnvHost" value="ZaneMacWin7"/> <item stringID="User_EnvHost" value="LabWin7"/>
<table stringID="User_EnvCpu"> <table stringID="User_EnvCpu">
<column stringID="arch"/> <column stringID="arch"/>
<column stringID="speed"/> <column stringID="speed"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="arch" value="QEMU Virtual CPU version 2.5+"/> <item stringID="arch" value="AMD FX(tm)-8320 Eight-Core Processor "/>
<item stringID="speed" value="1000 MHz"/> <item stringID="speed" value="3792 MHz"/>
</row>
<row stringID="row" value="1">
<item stringID="arch" value="QEMU Virtual CPU version 2.5+"/>
<item stringID="speed" value="1000 MHz"/>
</row> </row>
</table> </table>
</section> </section>
@ -79,7 +75,7 @@
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/> <item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
</section> </section>
<section stringID="XST_ERRORS_STATISTICS"> <section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="11"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="18"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
</section> </section>

14
cpld/XC95144XL/_xmsgs/pn_parser.xmsgs
View File

@ -8,19 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/CNT.v&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/FSB.v&quot; into library work</arg>
</msg>
<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">Z:/Warp-SE/cpld/CNT.v</arg>&quot; Line <arg fmt="%d" index="2">127</arg>. <arg fmt="%s" index="3">Syntax error near &quot;&lt;=&quot;.</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/IOBM.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/RAM.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/WarpSE.v&quot; into library work</arg>
</msg> </msg>
</messages> </messages>

43
cpld/XC95144XL/_xmsgs/xst.xmsgs
View File

@ -5,37 +5,58 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="error" file="HDLCompilers" num="28" delta="new" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 63 </arg>&apos;<arg fmt="%s" index="2">BACTr</arg>&apos; has not been declared <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 38 </arg>&apos;<arg fmt="%s" index="2">BACTr</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="26" delta="new" >&quot;<arg fmt="%s" index="1">../RAM.v</arg>&quot; line <arg fmt="%d" index="2">69</arg> <arg fmt="%s" index="3">unexpected token: &apos;;&apos;</arg> <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 96 </arg>&apos;<arg fmt="%s" index="2">RefFromRS0Next</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="26" delta="new" >&quot;<arg fmt="%s" index="1">../RAM.v</arg>&quot; line <arg fmt="%d" index="2">75</arg> <arg fmt="%s" index="3">unexpected token: &apos;begin&apos;</arg> <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 100 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="26" delta="new" >&quot;<arg fmt="%s" index="1">../RAM.v</arg>&quot; line <arg fmt="%d" index="2">76</arg> <arg fmt="%s" index="3">expecting &apos;;&apos;, found &apos;)&apos;</arg> <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 101 </arg>&apos;<arg fmt="%s" index="2">RefFromRS0Pre</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="26" delta="new" >&quot;<arg fmt="%s" index="1">../RAM.v</arg>&quot; line <arg fmt="%d" index="2">76</arg> <arg fmt="%s" index="3">unexpected token: &apos;&lt;=&apos;</arg> <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 107 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="26" delta="new" >&quot;<arg fmt="%s" index="1">../RAM.v</arg>&quot; line <arg fmt="%d" index="2">76</arg> <arg fmt="%s" index="3">expecting &apos;endmodule&apos;, found &apos;0&apos;</arg> <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 113 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="28" delta="new" ><arg fmt="%s" index="1">&quot;../FSB.v&quot; line 59 </arg>&apos;<arg fmt="%s" index="2">BERR</arg>&apos; has not been declared <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 118 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="28" delta="new" ><arg fmt="%s" index="1">&quot;../CNT.v&quot; line 29 </arg>&apos;<arg fmt="%s" index="2">RefREQ</arg>&apos; has not been declared <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 124 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="28" delta="new" ><arg fmt="%s" index="1">&quot;../CNT.v&quot; line 30 </arg>&apos;<arg fmt="%s" index="2">RefREQ</arg>&apos; has not been declared <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 132 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="26" delta="new" >&quot;<arg fmt="%s" index="1">../CNT.v</arg>&quot; line <arg fmt="%d" index="2">34</arg> <arg fmt="%s" index="3">expecting &apos;;&apos;, found &apos;=&apos;</arg> <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 139 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg> </msg>
<msg type="error" file="HDLCompilers" num="26" delta="new" >&quot;<arg fmt="%s" index="1">../CNT.v</arg>&quot; line <arg fmt="%d" index="2">34</arg> <arg fmt="%s" index="3">expecting &apos;endmodule&apos;, found &apos;0&apos;</arg> <msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 146 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg>
<msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 153 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg>
<msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 160 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg>
<msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 167 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg>
<msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 176 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg>
<msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 184 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg>
<msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../RAM.v&quot; line 190 </arg>&apos;<arg fmt="%s" index="2">RAMDIS1</arg>&apos; has not been declared
</msg>
<msg type="error" file="HDLCompilers" num="28" delta="old" ><arg fmt="%s" index="1">&quot;../FSB.v&quot; line 71 </arg>&apos;<arg fmt="%s" index="2">BERR</arg>&apos; has not been declared
</msg> </msg>
</messages> </messages>

10
cpld/XC95144XL/iseconfig/WarpSE.projectmgr
View File

@ -10,13 +10,13 @@
<ClosedNode>/MXSE Z:|Warp-SE|cpld|WarpSE.v</ClosedNode> <ClosedNode>/MXSE Z:|Warp-SE|cpld|WarpSE.v</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>WarpSE (Z:/Warp-SE/cpld/WarpSE.v)</SelectedItem> <SelectedItem>iobm - IOBM (C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/IOBM.v)</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000d2000000020000000000000000000000000200000064ffffffff000000810000000300000002000000d20000000100000003000000000000000100000003</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000d2000000020000000000000000000000000200000064ffffffff000000810000000300000002000000d20000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>WarpSE (Z:/Warp-SE/cpld/WarpSE.v)</CurrentItem> <CurrentItem>iobm - IOBM (C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/IOBM.v)</CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes> <ClosedNodes>
@ -29,7 +29,7 @@
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000012b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012b0000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem> <CurrentItem></CurrentItem>
</ItemView> </ItemView>
@ -40,7 +40,7 @@
<SelectedItems/> <SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000002b3000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004900000001000000000000009d0000000100000000000000660000000100000000000001670000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004900000001000000000000009d0000000100000000000000660000000100000000000002570000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>CNT.v</CurrentItem> <CurrentItem>CNT.v</CurrentItem>
</ItemView> </ItemView>
@ -52,7 +52,7 @@
<SelectedItems/> <SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000010001000100000000000000000000000064ffffffff000000810000000000000001000003a30000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem> <CurrentItem>work</CurrentItem>
</ItemView> </ItemView>

6
cpld/XC95144XL/iseconfig/WarpSE.xreport
View File

@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2022-09-03T14:17:57</DateModified> <DateModified>2023-03-19T20:19:43</DateModified>
<ModuleName>WarpSE</ModuleName> <ModuleName>WarpSE</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp> <SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>Z:/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath> <SavedFilePath>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
<ImplementationReportsDirectory>Z:/Warp-SE/cpld/XC95144XL\</ImplementationReportsDirectory> <ImplementationReportsDirectory>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\</ImplementationReportsDirectory>
<DateInitialized>2022-03-28T09:29:43</DateInitialized> <DateInitialized>2022-03-28T09:29:43</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering> <EnableMessageFiltering>false</EnableMessageFiltering>
</header> </header>

4
cpld/XC95144XL/webtalk_pn.xml
View File

@ -3,11 +3,11 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Sep 03 16:22:17 2022"> <application name="pn" timeStamp="Mon Mar 20 00:58:19 2023">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="8B3C87EB1A1F4FD6BCA39339C89EC1EE" type="project"/> <property name="ProjectID" value="8B3C87EB1A1F4FD6BCA39339C89EC1EE" type="project"/>
<property name="ProjectIteration" value="0" type="project"/> <property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="Z:/Warp-SE/cpld/XC95144XL/WarpSE.xise" type="project"/> <property name="ProjectFile" value="C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2022-03-28T09:14:07" type="project"/> <property name="ProjectCreationTimestamp" value="2022-03-28T09:14:07" type="project"/>
</section> </section>
<section name="Project Statistics" visible="true"> <section name="Project Statistics" visible="true">