Commit Graph

252 Commits

Author SHA1 Message Date
Maxim Poliakovski
7bc4b8840a scsi_bus: fix device selection bug. 2022-11-02 23:21:46 +01:00
Maxim Poliakovski
5a59b97257 Sc53C94: implement cycle completion commands. 2022-11-02 22:28:43 +01:00
Maxim Poliakovski
5a33fba75e ScsiDevice: command completion states. 2022-11-02 21:28:30 +01:00
Maxim Poliakovski
0c74ebbc45 scsi_bus: support status and message in. 2022-11-02 21:27:18 +01:00
Maxim Poliakovski
2865a611e7 Sc53C94: implement reading the FIFO register. 2022-11-02 21:19:31 +01:00
Maxim Poliakovski
f2be286515 scsi_bus: fix asserting control lines. 2022-11-01 02:52:30 +01:00
Maxim Poliakovski
2c3a5c3b8f Sc53C94: reading current transfer count. 2022-11-01 02:12:09 +01:00
Maxim Poliakovski
c54c1cdb65 Sc53C94: improve status register. 2022-11-01 02:11:06 +01:00
Maxim Poliakovski
8abefb8f8d machinepdm: properly insert SCSI hard disk image.
Skip SCSI hard disk registration if no disk image was given.
2022-11-01 01:17:50 +01:00
Maxim Poliakovski
6ffe28a8a4 Implement SCSI Pseudo-DMA register on PDM. 2022-11-01 01:17:50 +01:00
Maxim Poliakovski
7ab44886c4 Sc53C94: implement information transfer command. 2022-11-01 01:17:50 +01:00
Maxim Poliakovski
fbfae98d6d scsi_bus: packet data transfers. 2022-10-31 23:21:35 +01:00
Maxim Poliakovski
c7ceb9d6b9 sc53c94: fix setting internal transfer counter. 2022-10-31 23:21:35 +01:00
Maxim Poliakovski
c28fd138c2 nvram: fix initialization bug. 2022-10-31 01:01:46 +01:00
dingusdev
b480903c7a Slight code clean-up
Prevents crashing
2022-10-30 15:38:09 -07:00
Maxim Poliakovski
46a0e82258 scsi_hd: some fixes and improvements. 2022-10-27 14:19:58 +02:00
Maxim Poliakovski
a58c9b1a62 ScsiDevice: fix process_command() signature. 2022-10-27 14:07:20 +02:00
Maxim Poliakovski
f3cd5b8b36 sc53c94: fix sending commands to SCSI devices. 2022-10-27 13:49:41 +02:00
dingusdev
2065f3588b Inquiry cmd fixed 2022-10-26 09:30:05 -07:00
dingusdev
f792b38ea3 Started SCSI command reading 2022-10-26 09:18:32 -07:00
Maxim Poliakovski
4f6bd16f3a sc53c94: support selection and command transfer. 2022-10-25 03:03:15 +02:00
Maxim Poliakovski
c51ea575ca scsi_bus: various fixes and improvements. 2022-10-25 03:03:15 +02:00
Maxim Poliakovski
9efac80271 scsi_hd: fix notify() method. 2022-10-25 03:03:15 +02:00
Maxim Poliakovski
eeb576a927 Improve ScsiDevice class. 2022-10-25 02:53:21 +02:00
dingusdev
3af9729e5b Modest refactoring for SCSI HDs 2022-10-23 16:45:58 -07:00
joevt
9f1d613a2d Fix PCI struct offset size
The Pointer to PCI Data Structure is supposed to be two bytes. It is described in the PCI Firmware Specification Revision 3.0, section 5.1.1. PCI Expansion ROM Header Format.
The pointer is two bytes at 0x18. The pointer is supposed to be a multiple of 4 which means there's always at least two bytes of padding after the pointer. Some BIOS firmware images may use the 2 bytes following the pointer for other purposes (plus additional bytes before the PCI Data Structure) so we cannot assume the bytes will be zero.
Some PCI expansion ROMs may include both BIOS and Open Firmware images.
2022-10-23 00:26:32 -07:00
Maxim Poliakovski
c2abc89a3b Fix SCSI HD interface so it can be added to a bus. 2022-10-22 23:41:19 +02:00
dingusdev
aa1d23e08b Fixed hard disk support
Compiles, still unfinished
2022-10-22 11:41:52 -07:00
dingusdev
ee9573327c Reorganized hard disk code
Not compiling yet.
2022-10-08 16:51:54 -07:00
Maxim Poliakovski
3a5c61797c
Revert "PCI fixes" 2022-09-02 23:24:06 +00:00
joevt
b654424465 Fix PCI config r/w of byte and word and unaligned
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.

- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the pci_cfg_read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.

- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.

Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.

The PCI controllers (bandit, chaos, mpc106) need to encode the offset (0,1,2,3) into the reg_offs parameter passed to pci_cfg_read and pci_cfg_write so they can return or modify the correct bytes of the dword at reg_offs & 3.

The pci_cfg_read and pci_cfg_write methods extract the offset from reg_offs and report unaligned accesses.

pci_cfg_read uses pci_cfg_rev_read to read from the reg using the size and offset to determine which bytes to read.

pci_cfg_write uses pci_cfg_rev_write to write to the reg using the size and offset to determine which bytes to modify.

Other changes:
- for unimplemented config register reads and writes, bandit and ATIRage now includes offset and size (and value in the case of writes) in log warnings.
- for unimplemented config register reads and writes, pcidevice now includes offset in log warnings.
- pci_read and pci_write of mpc106 require an offset parameter since config_addr does not contain the offset (it is always a multiple of 4). The offset is included in the log warninings for non-existent PCI devices.
- ATIRage uses pci_cfg_rev_read and pci_cfg_rev_write which correctly places user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.

Notes:
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.
2022-09-02 03:39:50 -07:00
joevt
d91e14abc6 Log PCI config write values MSB first
Writes to config registers of invalid or non-existent PCI devices are logged. They should be logged with most significant byte first.
The values enter the methods in reverse byte order so they need to be byte swapped (except when size is 1) for logging.
The result is that this command in Open Firmware:
`12345678 16800 config-l!`
will log this:
`VCI0 err: write attempt to non-existing VCI device ??:0d.0 @00.l = 12345678`
2022-09-02 03:39:50 -07:00
joevt
a24840803c Allow bit 1 of I/O BARs to be set
Usually bit 1 of I/O BARs is 0 since it is reserved, but control has an I/O BAR where this bit is set.
bar_cfg is used to determine the default values of the least significant bits (2 bits for I/O BARs and 4 bits for Memory BARs).
The upper bits of bar_cfg determine which bits can be set and also determines the size of the BAR.
2022-09-02 03:39:50 -07:00
joevt
7e7522d4b7 Fix Expansion ROM BAR writes
The bits that can be set are the enable bit (bit 0) plus the bits represented by exp_bar_cfg which is determined by the size of the ROM which is calculated to be a power of 2 and a minimum of 2K.
2022-09-02 03:39:50 -07:00
dingusdev
a61dd5701a Initial prototyping for hard disks 2022-09-01 22:10:52 -07:00
Maxim Poliakovski
5b08f283e5 Hacks for debugging HW interrupts. 2022-08-27 17:38:53 +02:00
joevt
e41b196977 Fix return value for bad pci config address
PCI config read fails should return all 1 bits.
All unused registers in an existing PCI device should return 0.

Because that's what my Power Mac 8600 returns when I run my Open Firmware lspci command.
Any bus/device/function that doesn't exist returns FF and won't be listed by lspci.
Any registers that are unused will show as 00 in the lspci output.

Make grackle log bus:device.function @register.size in all cases.
2022-08-24 07:58:12 -07:00
Maxim Poliakovski
994f8d7155 viacuda: fix interrupts. 2022-08-24 14:15:48 +02:00
joevt
1ccc8d1a25 Fix setenv and printenv
- Allow changing integer variables. Previously they could not be changed.
- Allow changing string variables. Previously they could only be changed if their length increased.
- printenv had a bug with strings longer than 32 characters.
- printenv now translates carriage return (used in nvramrc) as endl (which should perform carriage return and linefeed)
- For integers, setenv assumes decimal number input but if that fails it will try hex conversion. 0x prefix for hex numbers is optional unless the number only has digits 0 - 9.
- setenv converts linefeed to carriage return for string variables. nvramrc requires this for proper editing in Open Firmware.
- Added Open Firmware 2.4 nvram field names to OfNvramHdr comments.
2022-08-22 17:20:04 -07:00
joevt
3ee2ea1871 Fix read/write argument names
base class uses reg_start so derived classes should do the same.
Some derived class already uses reg_start for read method.
2022-08-22 17:16:22 -07:00
joevt
3b4f40635a Register offsets should be logged as hex
- decimal values are confusing (can't tell if 12 means 12 or 18)
- most specs show hex values for register offsets.
2022-08-22 17:16:22 -07:00
joevt
c644d1609f PCI Expansion ROM size should be power of 2
The expansion rom base register indicates the size of the expansion rom by the number of bits that remain zero after code attempts to set them all to 1. For example, a result of fffe0000 means 128K. The 11 least significant bits are ignored in the size calculation, which means the minimum rom size is indicated by fffff800 = 2K.

Handle the case where an expansion rom file might not have a size that is a multiple of 2 or is not greater than 2K.
Bytes between the end of the file and the end of the calculated rom size are set to 0xff.
2022-08-22 17:16:22 -07:00
joevt
d843091a4d Allow setting PCI capabilities pointer
The capabilities pointer is usually a constant, but whatever the capabilities pointer points to has to be handled by the derived class.
2022-08-22 17:16:22 -07:00
joevt
6fad095730 Allow setting PCI status register
Don't always return 0 when reading it. The status register contains some bits that Open Firmware uses to set some properties.
A PCI device can set a default status register value to set those bits.
	this->status = 0x02B0; // 0000  0 01 0  1 0 1 1  0000 Capabilities List, 66 MHz, Fast Back-to-Back, DevSel Speed: Medium
2022-08-22 17:16:22 -07:00
joevt
6af8b52376 changes to pci logging
For invalid or unsupported PCI accesses, do the following:
- log a device's full pci address using pciutils setpci command format bb:dd.f @rr.s (bus:device:function @register+offset.size).
- report as read or write access.
- log value for writes.
- bus, device, function, and register values cannot be determined from Invalid IDSEL values so they will output as ??.
- for invalid IDSEL values, report the entire value of the config_addr.
- for valid IDSEL values, the bus number cannot be determined since IDSEL only specifies device number. It's probably bus 00 but we'll show ?? to indicate an IDSEL type access.

Add missing config type read access logging for chaos.
2022-08-22 17:16:17 -07:00
joevt
63248b0fa2 Set Bandit's HWComponent name
Bandit has two names:
- PCIDevice->pci_name
- PCIDevice:MMIODevice:HWComponent->name
The latter was not being set.
2022-08-22 17:07:50 -07:00
joevt
cd122ce263 Open Firmware is two words
Not OpenFirmware.
Also fixed a spelling mistake and removed some extra spaces.
2022-08-22 16:47:38 -07:00
Maxim Poliakovski
e097b7a0a1 bandit: fix return value for empty slots. 2022-08-22 15:05:35 +02:00
Maxim Poliakovski
32b8c8ed43 pcidevice: fix expansion ROM mapping. 2022-08-20 12:51:08 +02:00
Maxim Poliakovski
56c54e4c8c pcihost: add attach_pci_device method. 2022-08-19 18:55:33 +02:00
Maxim Poliakovski
4964008511 machineid: improve Gossamer ID description. 2022-08-15 20:49:06 +02:00
joevt
93fae1ee68 Merge remote-tracking branch 'upstream/master' 2022-08-14 16:38:51 -07:00
Maxim Poliakovski
8cdbd9f81f Generic I2C PROM emulation. 2022-08-14 23:01:55 +02:00
joevt
b76bfedf4b Remove unnecessary linefeeds from log
To remove blank lines in the dingusppc.log file or in the console output when -d is used.
2022-08-14 05:26:56 -07:00
Maxim Poliakovski
b67644ba35 athens: support ID reading & dot clock disabling. 2022-08-11 01:43:29 +02:00
Maxim Poliakovski
5463c8e6cb athens: fix compilation with GCC. 2022-08-07 15:32:05 +02:00
Maxim Poliakovski
bd19914132 Initial emulation of the Athens clock ASIC. 2022-08-07 15:25:58 +02:00
Maxim Poliakovski
e3900b9062 bandit: add Chaos support. 2022-08-06 19:29:45 +02:00
Maxim Poliakovski
ea0fb3b410 bandit: initialize address mask register. 2022-07-25 12:51:55 +02:00
Maxim Poliakovski
b8915f11a2 debugger: fix ofnvram commands for Nubus machines. 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
9971052a78 mesh: self-registration with the device registry. 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
7db0a31cc5 nvram: self-registration with the device registry. 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
41a314d6d6 bandit: self-registration with the device registry. 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
2dfc160e30 sc53c94: self-registration with the device registry. 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
66debbc730 viacuda: self-registration with the device registry. 2022-07-18 20:27:34 +02:00
Maxim Poliakovski
06001a778f GCC compilation fixes. 2022-05-21 15:10:40 +02:00
Maxim Poliakovski
ed02a06bb8 pcidevice: loading of expansion ROMs from files. 2022-05-21 14:51:27 +02:00
Maxim Poliakovski
5b7e79b979 Bandit: implement I/O space transactions. 2022-05-21 14:51:27 +02:00
Maxim Poliakovski
bfd48eeeb2 Bandit: implement address mask register. 2022-05-21 14:51:27 +02:00
Maxim Poliakovski
4225f0aec2 ofnvram: implement changing of string variables. 2022-05-21 14:51:27 +02:00
Maxim Poliakovski
a7e06f4e4b Utility class for viewing/changing OF NVRAM variables. 2022-05-21 14:51:27 +02:00
Maxim Poliakovski
4b2f3cedc7 Make NVRAM a full-fledged HW component. 2022-05-21 14:51:27 +02:00
Maxim Poliakovski
d863fa0c80 Bandit: use common PCI configuration code. 2022-05-21 14:51:27 +02:00
Maxim Poliakovski
1f67a57d7b Common code for handling PCI config space. 2022-05-21 14:51:26 +02:00
Maxim Poliakovski
8d9691cc6f MESH: add MeshScsi namespace. 2022-05-21 14:51:26 +02:00
Maxim Poliakovski
4b32e9bd30 Initial emulation of the Platinum Memory controller. 2022-05-21 14:51:26 +02:00
Maxim Poliakovski
23a046d889 Refine Bandit config address handling. 2022-05-21 14:51:26 +02:00
Maxim Poliakovski
cdb34032bc Initial emulation of the Bandit ARBus-to-PCI bridge. 2022-05-21 14:51:26 +02:00
Maxim Poliakovski
74f4dbd7e6 pcihost: pull common code from Grackle. 2022-05-21 14:51:26 +02:00
dingusdev
36fa53e8c1 MSVC compilation fixes 2022-03-12 15:43:45 -07:00
Maxim Poliakovski
edd3979647 Cuda: increase size of the input buffer. 2022-02-19 23:23:24 +01:00
Maxim Poliakovski
2525398b6e SWIM3: add support for floppy DMA. 2022-02-15 15:53:18 +01:00
Maxim Poliakovski
0d3fd01fef Improve emulation of the VIA timers. 2022-02-13 03:02:17 +01:00
Maxim Poliakovski
9f3f46603f AMIC: handle SWIM3 interrupts. 2022-02-07 23:10:17 +01:00
Maxim Poliakovski
b25b526582 hwcomponent: add floppy disk drive component type. 2022-02-06 15:20:07 +01:00
Maxim Poliakovski
00093bdc95 sc53c94: support interrupts. 2022-02-06 01:50:54 +01:00
Maxim Poliakovski
298135fd7a AMIC: process VIA2 interrupts. 2022-02-06 01:50:54 +01:00
Maxim Poliakovski
7c53620a40 sc53c94: implement sequencer and some commands. 2022-02-06 01:50:54 +01:00
Maxim Poliakovski
b5f70feb28 Initial SCSI bus emulation. 2022-02-06 01:50:54 +01:00
Maxim Poliakovski
5c177cc50f Simplify registration of HW component types. 2022-01-26 16:45:21 +01:00
Maxim Poliakovski
dc34f282b7 53C94: support more registers and commands. 2022-01-24 22:55:49 +01:00
Maxim Poliakovski
5883524fb8 53C94: chip initialization and identification. 2022-01-22 04:37:52 +01:00
Maxim Poliakovski
0899186ffc ViaCuda: implement post-initialization. 2022-01-21 12:42:05 +01:00
Maxim Poliakovski
c1208b398e Add posti-initialization to HW components. 2022-01-21 12:42:05 +01:00
Maxim Poliakovski
4867a68e11 VIA: public method for asserting control lines. 2022-01-21 11:08:32 +01:00
Maxim Poliakovski
9c4e6c8a86 Rewrite ViaCuda to support SR and T2 interrupts. 2022-01-10 17:56:24 +01:00
Maxim Poliakovski
c218badd5a Clean up some ctors/dtors. 2022-01-10 17:56:24 +01:00
Maxim Poliakovski
d9d8384d4a Add interrupt controller interface and definitions. 2022-01-10 17:56:24 +01:00
dingusdev
84ded9fc7a Added further CUDA commands 2021-11-10 07:56:50 -07:00
Maxim Poliakovski
392fa87ba4 Add NCR 53C90 stub. 2021-10-26 19:00:04 +02:00
Maxim Poliakovski
c0cd6eb38f Add missing licence headers, update license date. 2021-10-23 21:00:31 +02:00
Maxim Poliakovski
9329d56d83 Move devices into dedicated subdirectories. 2021-10-23 20:17:47 +02:00