gbeauche
e0a76f9e38
Don't handle XLM_IRQ_NEST atomically in emulated mode. That's useless since
...
this variable is modified only within a single thread and interrupts are
not handled asynchronously.
2004-06-22 17:10:08 +00:00
gbeauche
1988a45a16
More realistic "mftb" implementation, aka. fix AbsoluteToNanoseconds() and
...
generally speaking UpTime()-based stopwatchers.
2004-06-22 15:48:50 +00:00
gbeauche
070ac7079f
Always handle interrupt even if InterruptFlags == 0, though it should not
...
really happen in practise.
2004-06-22 14:18:35 +00:00
gbeauche
72b26d7ff7
Stop forced compilation when entering a new JIT execution level.
2004-06-15 21:27:46 +00:00
gbeauche
aeab320c3f
Speed up testsuite with JIT compilers. Fix exit code.
2004-06-15 21:02:24 +00:00
gbeauche
f574a5df05
Cleanups. Rewrite gen_bc() so that no push/pop could be inserted thus
...
causing crahes with some compilers. However, that's slower.
2004-06-09 16:36:44 +00:00
gbeauche
301d3a3192
STATS: Account for all interrupts, but still count native interrupts. It
...
turns out that for a regular bootup sequence to the Finder, less than 30%
interrupts triggered were in native mode.
Default EMUL_TIME_STATS to 0, end user probably doesn't want garbage to
be printed to his console.
2004-06-05 07:09:38 +00:00
gbeauche
389dd61d0d
Check for SIGSEGVs from DR Cache code too.
2004-05-31 10:08:31 +00:00
gbeauche
619aa9b319
Translate LMW, STMW and DCBZ instructions.
2004-05-23 16:34:38 +00:00
gbeauche
b0aae35951
Do FOLLOW_CONST_JUMPS for bcl 20,BI,TARGET branches too, since that's an
...
unconditional jump and we don't need the LR in that case.
Also fix this:
SheepShaver: ../kpx_cpu/src/cpu/ppc/ppc-translate.cpp:1499: powerpc_block_info* powerpc_cpu::compile_block(unsigned int): Assertion `dg.jmp_addr[i] != __null' failed.
Aborted
aka. StuffIt Expander + pressing the 'Cancel' button.
2004-05-23 06:41:25 +00:00
gbeauche
05bd5f40b4
Fix NativeOp code generation, especially in PPC_REENTRANT_JIT mode
2004-05-23 05:28:12 +00:00
gbeauche
f376933138
Attempt to fix direct block chaining code in corner cases. e.g. really
...
chain only blocks within page boundaries (compare against block entry point)
2004-05-22 17:57:36 +00:00
gbeauche
3a033cf79b
atomic spcflags
2004-05-20 17:19:59 +00:00
gbeauche
bd6eaf680a
Get rid of old (and broken) ASYNC_IRQ / MUTICORE code
2004-05-20 12:33:58 +00:00
gbeauche
3a960764ea
Don't allow "recursive" NanoKernel interrupts
2004-05-20 11:47:27 +00:00
gbeauche
ec6c98035b
Better interrupt context checking code
2004-05-20 11:05:30 +00:00
gbeauche
c3f2342f47
Make NativeOp() handler a sheepshaver_cpu handler, thus getting rid of ugly
...
GPR macro definition.
Make the JIT engine somewhat reentrant. This brings a massive performance
boost for applications that cause many Execute68k(). e.g. audio in PlayerPRO.
2004-05-19 21:23:17 +00:00
gbeauche
ae0e7293dd
Don't take an EMUL_OP mode switch for Microseconds() and SynchIdleTime()
2004-05-15 17:26:28 +00:00
gbeauche
7da40bee5c
Handle SAFE_INTERRUPT_PPC to check possible nested calls (and this happens)
2004-05-12 15:54:23 +00:00
gbeauche
05fad61b21
Direct block chaining works on all supported platforms
2004-05-12 11:36:39 +00:00
gbeauche
81ae2fee40
Direct block chaining on x86 and amd64 too. Optimize do_execute_branch_bo<>
...
No need to update Program Counter if we have direct linked blocks.
TODO: remove obsolete PC-related generators
2004-05-12 10:44:04 +00:00
gbeauche
15a0779328
Size optimization: don't generate jump_next_A0() code in block chaining
...
mode since the only case we would reach that is when there are pending
interrupts, thus needing to exit from this basic block ASAP. Otherwise,
we jumped to linker trampolines
2004-05-11 21:53:48 +00:00
gbeauche
08bcd2653d
direct block chaining, aka faster block dispatcher
2004-05-11 20:53:25 +00:00
gbeauche
5164fc9dfc
parentesisation
2004-05-07 14:19:50 +00:00
gbeauche
2eda71a795
build fixes for x86 and some older compilers
2004-05-07 13:27:26 +00:00
gbeauche
ba7bfc478e
Extend NativeOp count to 64 (6-bit value), aka fix NATIVE_FILLRECT opcpdes.
...
Translate NQD_{bitblt,fillrect,invrect} to direct native calls.
Use Mac2HostAddr() for converting Mac base address to native.
2004-04-22 22:54:47 +00:00
gbeauche
8b40a7e721
NQD: use ReadMacInt*() and WriteMacInt*() accessors, i.e. code should now
...
be little-endian and 64-bit safe.
2004-04-22 21:45:18 +00:00
gbeauche
b4ac3fb507
Basic fillrect/invrect NQD. Code may need to be factored out somehow.
...
Verify that bitblt NQD transfer modes are really CopyBits() ones [MB5].
2004-04-22 20:57:31 +00:00
gbeauche
a65a6c6db2
Start Native QuickDraw acceleration
2004-04-18 23:03:53 +00:00
gbeauche
47348e8120
16-byte aligned memory allocator will try the following functions in-order
...
(determined at compile-time): posix_memalign, memalign, valloc, malloc.
2004-02-24 14:09:12 +00:00
gbeauche
ae93ea2f16
Make SheepShaver work with OS 8.6 out-of-the-box with no extra patch for
...
the time being. i.e. ignore writes to the zero page when faking SCSIGlobals
2004-02-24 11:12:54 +00:00
gbeauche
643f9ad5e5
fix auto-detection of SSE headers on x86
2004-02-24 10:21:21 +00:00
gbeauche
b802615c36
Don't include SSE/MMX intrinsics headers if they are not available
2004-02-20 17:33:28 +00:00
gbeauche
cdab3d6975
we have to 16-byte align sheepshaver_cpu object has it contains SSE values
...
that require this alignment.
2004-02-20 17:20:15 +00:00
gbeauche
443231c1da
First round of SSE/MMX optimizations & experimentations. AltiVec Fractal
...
Carbon performance increased by a factor 8 (420 MegaFlops).
2004-02-20 17:18:44 +00:00
gbeauche
2b1f76f343
handle .rodata.cst4, generate HAVE_gen_op_XXX for compile-time detection of
...
synthetic instruction generators available.
2004-02-20 17:16:55 +00:00
gbeauche
ea3c6801ab
Experiment with generic AltiVec optimizations for V4SF, V2DI operands (+60%)
2004-02-16 23:17:27 +00:00
gbeauche
0c421f0be8
Filter out specific symbols first prior to triggering the general case with
...
C++ symbol demangling.
2004-02-16 15:36:34 +00:00
gbeauche
7a7abb30b4
GCC 3.4 fixes
2004-02-16 15:35:37 +00:00
gbeauche
18893e22bd
GCC 3.4 does not allow the lazy_allocator instantiation, the other form is
...
not supported by any GCC but ICC accepts it.
2004-02-16 15:34:55 +00:00
gbeauche
d10a3586f1
Year got increased "recently". ;-)
2004-02-16 10:57:07 +00:00
gbeauche
313cddeeb2
AltiVec emulation! ;-)
2004-02-15 17:17:37 +00:00
gbeauche
d92989dc53
Add AltiVec regression testsuite
2004-02-15 17:16:57 +00:00
gbeauche
74cf5d2686
add barrier to inlined block dispatcher
2004-01-29 21:36:31 +00:00
gbeauche
c9edbd29ee
Handle .rodata.cst16 on AMD64 for FP constants.
2004-01-27 17:02:13 +00:00
gbeauche
8afa65cc96
Inline fast basic block lookups. Only check top tag as it is a hit more than
...
95% of the time. Overall, this improves performance by more than 2x on a P4.
2004-01-27 13:54:51 +00:00
gbeauche
6a214d48b0
Faster double load/store on ia32
2004-01-26 13:51:01 +00:00
gbeauche
ea9553ee65
Optimize rlwinm further. Translate FP instructions if we don't need to
...
compute exceptions.
2004-01-25 23:21:06 +00:00
gbeauche
9c6b42b014
Optimize gen_mov_32_REG_im(0) case
2004-01-24 17:50:32 +00:00
gbeauche
82808234fa
Merge in FP exceptions support but disable it for now as it is incomplete
...
and slower. Implement mcrfs. Fix and optimize fctiw with native rounding.
2004-01-24 16:43:45 +00:00
gbeauche
3de5a15902
Don't define disasm_block() in non-JIT mode. Also make sure to disassemble
...
native code if we can (i.e. TARGET_NATIVE disassembler exists).
2004-01-24 11:52:54 +00:00
gbeauche
10b9ab2c34
Generate PowerPC code wrapping GetResource() replacements. That way, it's
...
a normal PPC function invocation that can be JIT compiled to native code
instead of nesting execute() calls which may lead to use the interpreter
(this took around 11% of total execution time on boot, downto 3%).
Also, optimize some SheepShaver EmulOps and actually report non-CTI.
2004-01-24 11:28:06 +00:00
gbeauche
60d371486b
Propagate done_compile down to compile1() in case it needs to override
...
the end-of-block condition (e.g. sheep EmulOps)
2004-01-24 11:22:48 +00:00
gbeauche
48d844a40a
Add gen_spcflags_{init,set,clear} + load/store of GPRs to T2.
2004-01-24 11:20:33 +00:00
gbeauche
6a4463b8fb
We need at least for native registers, hence we are guaranteed to have
...
REG_T2 available. Add 16/32 sign-extension in T1. Add call generators
with (T0, T1) and (T0, T1, T2) arguments.
2004-01-24 11:18:29 +00:00
gbeauche
09cd7ccfd6
gcc on darwin defines __ppc__, not __powerpc__
2004-01-14 23:16:37 +00:00
gbeauche
07f0be19b5
Fix FP single operations. aka fix scrollbar & Graphing Calculator bugs.
2004-01-13 23:50:09 +00:00
cebix
2d5de1af9d
Happy New Year! :)
2004-01-12 15:37:24 +00:00
gbeauche
9e1d1606ff
Cosmetic fixes to vm_write_memory_*() functions.
2003-12-26 17:27:47 +00:00
gbeauche
97ce4fdc75
Match Linux/ppc native version better: jump to ROM with EmulatorData in r4,
...
preserve CR & XER registers on EmulOp.
2003-12-25 23:54:36 +00:00
gbeauche
561046449a
Fix no JIT & no decode cache case to default to interpretive mode only.
2003-12-25 23:33:15 +00:00
gbeauche
bbde2a2054
Use an alternate stack base while servicing PowerPC interrupts.
2003-12-05 13:37:56 +00:00
gbeauche
4755f118df
Revert 32-bit EA load/stores workaround, problem was 0xffffffff read from
...
[PgChk]+4 which yields to 3 on 32-bit arches and something > 32-bit on AMD64
2003-12-05 12:38:44 +00:00
gbeauche
091a219280
Use a unique ExecuteNative() interface in any case, i.e. native & emulated
2003-12-04 23:37:38 +00:00
gbeauche
158f63d1e3
Force 32-bit EA in load/store operations. This fixes SheepShaver/JIT on AMD64.
2003-12-04 18:10:36 +00:00
gbeauche
5dca41d253
Add gen_invoke_CPU_im_im() to invoke do_record_step(pc, opcode).
2003-12-04 17:53:04 +00:00
gbeauche
328bb9f239
Add new thunking system for 64-bit fixes.
2003-12-04 17:26:38 +00:00
gbeauche
490fa2d553
Add x86 asm opts (though disabled for now)
2003-12-03 11:45:45 +00:00
gbeauche
5b0569944f
Don't enable asm opts for now, this hides measurability of other generic
...
optimizations. Remove no longer used synthetic instructions.
2003-12-03 11:45:13 +00:00
gbeauche
0c2735dbcc
fix stats reports
2003-12-03 10:59:43 +00:00
gbeauche
7ebe0347bf
Add "jit" prefs item. Fix PPC_DECODE_CACHE version to fill in new min_pc &
...
max_pc members of block info. Increase -finline-limit to 10000 for older gcc
2003-12-03 10:52:50 +00:00
gbeauche
34f90d6b3a
PowerPC tester: open results file in binary mode, aka fix pb on DOS.
2003-12-03 09:16:46 +00:00
gbeauche
8db8d10287
fix extraction of XER from QEMU engine
2003-12-03 07:27:05 +00:00
gbeauche
04214f3820
Fix decrement the CTR, then branch conditional if decremented CTR != 0.
...
Remove CR cache for now. Remove BC & MODE_68K hacks for SheepShaver,
that was a colateral damage of wrong branch emulation of the former.
2003-12-02 22:49:18 +00:00
gbeauche
dc79320904
cleanups
2003-12-02 15:00:40 +00:00
gbeauche
3ca595a337
PowerPC tester: add support for QEMU engine.
2003-12-02 14:57:07 +00:00
gbeauche
07c8e505c9
PowerPC tester: add support for Bart's Model 3 CPU emulator
2003-12-02 11:29:46 +00:00
gbeauche
e2ca6270f8
Implement ISYNC, MTCRF, MCRF.
2003-12-01 13:40:38 +00:00
gbeauche
054748532a
NOP'ize unimplemented instructions
2003-12-01 13:21:41 +00:00
gbeauche
dd956c78db
gather some stats on untranslated instructions
2003-12-01 13:07:26 +00:00
gbeauche
32f34c07c5
fix stack allocation, really roundup to next 16 KB boundaries
2003-12-01 11:02:13 +00:00
gbeauche
f034ae704f
handle ROM areas and put associated blocks into dormant state
2003-12-01 00:16:21 +00:00
gbeauche
ceb9b4a428
cleanups & optimize for constant branches (i.e. follow them).
2003-12-01 00:03:02 +00:00
gbeauche
4a3cd024ed
better handling of static translation cache allocation, handle nested
...
execution paths from the cpu core, cleanups for KPX_MAX_CPUS == 1.
2003-11-30 17:21:53 +00:00
gbeauche
c1dba58808
fix & reenable asm compare ops for ppc
2003-11-30 17:18:17 +00:00
gbeauche
10db506aa5
handle CR cache though it's not efficient with current approach without
...
superblock (traces) optimization.
2003-11-30 17:17:32 +00:00
gbeauche
7594e26d36
fix new block creation on full cache that was just invalidated, add
...
provisions for following constants jumps in next commit.
2003-11-30 17:16:24 +00:00
gbeauche
833fc0c935
remove dead code
2003-11-30 17:13:10 +00:00
gbeauche
efad4ff3b6
Handle even more XER test masks to be preserved or to be set.
2003-11-30 09:07:36 +00:00
gbeauche
d0a2277325
Gather stats about compile time. Define KPX_MAX_CPUS to 1 for allowing
...
allocation of translation cache into .data section on PowerPC.
2003-11-28 22:13:50 +00:00
gbeauche
0301afb3eb
first part of CR caching fixes
2003-11-28 22:11:59 +00:00
gbeauche
6a7c8f7e83
Add PowerPC tester glue for Microlib CPU core
2003-11-28 15:12:37 +00:00
gbeauche
3bea82fa1c
fix merge, hunks were missing
2003-11-27 23:59:00 +00:00
gbeauche
8ca440d0b5
Fix SRAW on non PowerPC platforms.
2003-11-27 23:53:41 +00:00
gbeauche
8711c4afd6
Add support for external results file for non PowerPC platforms.
2003-11-27 23:52:19 +00:00
gbeauche
2bacb2fd01
Workaround CR expectations in MODE_68K execution
2003-11-27 11:06:23 +00:00
gbeauche
d7ac6a0e68
Fix SLW & SRW, an x86 does not work the same way as a ppc
2003-11-27 10:53:37 +00:00
gbeauche
ae2d91912c
fix dummy includes
2003-11-27 10:06:27 +00:00
gbeauche
36ce9c07e6
Statically allocate the translation cache on PowerPC. This makes it possible
...
to generate direct bl instructions for function invokation.
2003-11-27 00:26:35 +00:00
gbeauche
e30001bc00
Fix BCCTR & BCLR. However, conditions are still wrong somehow, disabled
...
this case. Factored & optimized branch instructions.
2003-11-26 23:58:14 +00:00
gbeauche
2eba241021
self credit cpu emulator ;-)
2003-11-25 10:27:59 +00:00
gbeauche
73d51962f6
Merge in-progress PowerPC "JIT1" engine for AMD64, IA-32, PPC.
...
The merge probably got wrong as there are some problems probably due to the
experiment begining with CR deferred evaluation. With nbench/ppc, performance
improvement was around 2x. With nbench on x86, performance improvement was
around 4x on average.
Incompatible change: instr_info_t has a new field in the middle. But since
insertion of PPC_I(XXX) identifiers is auto-generated, there is no problem.
2003-11-24 23:45:52 +00:00
gbeauche
2a0f750a83
Optimize memory accesses on little endian systems that can do unaligned
...
accesses to memory. Fix build when vm.hpp is included in a C program.
2003-11-24 21:30:17 +00:00
gbeauche
e9f3546539
Remove even more obsolete code. Drop TBL/TBU registers, they are manually
...
handled through the mftb instruction accessor.
2003-11-11 11:44:34 +00:00
gbeauche
cf0ed72f24
Remove obsolete code related to PPC_NO_FPSCR_UPDATE, PPC_LAZY_PC_UPDATE,
...
PPC_LAZY_CC_UPDATE, PPC_HAVE_SPLIT_CR defines.
2003-11-11 11:32:27 +00:00
gbeauche
b66d8ef433
Fix "ignoresegv" case to actually skip the faulty instruction. Merge
...
conditions to skip instruction on SIGSEGVfrom PowerPC native mode. The
instruction skipper takes care to set the output register to 0.
2003-11-10 16:23:58 +00:00
gbeauche
0260210ddf
- XLM_IRQ_NEST is always in native byte order format since any write to
...
this variable go through {Enable,Disable}Interrupt().
- Add Ether thunks but only for WORDS_BIGENDIAN case since we do need more
complicated translation functions.
2003-11-10 15:11:44 +00:00
gbeauche
cd86ff9e94
- Start emulating the FPSCR. Fix mtfsf, mffs.
...
- Implement mftbr so that MacOS can fully boot with extensions. However,
using clock() is probably not the right solution. Patching UpTime from
DriverServicesLib et al. may be a better solution.
2003-11-09 15:39:30 +00:00
gbeauche
59e6227c08
fix mullwo & divw on invalid inputs
2003-11-09 07:19:39 +00:00
gbeauche
aebcb7a6bb
New testing framework faster to compile and more flexible. i.e. we now
...
generate 350K+ instructions. This exhausts errors for mullwo & divw.
2003-11-08 11:57:04 +00:00
gbeauche
4b73163083
Fix PPC_LAZY_CC_UPDATE build. TODO: remove since this is slower.
2003-11-04 22:01:36 +00:00
gbeauche
175dfeea02
fix lfs/stfs breakage introduced with latest FPR type change
2003-11-04 20:56:21 +00:00
gbeauche
8c40d739b6
Add some statistics for interrupt handling, Execute68k/Trap, MacOS & NativeOp
2003-11-04 20:48:29 +00:00
gbeauche
42e1cabc94
Move variables for compile statistics to powerpc_cpu private data
2003-11-04 20:45:46 +00:00
gbeauche
30bd089279
PowerPC floating-point registers are now an union of uint64 & double. This
...
eases FP load/stores.
2003-11-04 15:03:15 +00:00
gbeauche
8ddf749ed5
fix vm_do_read_memory_8()
2003-11-04 15:00:02 +00:00
gbeauche
a42281aad1
Implement partial block cache invalidation. Rewrite core cached blocks
...
execution loop with a Duff's device. Gather some predecode time statistics.
This shows that only around 2% of total emulation time is spent for
predecoding the instructions.
2003-11-03 21:28:32 +00:00
gbeauche
f0ea192460
Optimized pointers to non virtual member functions. This reduces space
...
and overhead since runtime checks are eliminated. Actually, it yields
up to 10% performance improvement with specialized decoders.
2003-11-02 14:48:20 +00:00
gbeauche
d956d3c4ca
add specialized instruction decoders (disabled for now)
2003-11-01 17:07:17 +00:00
gbeauche
89d0f9ca29
Integrate spcflags handling code to kpx_cpu core. We can also remove
...
oldish EXEC_RETURN handling with a throw/catch mechanism since we
do have a dependency on extra conditions (invalidated cache) that
prevents fast execution loops.
2003-11-01 15:15:31 +00:00
gbeauche
9ce43c6cf3
Fix ASYNC_IRQ build but locks may still happen. Note that with a predecode
...
cache, checking for pending interrupts may not be the bottle neck nowadays.
2003-10-26 14:16:40 +00:00
gbeauche
60d34a6816
Rewrite interrupts handling code so that the emulator can work with a
...
predecode cache. This implies to run in interpreted mode only while
processing EmulOps or other native (nested) runs.
Note that the FLIGHT_RECORDER with a predecode cache gets slower than
without caching at all.
2003-10-26 13:59:04 +00:00
gbeauche
d766049d59
- enable multicore cpu emulation with ASYNC_IRQ
...
- move atomic_* operations to main_unix so that they could use spinlocks or
other platform-specific locking mechanisms
2003-10-26 09:14:14 +00:00
gbeauche
ccf89d9efb
Preserve CR in execute_68k(). This enables MacOS 8.6 to work. ;-)
2003-10-19 21:37:43 +00:00
gbeauche
cb13fe3007
Log both r24 (m68k emulator PC) & stack pointer in SheepShaver mode only
2003-10-19 21:36:21 +00:00
gbeauche
9a05805a27
- Fix ADDME & ADDZE decoders, add RA==R0 testers
...
- Increase predecode cache size to 32K entries
- Enable PPC_EXECUTE_DUMP_STATE for predecode cache as well
2003-10-18 13:43:25 +00:00
gbeauche
1b9876889e
- Record address range of block to invalidate. i.e. icbi records ranges
...
and isync actually invalidate caches
2003-10-12 06:44:04 +00:00
gbeauche
7e0dccc544
- Handle MakeExecutable() replacement
...
- Disable predecode cache in CVS for now
- Fix flight recorder ordering in predecode cache mode
2003-10-12 05:44:17 +00:00
gbeauche
a3036b0c9d
Really enable flight_recorder with predecode cache on
2003-10-11 16:43:42 +00:00
gbeauche
7e20a8d205
- Add support for FLIGHT_RECORDER with predecode cache
...
- Always enable predecode cache & flight recorder for now
2003-10-11 09:57:52 +00:00
gbeauche
ebb67f0421
- Minor optimization to execute_ppc() as we apparently don't need to move
...
target PC into CTR.
- Fix breakage introduced during little endian fixing. We now assume that
MacOS doesn't rely on any PPC register that may have been saved on top
of it stack. i.e. register state is saved onto native stack.
2003-10-11 09:33:27 +00:00
gbeauche
1012da75dd
- Cleanups & make sure PPC emulator config is setup in sysdeps.h
...
- Log r24 in SheepShaver mode as this represents the 68k emulator PC
2003-10-11 09:03:03 +00:00
gbeauche
19053d4992
little endian fixes, note that trampolines are still not 64-bit clean either
2003-09-29 22:50:31 +00:00
gbeauche
5229b42622
basic implementation for missing functions (signbit/isless/isgreater) in
...
older C libraries
2003-09-29 22:45:31 +00:00
gbeauche
1713a26a3f
NULL is the null pointer to member function
2003-09-29 22:42:53 +00:00
gbeauche
b8b139faf2
- Share EmulatorData & KernelData struct definitions
...
- Introduce new SheepShaver data area for alternate stacks, thunks, etc.
- Experimental asynchronous interrupts handling. This improves performance
by 30% but some (rare) lockups may occur. To be debugged!
2003-09-29 15:46:09 +00:00
gbeauche
1c2fa89e31
use B2 sigsegv API instead of rewriting yet another sigsegv handler for x86
2003-09-29 07:05:15 +00:00
gbeauche
3851071ecd
Try to handle XLM_IRQ_NEST atomically in emulated PPC views. Fix placement
...
of fake SCSIGlobals (disabled for now). Switch back to mono core emulation
until things are debugged enough. Implement get_resource() et al.
2003-09-28 21:27:34 +00:00
gbeauche
2a86a4f62a
Handle dcbz. Ignore unaligned load/store multiple. Fix icbi/isync.
2003-09-28 21:22:59 +00:00
gbeauche
4e5e13d92d
make do_execute() a template so that execution loop prologues/epilogues
...
can be performed in derived engines
2003-09-28 21:22:09 +00:00
gbeauche
2f13888ea8
plain interpretive mode for debugging purposes
2003-09-28 21:21:07 +00:00
gbeauche
2a756136e4
more tests
2003-09-21 22:13:09 +00:00
gbeauche
2cc3b4edab
fix xoris
2003-09-21 21:45:05 +00:00
gbeauche
089247fcff
Merge in cpu core:
...
- make cache invalidation routines public
- fix shift instructions, especially for invalid shift counts
- fix mullwo to set overflow only if the product can't be represented in
32 bits
2003-09-15 22:48:57 +00:00
gbeauche
b5b471b4f1
add PowerPC emulator tester
2003-09-14 22:10:58 +00:00
gbeauche
fb8fbf71ed
PowerPC emulator fixes:
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- make divw. behaviour more realistic (vs ppc 7410) when rB == 0
- fix carry/overflow computations to fix SUBFME handling
- fix nand duplicate with wrong operand
2003-09-14 22:09:13 +00:00
gbeauche
029a7fd85b
Merge in old kpx_cpu snapshot for debugging
2003-09-07 14:25:05 +00:00