Zane Kaminski
3816ecd0a1
ugh
2021-03-19 02:56:20 -04:00
Zane Kaminski
a444cc31aa
idk
2021-03-15 13:40:59 -04:00
Zane Kaminski
e5da11855d
Remove old CPLD stuff
2021-03-15 13:40:41 -04:00
Zane Kaminski
db594211fa
Fabbed
2021-02-17 19:29:24 -05:00
Zane Kaminski
9f0867fe56
reset button detect
2020-10-25 05:22:14 -04:00
Zane Kaminski
3091ea4d32
Sketch of verilog
2020-10-07 23:32:29 -04:00
Zane Kaminski
66c0973cdf
Many changes
2020-03-10 18:54:44 -04:00
Zane Kaminski
7e41906335
Put FullIOEN back
2020-02-26 03:37:20 -05:00
Zane Kaminski
209afbc5c5
Added transfer counters
2020-02-26 03:34:33 -05:00
Zane Kaminski
6a33e1adb0
Added separate configuration section
2020-02-26 03:31:20 -05:00
Zane Kaminski
156aa66473
Cleanup
2020-02-26 03:15:36 -05:00
Zane Kaminski
593f5cb010
Removed inhibit output
2020-02-26 03:14:33 -05:00
Zane Kaminski
76bceb089d
Moved REGEN and IOROMEN (no functional change)
2020-02-26 03:14:13 -05:00
Zane Kaminski
4575818d63
Removed SetWR and FullIOEN
2020-02-26 02:13:35 -05:00
Zane Kaminski
d9e9038a4d
Comments, no actual changes to CPLD verilog
2020-02-16 22:03:57 -05:00
Zane Kaminski
b29662bcab
Fixed previous problem, working again
2020-02-16 00:11:12 -05:00
Zane Kaminski
79789a9e8b
Doesn't work but committing for posterity
2020-02-15 23:15:54 -05:00
Zane Kaminski
90875fd58f
Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev
2020-01-26 15:15:07 -05:00
Zane Kaminski
c02ffbbe6a
Separated CSDBEN
2020-01-26 15:13:37 -05:00
Zane Kaminski
2bc381ebc5
Removed state counter reset
2019-12-21 01:46:05 -05:00
Zane Kaminski
6e135d4305
Fixed bugs in new PLD stuff
2019-10-20 22:41:24 -04:00
Zane Kaminski
f471e04244
New PLD revision
...
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00
Zane Kaminski
ebaef9824f
Merge branch 'dev' of https://github.com/ZaneKaminski/GR8RAM into dev
2019-10-13 01:42:28 -04:00
Zane Kaminski
4ef5acf2d3
Register reset/initial values set syntax changed
2019-10-13 01:40:25 -04:00
Zane Kaminski
7f581f6ba0
24-bit counter, CAS fixed
2019-10-11 20:34:51 -04:00
Zane Kaminski
66fc09b402
Made AddrH high bit variable with mode input
2019-09-07 21:16:23 -04:00
Zane Kaminski
f52c6e4781
Pipelined addition
2019-09-04 21:45:56 -04:00
Zane Kaminski
a87ee9c819
Trying again with RamFactor firmware
2019-09-02 20:56:37 -04:00
Zane Kaminski
215f5ca2c6
Clarifications and bugfixes, will try again
2019-09-02 01:42:07 -04:00
Zane Kaminski
6b2378f99a
1MB CPLD design seems to work, fails Apple BIST
2019-09-01 21:18:44 -04:00
Zane Kaminski
396cc3c03c
CPLD firmware compiles
2019-08-31 22:55:04 -04:00