David Banks
7cc6bd93f4
build: include icemulti in overall release package
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Change-Id: Iba6962d3d25aec4b6dab080db8a607dcdc50f5f0
2019-11-02 20:09:57 +00:00
David Banks
c6f860ed2c
6502: seperate top level for GODIL and old LX9, rename modules for consistency
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Change-Id: I6d9f390a24b63a303f4a557e49ee68109af4c76a
2019-11-02 19:31:32 +00:00
David Banks
9c4c0837e5
6809: seperate top level for GODIL and old LX9
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Change-Id: I4a7d2a67c8aeaabc25d2987edb4a9026e92b1efc
2019-11-02 15:18:33 +00:00
David Banks
d9f53c1f09
Z80: refactor at top level to better support tristateable outputs
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Change-Id: Ic4a55eb99c85ff2032079d8d12c7d7e44803b6e2
2019-11-02 13:26:00 +00:00
David Banks
b8d08ccdaa
Z80: lx9_dave add pullups to tristateable outputs
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Change-Id: Ibee63f2940c921fde792ff7b63e15c2fbd4e8d32
2019-11-01 18:32:42 +00:00
David Banks
643afe51d3
.xise project churn (of no consequence)
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Change-Id: Ibfc0d1d89ca6e83bad34388a7557171650d89c0b
2019-10-27 19:21:26 +00:00
David Banks
ee1510d069
lx9_dave: makefile fixes
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Change-Id: I280b33ad597b59b0cbb55a85d919aba67136f339
2019-10-27 19:20:25 +00:00
David Banks
b9ac0628d2
lx9_dave: fix Makefile to build loader and unknown subdirs
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Change-Id: I4b2f5b588dd075452226d73269400255d9046cbd
2019-10-27 17:29:21 +00:00
David Banks
26f0bea110
Z80: Output NOPs when paused (inc M1)
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Change-Id: I100fac021d68662497fbd2d0c7428dcaf9ef98a3
2019-10-26 15:19:44 +01:00
David Banks
a29aa3015a
lx9_dave z80: increase code space to 32KB
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Change-Id: I7ab22f8cca51184b94e709336b661b8685d02d0b
2019-10-25 17:11:13 +01:00
David Banks
c045ebd10c
All 6809 designs now use MC6809CpuMonCore
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Change-Id: I97ca73690c7e1258a5b359260d695af25c21ca54
2019-10-24 14:06:03 +01:00
David Banks
3cc7789923
6502/65c02: Uncomment Rdy in .ucf file
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Change-Id: I6ef4f92dc4e0438c169d20ab5b05f8d4162478ff
2019-10-17 14:47:08 +01:00
David Banks
1c44718f91
Seperate 6502 and 65c02 builds
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Change-Id: I41af27c62e61a6490bda4da01da6e4f8740121fb
2019-10-16 20:40:15 +01:00
David Banks
cc1c8ba709
Multiboot: increase cclk to 26MHz
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Change-Id: I7bb6c17a582c7d283458bd7ed8a1bc2852bb73b3
2019-10-16 16:11:44 +01:00
David Banks
131312e0e9
Multiboot: initial impl
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Change-Id: I7efa2cf8079b4bfc1e89c5c26ecce30dfae34782
2019-10-16 15:49:58 +01:00
David Banks
9bcea56588
z80: CLK_n timing constraint now 8MHz
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Change-Id: Ia544905845a8b7996ff3e381a1e47184cc5dda82
2019-10-15 11:45:51 +01:00
David Banks
984ac1a2d3
z80: fixed an error in board.ucf in the previous commit
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Change-Id: Ib83916a7e1d1dcc163001ab342e65b80858d9c29
2019-10-03 18:26:15 +01:00
David Banks
dfeaff9488
6502: minor fixes to lx9_dave, boots in beeb
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Change-Id: I18c909f7586b439d52ecc938d4a9bb7a3e6d76e5
2019-10-03 13:17:18 +01:00
David Banks
c660ea87be
Updated lx9_dave/ice6502 for active level shifter design
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Change-Id: Ib2e98050d02c9c1e3dd7c9a9b63eea118b95a540
2019-09-20 15:34:44 +01:00
David Banks
a25a008ffc
Updated lx9_dave/icez80 for active level shifter design
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Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
David Banks
1dcf9fa247
Updated lx9_dave/ice6502 with correct .ucf file and a new top-level design
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Change-Id: Ic67e37fb876322983a44c35e9db08b1b8371aea2
2018-11-20 17:32:02 +00:00
David Banks
b9d6359be4
Checked in initial work on lx9_dave target (see full comment)
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The .ucf files look like they are for a completely different board
(the lx9 starter board, not the epizza board). So these need to be
reworked completely.
Also, the following signals needs adding to the top level 6502 design:
- OEAH (output)
- OEAL (output)
- OED (output)
- ML (output)
- VP (output)
- BE (input)
The system will not work without some attention to these.
Minimally, in the FPGA design we can tie them as follows:
- OEAH (output) - set to 0 (address bus always enabled)
- OEAL (output) - set to 0 (ditto)
- OED (output) - set to !phi2 (data bus driven in second half of clock)
- ML (output) - set output to 1 (and fit P3 link between pins 2 and 3)
- VP (output) - set output to 1 (and don't fit P4 link)
- BE (input) - ignore input
The current adapter design does not fully support the implementation of BE
as it does not provide a way to tristate RNW. That would require the addition
of a seperate level shifter, e.g. a 74LVC1G125
Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:42:58 +00:00
