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238 Commits 4 Branches 8 Tags 7.3 MiB
cfce5b1bd7
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40 Commits

Author SHA1 Message Date
David Banks
cfce5b1bd7 Z80/6809: rename clocks for consistency 
Change-Id: Iecd3ac5ede39865efc58eaa9e45f5892a44acb82
 2019-11-02 19:31:32 +00:00
David Banks
e0db1ccd7c Removed ice6502mon as it's never really been used 
Change-Id: I0898ea3450573c5dafc143e5589aa0a3b4a1dc6c
 2019-11-02 19:31:38 +00:00
David Banks
1227d174a9 Removed ice6502fast as it's never really been used 
Change-Id: I7179414838f0488b12f0cc01d51b09184d835546
 2019-11-02 19:31:32 +00:00
David Banks
9c4c0837e5 6809: seperate top level for GODIL and old LX9 
Change-Id: I4a7d2a67c8aeaabc25d2987edb4a9026e92b1efc
 2019-11-02 15:18:33 +00:00
David Banks
29438683b2 Z80: seperate top level for GODIL and old LX9 
Change-Id: I1f339996037bb8a20afb7664877e0ed1d53d3868
 2019-11-02 14:50:43 +00:00
David Banks
d9f53c1f09 Z80: refactor at top level to better support tristateable outputs 
Change-Id: Ic4a55eb99c85ff2032079d8d12c7d7e44803b6e2
 2019-11-02 13:26:00 +00:00
David Banks
b8d08ccdaa Z80: lx9_dave add pullups to tristateable outputs 
Change-Id: Ibee63f2940c921fde792ff7b63e15c2fbd4e8d32
 2019-11-01 18:32:42 +00:00
David Banks
c2e80e2e4c Build: simplfy makefile by outputting a .bin file 
Change-Id: I85cea0011a819fff3789e121a89af05b24ddfbd7
 2019-10-31 12:53:23 +00:00
David Banks
b0d7418a47 Add pullup to ICE-Z80 Mode input on GODIL 
Change-Id: I749690f5805adc34bb658f6ba9d161b240fb45a4
 2019-10-30 14:29:05 +00:00
David Banks
4818f026b2 Removed unused h44780 support (free AVR PortA) 
Change-Id: Iadde3718cfd6e8be08b680796d8c9cd01016e694
 2019-10-29 14:56:16 +00:00
David Banks
643afe51d3 .xise project churn (of no consequence) 
Change-Id: Ibfc0d1d89ca6e83bad34388a7557171650d89c0b
 2019-10-27 19:21:26 +00:00
David Banks
ee1510d069 lx9_dave: makefile fixes 
Change-Id: I280b33ad597b59b0cbb55a85d919aba67136f339
 2019-10-27 19:20:25 +00:00
David Banks
ff3a5143b8 lx9_dave: add build target for loader and unknown 
Change-Id: Ic9099b9e4586e86260c4396ee0e64066b729a18d
 2019-10-27 18:51:00 +00:00
David Banks
b6abb6964a Z80: Update all builds to 8 comparators and 16KB code 
Change-Id: I8adc986caab323de395301ba397f4c7874e50d49
 2019-10-27 17:32:29 +00:00
David Banks
820ee65cee Z80: Add mode input to other icez80 builds build 
Change-Id: I1b9130ec3835f08a4c3f429860aff6f09dc92d8c
 2019-10-27 17:30:23 +00:00
David Banks
b9ac0628d2 lx9_dave: fix Makefile to build loader and unknown subdirs 
Change-Id: I4b2f5b588dd075452226d73269400255d9046cbd
 2019-10-27 17:29:21 +00:00
David Banks
0b6e686934 Z80: Disable godil_250 build (no longer fits) 
Change-Id: I578f3fb6df2b36ef6a00b25a49ccc5f407bf7961
 2019-10-27 17:29:21 +00:00
David Banks
26f0bea110 Z80: Output NOPs when paused (inc M1) 
Change-Id: I100fac021d68662497fbd2d0c7428dcaf9ef98a3
 2019-10-26 15:19:44 +01:00
David Banks
a29aa3015a lx9_dave z80: increase code space to 32KB 
Change-Id: I7ab22f8cca51184b94e709336b661b8685d02d0b
 2019-10-25 17:11:13 +01:00
David Banks
c045ebd10c All 6809 designs now use MC6809CpuMonCore 
Change-Id: I97ca73690c7e1258a5b359260d695af25c21ca54
 2019-10-24 14:06:03 +01:00
David Banks
3cc7789923 6502/65c02: Uncomment Rdy in .ucf file 
Change-Id: I6ef4f92dc4e0438c169d20ab5b05f8d4162478ff
 2019-10-17 14:47:08 +01:00
David Banks
f4bff7757c Use CPU_65C02 for defined as CPU == 65C02 doesn't work 
Change-Id: Ibedbac5941ab897f0d530dfa3d73cc516d62bd8f
 2019-10-16 20:41:08 +01:00
David Banks
1c44718f91 Seperate 6502 and 65c02 builds 
Change-Id: I41af27c62e61a6490bda4da01da6e4f8740121fb
 2019-10-16 20:40:15 +01:00
David Banks
cc1c8ba709 Multiboot: increase cclk to 26MHz 
Change-Id: I7bb6c17a582c7d283458bd7ed8a1bc2852bb73b3
 2019-10-16 16:11:44 +01:00
David Banks
131312e0e9 Multiboot: initial impl 
Change-Id: I7efa2cf8079b4bfc1e89c5c26ecce30dfae34782
 2019-10-16 15:49:58 +01:00
David Banks
9bcea56588 z80: CLK_n timing constraint now 8MHz 
Change-Id: Ia544905845a8b7996ff3e381a1e47184cc5dda82
 2019-10-15 11:45:51 +01:00
David Banks
4c746994cb z80: major rewrite of memory access state machine 
Change-Id: Icc5c7c991120ed155691c1e74517ac02f8ea2ada
 2019-10-14 13:35:13 +01:00
David Banks
984ac1a2d3 z80: fixed an error in board.ucf in the previous commit 
Change-Id: Ib83916a7e1d1dcc163001ab342e65b80858d9c29
 2019-10-03 18:26:15 +01:00
David Banks
dfeaff9488 6502: minor fixes to lx9_dave, boots in beeb 
Change-Id: I18c909f7586b439d52ecc938d4a9bb7a3e6d76e5
 2019-10-03 13:17:18 +01:00
David Banks
c660ea87be Updated lx9_dave/ice6502 for active level shifter design 
Change-Id: Ib2e98050d02c9c1e3dd7c9a9b63eea118b95a540
 2019-09-20 15:34:44 +01:00
David Banks
a25a008ffc Updated lx9_dave/icez80 for active level shifter design 
Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
 2019-09-20 15:34:34 +01:00
David Banks
e9d4e98b96 LX9 6502: Move fakeTube input to p112 (next to a GND) 
Change-Id: Ib52362ed12ddc885025f1e098f864fdb313b795d
 2018-12-21 17:45:22 +00:00
David Banks
1dcf9fa247 Updated lx9_dave/ice6502 with correct .ucf file and a new top-level design 
Change-Id: Ic67e37fb876322983a44c35e9db08b1b8371aea2
 2018-11-20 17:32:02 +00:00
David Banks
b9d6359be4 Checked in initial work on lx9_dave target (see full comment) 
The .ucf files look like they are for a completely different board
(the lx9 starter board, not the epizza board). So these need to be
reworked completely.

Also, the following signals needs adding to the top level 6502 design:
- OEAH (output)
- OEAL (output)
- OED  (output)
- ML   (output)
- VP   (output)
- BE   (input)

The system will not work without some attention to these.

Minimally, in the FPGA design we can tie them as follows:
- OEAH (output) - set to 0 (address bus always enabled)
- OEAL (output) - set to 0 (ditto)
- OED  (output) - set to !phi2 (data bus driven in second half of clock)
- ML   (output) - set output to 1 (and fit P3 link between pins 2 and 3)
- VP   (output) - set output to 1 (and don't fit P4 link)
- BE   (input)  - ignore input

The current adapter design does not fully support the implementation of BE
as it does not provide a way to tristate RNW. That would require the addition
of a seperate level shifter, e.g. a 74LVC1G125

Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
 2018-11-20 09:42:58 +00:00
David Banks
40cac3c401 Updated Makefile for 64-bit build 
Change-Id: Ieaa309d30463209cd0e9c1aa6e6b23cbec8e92b0
 2018-02-15 13:05:49 +00:00
David Banks
e45e4423af Added lx9_jason_flipped to build 
Change-Id: I6c0a140a1e5229dca8eddc770a232712de17cd4b
 2017-09-22 22:57:54 +01:00
David Banks
7954f86e41 Added build for a flipped version of Jason's level shifter, so USB comes out at the pin 1 end (better for Beeb) 
Change-Id: Icd48522640507469b43ca3545fa1c46f88b0f0bb
 2017-08-09 18:16:11 +01:00
David Banks
168e5637e9 Pinout change for LX9: DIP pins 37 and 38 needed swapping 
Change-Id: I3f96f2d7cd8a8640e4a6c60466067daccf1e0590
 2017-08-09 16:37:41 +01:00
David Banks
6415a81a40 On LX9 board, updated Tx=51 and Rx=55 
Change-Id: I5bcd032eab29ef93d36e8011fee673028042483f
 2017-07-29 19:55:27 +01:00
David Banks
7453cf4f9f LX9 support: massive refactor of the build system 
Change-Id: I75ff141a0d3b2c30a37d8f0e497f4f923e302b8b
 2017-07-26 14:59:20 +01:00