2021-07-17 00:30:48 +00:00
|
|
|
|
//
|
|
|
|
|
// Amiga.cpp
|
|
|
|
|
// Clock Signal
|
|
|
|
|
//
|
|
|
|
|
// Created by Thomas Harte on 16/07/2021.
|
|
|
|
|
// Copyright © 2021 Thomas Harte. All rights reserved.
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
#include "Amiga.hpp"
|
|
|
|
|
|
2021-07-20 02:30:34 +00:00
|
|
|
|
#include "../../Activity/Source.hpp"
|
2021-07-17 00:49:12 +00:00
|
|
|
|
#include "../MachineTypes.hpp"
|
|
|
|
|
|
2021-07-17 01:07:12 +00:00
|
|
|
|
#include "../../Processors/68000/68000.hpp"
|
|
|
|
|
|
2021-07-18 15:49:10 +00:00
|
|
|
|
#include "../../Components/6526/6526.hpp"
|
|
|
|
|
|
2021-07-17 00:30:48 +00:00
|
|
|
|
#include "../../Analyser/Static/Amiga/Target.hpp"
|
|
|
|
|
|
2021-07-17 01:07:12 +00:00
|
|
|
|
#include "../Utility/MemoryPacker.hpp"
|
|
|
|
|
#include "../Utility/MemoryFuzzer.hpp"
|
|
|
|
|
|
2021-07-22 01:49:20 +00:00
|
|
|
|
//#define NDEBUG
|
2021-07-19 00:25:43 +00:00
|
|
|
|
#define LOG_PREFIX "[Amiga] "
|
|
|
|
|
#include "../../Outputs/Log.hpp"
|
|
|
|
|
|
2021-07-23 01:16:23 +00:00
|
|
|
|
#include "Chipset.hpp"
|
2021-07-22 22:43:07 +00:00
|
|
|
|
|
2021-07-17 00:30:48 +00:00
|
|
|
|
namespace Amiga {
|
|
|
|
|
|
|
|
|
|
class ConcreteMachine:
|
2021-07-20 02:30:34 +00:00
|
|
|
|
public Activity::Source,
|
2021-07-17 01:07:12 +00:00
|
|
|
|
public CPU::MC68000::BusHandler,
|
2021-07-17 00:49:12 +00:00
|
|
|
|
public MachineTypes::ScanProducer,
|
|
|
|
|
public MachineTypes::TimedMachine,
|
2021-07-17 00:30:48 +00:00
|
|
|
|
public Machine {
|
|
|
|
|
public:
|
2021-07-17 01:07:12 +00:00
|
|
|
|
ConcreteMachine(const Analyser::Static::Amiga::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
|
2021-07-18 15:49:10 +00:00
|
|
|
|
mc68000_(*this),
|
2021-07-23 01:16:23 +00:00
|
|
|
|
chipset_(reinterpret_cast<uint16_t *>(memory_.chip_ram.data()), memory_.chip_ram.size()),
|
2021-07-18 21:17:41 +00:00
|
|
|
|
cia_a_handler_(memory_),
|
2021-07-18 16:13:56 +00:00
|
|
|
|
cia_a_(cia_a_handler_),
|
|
|
|
|
cia_b_(cia_b_handler_)
|
2021-07-17 01:07:12 +00:00
|
|
|
|
{
|
2021-07-17 00:30:48 +00:00
|
|
|
|
(void)target;
|
2021-07-17 00:49:12 +00:00
|
|
|
|
|
2021-07-17 01:07:12 +00:00
|
|
|
|
// Temporary: use a hard-coded Kickstart selection.
|
|
|
|
|
constexpr ROM::Name rom_name = ROM::Name::AmigaA500Kickstart13;
|
|
|
|
|
ROM::Request request(rom_name);
|
|
|
|
|
auto roms = rom_fetcher(request);
|
|
|
|
|
if(!request.validate(roms)) {
|
|
|
|
|
throw ROMMachine::Error::MissingROMs;
|
|
|
|
|
}
|
2021-07-22 22:43:07 +00:00
|
|
|
|
Memory::PackBigEndian16(roms.find(rom_name)->second, memory_.kickstart.data());
|
2021-07-18 01:10:06 +00:00
|
|
|
|
|
|
|
|
|
// NTSC clock rate: 2*3.579545 = 7.15909Mhz.
|
2021-07-23 01:16:23 +00:00
|
|
|
|
// PAL clock rate: 7.09379Mhz; 227 cycles/line.
|
2021-07-18 01:10:06 +00:00
|
|
|
|
set_clock_rate(7'093'790.0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// MARK: - MC68000::BusHandler.
|
|
|
|
|
using Microcycle = CPU::MC68000::Microcycle;
|
|
|
|
|
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
|
2021-07-18 15:49:10 +00:00
|
|
|
|
// Intended 1-2 step here is:
|
2021-07-18 01:10:06 +00:00
|
|
|
|
//
|
|
|
|
|
// (1) determine when this CPU access will be scheduled;
|
|
|
|
|
// (2) do all the other actions prior to this CPU access being scheduled.
|
|
|
|
|
//
|
|
|
|
|
// (or at least enqueue them, JIT-wise).
|
|
|
|
|
|
2021-07-18 15:49:10 +00:00
|
|
|
|
// Advance time.
|
2021-07-19 23:03:37 +00:00
|
|
|
|
|
2021-07-23 23:25:53 +00:00
|
|
|
|
// The CIAs are on the E clock.
|
|
|
|
|
// TODO: so they probably should be behind VPA?
|
|
|
|
|
cia_divider_ += cycle.length;
|
|
|
|
|
const HalfCycles e_clocks = cia_divider_.divide(HalfCycles(20));
|
|
|
|
|
if(e_clocks > HalfCycles(0)) {
|
|
|
|
|
cia_a_.run_for(e_clocks);
|
|
|
|
|
cia_b_.run_for(e_clocks);
|
|
|
|
|
}
|
2021-07-18 15:49:10 +00:00
|
|
|
|
|
2021-07-24 01:24:07 +00:00
|
|
|
|
const auto changes = chipset_.run_for(cycle.length);
|
|
|
|
|
cia_a_.advance_tod(changes.vsyncs);
|
|
|
|
|
cia_b_.advance_tod(changes.hsyncs);
|
2021-07-23 01:45:51 +00:00
|
|
|
|
|
2021-07-20 01:50:35 +00:00
|
|
|
|
// Check for assertion of reset.
|
|
|
|
|
if(cycle.operation & Microcycle::Reset) {
|
2021-07-20 02:17:40 +00:00
|
|
|
|
memory_.reset();
|
2021-07-22 01:49:20 +00:00
|
|
|
|
LOG("Reset; PC is around " << PADHEX(8) << mc68000_.get_state().program_counter);
|
2021-07-20 01:50:35 +00:00
|
|
|
|
}
|
|
|
|
|
|
2021-07-18 15:49:10 +00:00
|
|
|
|
// Do nothing if no address is exposed.
|
|
|
|
|
if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
|
|
|
|
|
|
2021-07-18 01:10:06 +00:00
|
|
|
|
// TODO: interrupt acknowledgement.
|
|
|
|
|
|
|
|
|
|
// Grab the target address to pick a memory source.
|
|
|
|
|
const uint32_t address = cycle.host_endian_byte_address();
|
2021-07-22 01:49:20 +00:00
|
|
|
|
// if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord)) && !(cycle.operation & Microcycle::IsProgram)) {
|
2021-07-19 00:25:43 +00:00
|
|
|
|
// printf("%06x\n", *cycle.address);
|
|
|
|
|
// }
|
2021-07-18 01:36:20 +00:00
|
|
|
|
|
2021-07-22 22:43:07 +00:00
|
|
|
|
if(!memory_.regions[address >> 18].read_write_mask) {
|
2021-07-18 01:36:20 +00:00
|
|
|
|
if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) {
|
|
|
|
|
// Check for various potential chip accesses.
|
2021-07-18 16:13:56 +00:00
|
|
|
|
|
2021-07-18 21:17:41 +00:00
|
|
|
|
// Per the manual:
|
|
|
|
|
//
|
2021-07-18 16:13:56 +00:00
|
|
|
|
// CIA A is: 101x xxxx xx01 rrrr xxxx xxx0 (i.e. loaded into high byte)
|
|
|
|
|
// CIA B is: 101x xxxx xx10 rrrr xxxx xxx1 (i.e. loaded into low byte)
|
2021-07-18 21:17:41 +00:00
|
|
|
|
//
|
|
|
|
|
// but in order to map 0xbfexxx to CIA A and 0xbfdxxx to CIA B, I think
|
|
|
|
|
// these might be listed the wrong way around.
|
|
|
|
|
//
|
|
|
|
|
// Additional assumption: the relevant CIA select lines are connected
|
|
|
|
|
// directly to the chip enables.
|
2021-07-18 16:13:56 +00:00
|
|
|
|
if((address & 0xe0'0000) == 0xa0'0000) {
|
|
|
|
|
const int reg = address >> 8;
|
2021-07-20 00:54:32 +00:00
|
|
|
|
LOG("CIA access: " << PADHEX(4) << *cycle.address);
|
2021-07-18 16:13:56 +00:00
|
|
|
|
|
|
|
|
|
if(cycle.operation & Microcycle::Read) {
|
|
|
|
|
uint16_t result = 0xffff;
|
2021-07-20 02:17:40 +00:00
|
|
|
|
if(!(address & 0x1000)) result &= 0xff00 | (cia_a_.read(reg) << 0);
|
|
|
|
|
if(!(address & 0x2000)) result &= 0x00ff | (cia_b_.read(reg) << 8);
|
2021-07-18 16:13:56 +00:00
|
|
|
|
cycle.set_value16(result);
|
|
|
|
|
} else {
|
2021-07-20 02:17:40 +00:00
|
|
|
|
if(!(address & 0x1000)) cia_a_.write(reg, cycle.value8_low());
|
|
|
|
|
if(!(address & 0x2000)) cia_b_.write(reg, cycle.value8_high());
|
2021-07-18 16:13:56 +00:00
|
|
|
|
}
|
2021-07-18 01:36:20 +00:00
|
|
|
|
} else if(address >= 0xdf'f000 && address <= 0xdf'f1be) {
|
2021-07-23 01:16:23 +00:00
|
|
|
|
chipset_.perform(cycle);
|
2021-07-18 01:36:20 +00:00
|
|
|
|
} else {
|
|
|
|
|
// This'll do for open bus, for now.
|
2021-07-22 01:49:20 +00:00
|
|
|
|
if(cycle.operation & Microcycle::Read) {
|
|
|
|
|
cycle.set_value16(0xffff);
|
|
|
|
|
}
|
2021-07-24 03:10:00 +00:00
|
|
|
|
LOG("Unmapped " << (cycle.operation & Microcycle::Read ? "read from " : "write to ") << PADHEX(4) << *cycle.address << " of " << cycle.value16());
|
2021-07-18 01:36:20 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
// A regular memory access.
|
|
|
|
|
cycle.apply(
|
2021-07-22 22:43:07 +00:00
|
|
|
|
&memory_.regions[address >> 18].contents[address],
|
|
|
|
|
memory_.regions[address >> 18].read_write_mask
|
2021-07-18 01:36:20 +00:00
|
|
|
|
);
|
2021-07-18 01:10:06 +00:00
|
|
|
|
}
|
2021-07-17 01:07:12 +00:00
|
|
|
|
|
|
|
|
|
return HalfCycles(0);
|
|
|
|
|
}
|
2021-07-17 00:49:12 +00:00
|
|
|
|
|
|
|
|
|
private:
|
2021-07-17 01:07:12 +00:00
|
|
|
|
CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
|
2021-07-17 01:41:32 +00:00
|
|
|
|
|
|
|
|
|
// MARK: - Memory map.
|
2021-07-18 21:17:41 +00:00
|
|
|
|
struct MemoryMap {
|
|
|
|
|
public:
|
2021-07-22 22:43:07 +00:00
|
|
|
|
std::array<uint8_t, 512*1024> chip_ram{};
|
|
|
|
|
std::array<uint8_t, 512*1024> kickstart{0xff};
|
2021-07-18 21:17:41 +00:00
|
|
|
|
|
|
|
|
|
struct MemoryRegion {
|
|
|
|
|
uint8_t *contents = nullptr;
|
2021-07-19 00:55:33 +00:00
|
|
|
|
unsigned int read_write_mask = 0;
|
2021-07-22 22:43:07 +00:00
|
|
|
|
} regions[64]; // i.e. top six bits are used as an index.
|
2021-07-18 21:17:41 +00:00
|
|
|
|
|
|
|
|
|
MemoryMap() {
|
|
|
|
|
// Address spaces that matter:
|
|
|
|
|
//
|
|
|
|
|
// 00'0000 – 08'0000: chip RAM. [or overlayed KickStart]
|
|
|
|
|
// – 10'0000: extended chip ram for ECS.
|
|
|
|
|
// – 20'0000: auto-config space (/fast RAM).
|
|
|
|
|
// ...
|
|
|
|
|
// bf'd000 – c0'0000: 8250s.
|
|
|
|
|
// c0'0000 – d8'0000: pseudo-fast RAM.
|
|
|
|
|
// ...
|
|
|
|
|
// dc'0000 – dd'0000: optional real-time clock.
|
|
|
|
|
// df'f000 - e0'0000: custom chip registers.
|
|
|
|
|
// ...
|
|
|
|
|
// f0'0000 — : 512kb Kickstart (or possibly just an extra 512kb reserved for hypothetical 1mb Kickstart?).
|
|
|
|
|
// f8'0000 — : 256kb Kickstart if 2.04 or higher.
|
|
|
|
|
// fc'0000 – : 256kb Kickstart otherwise.
|
2021-07-22 22:43:07 +00:00
|
|
|
|
set_region(0xfc'0000, 0x1'00'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
|
2021-07-20 02:17:40 +00:00
|
|
|
|
reset();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void reset() {
|
2021-07-18 21:17:41 +00:00
|
|
|
|
set_overlay(true);
|
|
|
|
|
}
|
2021-07-17 01:41:32 +00:00
|
|
|
|
|
2021-07-18 21:17:41 +00:00
|
|
|
|
void set_overlay(bool enabled) {
|
|
|
|
|
if(overlay_ == enabled) {
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
overlay_ = enabled;
|
2021-07-17 01:07:12 +00:00
|
|
|
|
|
2021-07-18 21:17:41 +00:00
|
|
|
|
if(enabled) {
|
2021-07-22 22:43:07 +00:00
|
|
|
|
set_region(0x00'0000, 0x08'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
|
2021-07-18 21:17:41 +00:00
|
|
|
|
} else {
|
2021-07-22 01:49:20 +00:00
|
|
|
|
// Mirror RAM to fill out the address range up to $20'0000 (?)
|
2021-07-22 22:43:07 +00:00
|
|
|
|
set_region(0x00'0000, 0x08'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
|
2021-07-18 21:17:41 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
2021-07-18 01:10:06 +00:00
|
|
|
|
|
2021-07-18 21:17:41 +00:00
|
|
|
|
private:
|
|
|
|
|
bool overlay_ = false;
|
|
|
|
|
|
2021-07-19 00:55:33 +00:00
|
|
|
|
void set_region(int start, int end, uint8_t *base, unsigned int read_write_mask) {
|
2021-07-18 21:17:41 +00:00
|
|
|
|
assert(!(start & ~0xfc'0000));
|
|
|
|
|
assert(!((end - (1 << 18)) & ~0xfc'0000));
|
|
|
|
|
|
2021-07-22 01:49:20 +00:00
|
|
|
|
base -= start;
|
2021-07-18 21:17:41 +00:00
|
|
|
|
for(int c = start >> 18; c < end >> 18; c++) {
|
2021-07-22 22:43:07 +00:00
|
|
|
|
regions[c].contents = base;
|
|
|
|
|
regions[c].read_write_mask = read_write_mask;
|
2021-07-18 21:17:41 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} memory_;
|
2021-07-18 01:10:06 +00:00
|
|
|
|
|
2021-07-23 01:16:23 +00:00
|
|
|
|
// MARK: - Chipset.
|
2021-07-19 00:25:43 +00:00
|
|
|
|
|
2021-07-23 01:16:23 +00:00
|
|
|
|
Chipset chipset_;
|
2021-07-19 00:25:43 +00:00
|
|
|
|
|
2021-07-18 15:49:10 +00:00
|
|
|
|
// MARK: - CIAs.
|
|
|
|
|
|
2021-07-18 21:17:41 +00:00
|
|
|
|
class CIAAHandler: public MOS::MOS6526::PortHandler {
|
|
|
|
|
public:
|
|
|
|
|
CIAAHandler(MemoryMap &map) : map_(map) {}
|
|
|
|
|
|
|
|
|
|
void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
|
|
|
|
|
if(port) {
|
|
|
|
|
// Parallel port output.
|
2021-07-22 01:49:20 +00:00
|
|
|
|
LOG("TODO: parallel output " << PADHEX(2) << +value);
|
2021-07-18 21:17:41 +00:00
|
|
|
|
} else {
|
|
|
|
|
// b7: /FIR1
|
|
|
|
|
// b6: /FIR0
|
|
|
|
|
// b5: /RDY
|
|
|
|
|
// b4: /TRK0
|
|
|
|
|
// b3: /WPRO
|
|
|
|
|
// b2: /CHNG
|
|
|
|
|
// b1: /LED [output]
|
|
|
|
|
// b0: OVL [output]
|
|
|
|
|
|
2021-07-22 01:49:20 +00:00
|
|
|
|
LOG("LED & memory map: " << PADHEX(2) << +value);
|
2021-07-20 02:30:34 +00:00
|
|
|
|
if(observer_) {
|
|
|
|
|
observer_->set_led_status(led_name, !(value & 2));
|
|
|
|
|
}
|
2021-07-18 21:17:41 +00:00
|
|
|
|
map_.set_overlay(value & 1);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-07-19 00:25:43 +00:00
|
|
|
|
uint8_t get_port_input(MOS::MOS6526::Port port) {
|
2021-07-20 02:17:40 +00:00
|
|
|
|
if(port) {
|
|
|
|
|
LOG("TODO: parallel input?");
|
|
|
|
|
} else {
|
|
|
|
|
LOG("TODO: CIA A, port A input — FIR, RDY, TRK0, etc");
|
|
|
|
|
}
|
2021-07-19 00:25:43 +00:00
|
|
|
|
return 0xff;
|
|
|
|
|
}
|
|
|
|
|
|
2021-07-20 02:30:34 +00:00
|
|
|
|
void set_activity_observer(Activity::Observer *observer) {
|
|
|
|
|
observer_ = observer;
|
|
|
|
|
if(observer) {
|
|
|
|
|
observer->register_led(led_name, Activity::Observer::LEDPresentation::Persistent);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-07-18 21:17:41 +00:00
|
|
|
|
private:
|
|
|
|
|
MemoryMap &map_;
|
2021-07-20 02:30:34 +00:00
|
|
|
|
Activity::Observer *observer_ = nullptr;
|
|
|
|
|
inline static const std::string led_name = "Power";
|
2021-07-18 16:13:56 +00:00
|
|
|
|
} cia_a_handler_;
|
2021-07-18 15:49:10 +00:00
|
|
|
|
|
2021-07-18 16:13:56 +00:00
|
|
|
|
struct CIABHandler: public MOS::MOS6526::PortHandler {
|
2021-07-19 23:03:37 +00:00
|
|
|
|
void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
|
|
|
|
|
if(port) {
|
|
|
|
|
// Serial port control.
|
|
|
|
|
//
|
|
|
|
|
// b7: /DTR
|
|
|
|
|
// b6: /RTS
|
|
|
|
|
// b5: /CD
|
|
|
|
|
// b4: /CTS
|
|
|
|
|
// b3: /DSR
|
|
|
|
|
// b2: SEL
|
|
|
|
|
// b1: POUT
|
|
|
|
|
// b0: BUSY
|
2021-07-22 20:10:30 +00:00
|
|
|
|
LOG("TODO: Serial control: " << PADHEX(2) << +value);
|
2021-07-19 23:03:37 +00:00
|
|
|
|
} else {
|
|
|
|
|
// Disk motor control, drive and head selection,
|
|
|
|
|
// and stepper control:
|
|
|
|
|
//
|
|
|
|
|
// b7: /MTR
|
|
|
|
|
// b6: /SEL3
|
|
|
|
|
// b5: /SEL2
|
|
|
|
|
// b4: /SEL1
|
|
|
|
|
// b3: /SEL0
|
|
|
|
|
// b2: /SIDE
|
|
|
|
|
// b1: DIR
|
|
|
|
|
// b0: /STEP
|
2021-07-22 20:10:30 +00:00
|
|
|
|
LOG("TODO: Stepping, etc; " << PADHEX(2) << +value);
|
2021-07-19 23:03:37 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
2021-07-18 16:13:56 +00:00
|
|
|
|
} cia_b_handler_;
|
2021-07-18 15:49:10 +00:00
|
|
|
|
|
2021-07-23 23:25:53 +00:00
|
|
|
|
HalfCycles cia_divider_;
|
2021-07-18 16:13:56 +00:00
|
|
|
|
MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250> cia_a_;
|
|
|
|
|
MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250> cia_b_;
|
2021-07-18 15:49:10 +00:00
|
|
|
|
|
2021-07-20 02:30:34 +00:00
|
|
|
|
// MARK: - Activity Source
|
|
|
|
|
void set_activity_observer(Activity::Observer *observer) final {
|
|
|
|
|
cia_a_handler_.set_activity_observer(observer);
|
|
|
|
|
}
|
|
|
|
|
|
2021-07-17 00:49:12 +00:00
|
|
|
|
// MARK: - MachineTypes::ScanProducer.
|
|
|
|
|
|
|
|
|
|
void set_scan_target(Outputs::Display::ScanTarget *scan_target) final {
|
|
|
|
|
(void)scan_target;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Outputs::Display::ScanStatus get_scaled_scan_status() const {
|
|
|
|
|
return Outputs::Display::ScanStatus();
|
2021-07-17 00:30:48 +00:00
|
|
|
|
}
|
|
|
|
|
|
2021-07-17 00:49:12 +00:00
|
|
|
|
// MARK: - MachineTypes::TimedMachine.
|
|
|
|
|
|
|
|
|
|
void run_for(const Cycles cycles) {
|
2021-07-17 01:07:12 +00:00
|
|
|
|
mc68000_.run_for(cycles);
|
2021-07-17 00:49:12 +00:00
|
|
|
|
}
|
2021-07-17 00:30:48 +00:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
using namespace Amiga;
|
|
|
|
|
|
|
|
|
|
Machine *Machine::Amiga(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
|
|
|
|
|
using Target = Analyser::Static::Amiga::Target;
|
|
|
|
|
const Target *const amiga_target = dynamic_cast<const Target *>(target);
|
|
|
|
|
return new Amiga::ConcreteMachine(*amiga_target, rom_fetcher);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Machine::~Machine() {}
|