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CLK/InstructionSets/x86/Decoder.cpp

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Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
//
// x86.cpp
// Clock Signal
//
Switches all American-style dates. I'd failed to configure my new computer appropriately, it seems.
2021-01-17 03:09:19 +00:00
// Created by Thomas Harte on 01/01/21.
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
// Copyright © 2021 Thomas Harte. All rights reserved.
//
Better plans project layout.
2021-01-15 23:16:01 +00:00
#include "Decoder.hpp"
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Proceeds to three instructions correctly decoded. 'Wow'.
2021-01-03 22:03:50 +00:00
#include <algorithm>
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
#include <cassert>
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
#include <utility>
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
Adds files for the M50740 and corrects namespace errors elsewhere.
2021-01-16 02:30:30 +00:00
using namespace InstructionSet::x86;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Switch `Decoder` into a template.
2022-02-21 17:21:57 +00:00
template <Model model>
Template `Instruction` on its content size.
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std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(const uint8_t *source, size_t length) {
Add instruction length limits.
2022-03-11 01:47:56 +00:00
// Instruction length limits:
//
Switch strategy on 8086 instruction lengths.
2022-03-11 14:48:26 +00:00
// 8086/80186: none*
Add instruction length limits.
2022-03-11 01:47:56 +00:00
// 80286: 10 bytes
// 80386: 15 bytes
Switch strategy on 8086 instruction lengths.
2022-03-11 14:48:26 +00:00
//
// * but, can treat internally as a limit of 65536 bytes — after that distance the IP will
// be back to wherever it started, so it's safe to spit out a NOP and reset parsing
// without any loss of context. This reduces the risk of the decoder tricking a caller into
// an infinite loop.
constexpr int max_instruction_length = model >= Model::i80386 ? 15 : (model == Model::i80286 ? 10 : 65536);
const uint8_t *const end = source + std::min(length, size_t(max_instruction_length - consumed_));
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// MARK: - Prefixes (if present) and the opcode.
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
/// Helper macro for those that follow.
#define SetOpSrcDestSize(op, src, dest, size) \
operation_ = Operation::op; \
source_ = Source::src; \
destination_ = Source::dest; \
operation_size_ = size
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
/// Covers anything which is complete as soon as the opcode is encountered.
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
#define Complete(op, src, dest, size) \
SetOpSrcDestSize(op, src, dest, size); \
phase_ = Phase::ReadyToPost
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
/// Handles instructions of the form rr, kk and rr, jjkk, i.e. a destination register plus an operand.
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
#define RegData(op, dest, size) \
SetOpSrcDestSize(op, DirectAddress, dest, size); \
Ensures that the operand is the only thing failing in decoding of the first instruction.
2021-01-09 04:02:06 +00:00
source_ = Source::Immediate; \
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
operand_size_ = size; \
Remove further errant 'Awaiting's.
2022-01-31 13:22:07 +00:00
phase_ = Phase::DisplacementOrOperand
Improves exposition, adds decoding of the 0xbx patch of MOVs.
2021-01-04 00:33:16 +00:00
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
/// Handles instructions of the form Ax, jjkk where the latter is implicitly an address.
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
#define RegAddr(op, dest, op_size, addr_size) \
SetOpSrcDestSize(op, DirectAddress, dest, op_size); \
Fixed: INs and OUTs remain single byte.
2022-03-09 15:51:16 +00:00
operand_size_ = addr_size; \
Remove further errant 'Awaiting's.
2022-01-31 13:22:07 +00:00
phase_ = Phase::DisplacementOrOperand
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
/// Handles instructions of the form jjkk, Ax where the former is implicitly an address.
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
#define AddrReg(op, source, op_size, addr_size) \
SetOpSrcDestSize(op, source, DirectAddress, op_size); \
Fixed: INs and OUTs remain single byte.
2022-03-09 15:51:16 +00:00
operand_size_ = addr_size; \
Completes the first test stream. ... and improves decoding consistency in conjunction.
2021-01-13 02:49:22 +00:00
destination_ = Source::DirectAddress; \
Remove further errant 'Awaiting's.
2022-01-31 13:22:07 +00:00
phase_ = Phase::DisplacementOrOperand
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
/// Covers both `mem/reg, reg` and `reg, mem/reg`.
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
#define MemRegReg(op, format, size) \
operation_ = Operation::op; \
phase_ = Phase::ModRegRM; \
modregrm_format_ = ModRegRMFormat::format; \
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
operand_size_ = DataSize::None; \
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
operation_size_ = size
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
/// Handles JO, JNO, JB, etc — anything with only a displacement.
#define Displacement(op, size) \
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
operation_ = Operation::op; \
Remove further errant 'Awaiting's.
2022-01-31 13:22:07 +00:00
phase_ = Phase::DisplacementOrOperand; \
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
displacement_size_ = size
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
/// Handles PUSH [immediate], etc — anything with only an immediate operand.
#define Immediate(op, size) \
operation_ = Operation::op; \
source_ = Source::Immediate; \
phase_ = Phase::DisplacementOrOperand; \
operand_size_ = size
The address size modifier doesn't seem to affect far address sizes. It's meant to affect only instructions with operands that reside in memory, I think. So probably only ::DirectAddress in my nomenclature. More research to do.
2022-03-11 17:46:07 +00:00
/// Handles far CALL and far JMP — fixed four or six byte operand operations.
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
#define Far(op) \
operation_ = Operation::op; \
Remove further errant 'Awaiting's.
2022-01-31 13:22:07 +00:00
phase_ = Phase::DisplacementOrOperand; \
Fix segment/offset sizes for far calls.
2022-03-09 20:23:43 +00:00
operand_size_ = DataSize::Word; \
The address size modifier doesn't seem to affect far address sizes. It's meant to affect only instructions with operands that reside in memory, I think. So probably only ::DirectAddress in my nomenclature. More research to do.
2022-03-11 17:46:07 +00:00
displacement_size_ = data_size(default_address_size_)
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
/// Handles ENTER — a fixed three-byte operation.
#define Displacement16Operand8(op) \
operation_ = Operation::op; \
phase_ = Phase::DisplacementOrOperand; \
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
displacement_size_ = DataSize::Word; \
operand_size_ = DataSize::Byte
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
Adds the missing shift group segues at c0 and c1.
2022-03-07 14:18:59 +00:00
/// Sets up the operation size, oncoming phase and modregrm format for a member of the shift group (i.e. 'group 2').
#define ShiftGroup() { \
const DataSize sizes[] = {DataSize::Byte, data_size_}; \
phase_ = Phase::ModRegRM; \
modregrm_format_ = ModRegRMFormat::MemRegROL_to_SAR; \
operation_size_ = sizes[instr & 1]; \
}
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
#define undefined() { \
Template `Instruction` on its content size.
2022-02-21 17:36:03 +00:00
const auto result = std::make_pair(consumed_, InstructionT()); \
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
reset_parsing(); \
return result; \
}
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
#define Requires(x) if constexpr (model != Model::x) undefined();
#define RequiresMin(x) if constexpr (model < Model::x) undefined();
Proceeds to three instructions correctly decoded. 'Wow'.
2021-01-03 22:03:50 +00:00
while(phase_ == Phase::Instruction && source != end) {
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
const uint8_t instr = *source;
Finally runs into the wall of trying to merge operands and offsets.
2021-01-04 01:08:13 +00:00
++source;
++consumed_;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
switch(instr) {
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
default: undefined();
Attempts to consolidate source/destination ordering.
2021-01-03 22:28:29 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
#define PartialBlock(start, operation) \
case start + 0x00: MemRegReg(operation, MemReg_Reg, DataSize::Byte); break; \
case start + 0x01: MemRegReg(operation, MemReg_Reg, data_size_); break; \
case start + 0x02: MemRegReg(operation, Reg_MemReg, DataSize::Byte); break; \
case start + 0x03: MemRegReg(operation, Reg_MemReg, data_size_); break; \
case start + 0x04: RegData(operation, eAX, DataSize::Byte); break; \
case start + 0x05: RegData(operation, eAX, data_size_)
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
PartialBlock(0x00, ADD); break;
case 0x06: Complete(PUSH, ES, None, data_size_); break;
case 0x07: Complete(POP, None, ES, data_size_); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
PartialBlock(0x08, OR); break;
case 0x0e: Complete(PUSH, CS, None, data_size_); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
// The 286 onwards have a further set of instructions
// prefixed with $0f.
case 0x0f:
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80286);
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
phase_ = Phase::InstructionPageF;
break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
PartialBlock(0x10, ADC); break;
case 0x16: Complete(PUSH, SS, None, DataSize::Word); break;
case 0x17: Complete(POP, None, SS, DataSize::Word); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
PartialBlock(0x18, SBB); break;
case 0x1e: Complete(PUSH, DS, None, DataSize::Word); break;
case 0x1f: Complete(POP, None, DS, DataSize::Word); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
PartialBlock(0x20, AND); break;
case 0x26: segment_override_ = Source::ES; break;
case 0x27: Complete(DAA, eAX, eAX, DataSize::Byte); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
PartialBlock(0x28, SUB); break;
case 0x2e: segment_override_ = Source::CS; break;
case 0x2f: Complete(DAS, eAX, eAX, DataSize::Byte); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
PartialBlock(0x30, XOR); break;
case 0x36: segment_override_ = Source::SS; break;
case 0x37: Complete(AAA, eAX, eAX, DataSize::Word); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
PartialBlock(0x38, CMP); break;
case 0x3e: segment_override_ = Source::DS; break;
case 0x3f: Complete(AAS, eAX, eAX, DataSize::Word); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
#undef PartialBlock
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
#define RegisterBlock(start, operation) \
case start + 0x00: Complete(operation, eAX, eAX, data_size_); break; \
case start + 0x01: Complete(operation, eCX, eCX, data_size_); break; \
case start + 0x02: Complete(operation, eDX, eDX, data_size_); break; \
case start + 0x03: Complete(operation, eBX, eBX, data_size_); break; \
case start + 0x04: Complete(operation, eSP, eSP, data_size_); break; \
case start + 0x05: Complete(operation, eBP, eBP, data_size_); break; \
case start + 0x06: Complete(operation, eSI, eSI, data_size_); break; \
case start + 0x07: Complete(operation, eDI, eDI, data_size_)
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
RegisterBlock(0x40, INC); break;
RegisterBlock(0x48, DEC); break;
RegisterBlock(0x50, PUSH); break;
RegisterBlock(0x58, POP); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
#undef RegisterBlock
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
case 0x60:
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80186);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Complete(PUSHA, None, None, data_size_);
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
break;
case 0x61:
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80186);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Complete(POPA, None, None, data_size_);
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
break;
case 0x62:
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80186);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
MemRegReg(BOUND, Reg_MemReg, data_size_);
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
break;
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
case 0x63:
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80286);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
MemRegReg(ARPL, MemReg_Reg, DataSize::Word);
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
break;
Add 80386 segment overrides.
2022-03-05 22:03:46 +00:00
case 0x64:
RequiresMin(i80386);
segment_override_ = Source::FS;
break;
case 0x65:
RequiresMin(i80386);
segment_override_ = Source::GS;
break;
Sets up [ignored] memory and data size prefixes.
2022-03-03 01:23:35 +00:00
case 0x66:
RequiresMin(i80386);
data_size_ = DataSize(int(default_data_size_) ^ int(DataSize::Word) ^ int(DataSize::DWord));
break;
case 0x67:
RequiresMin(i80386);
address_size_ = AddressSize(int(default_address_size_) ^ int(AddressSize::b16) ^ int(AddressSize::b32));
break;
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
case 0x68:
RequiresMin(i80286);
Immediate(PUSH, data_size_);
Record PUSH immediate operation size.
2022-03-09 19:24:57 +00:00
operation_size_ = data_size_;
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
break;
Introduce additional forms of IMUL.
2022-03-07 14:05:22 +00:00
case 0x69:
RequiresMin(i80286);
MemRegReg(IMUL_3, Reg_MemReg, data_size_);
operand_size_ = data_size_;
break;
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
case 0x6a:
RequiresMin(i80286);
Immediate(PUSH, DataSize::Byte);
break;
Introduce additional forms of IMUL.
2022-03-07 14:05:22 +00:00
case 0x6b:
RequiresMin(i80286);
MemRegReg(IMUL_3, Reg_MemReg, data_size_);
operand_size_ = DataSize::Byte;
sign_extend_ = true;
break;
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
case 0x6c: // INSB
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80186);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Complete(INS, None, None, DataSize::Byte);
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
break;
Eliminate INSD.
2022-03-12 16:37:21 +00:00
case 0x6d: // INSW/INSD
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80186);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Complete(INS, None, None, data_size_);
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
break;
case 0x6e: // OUTSB
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80186);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Complete(OUTS, None, None, DataSize::Byte);
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
break;
Eliminate INSD.
2022-03-12 16:37:21 +00:00
case 0x6f: // OUTSW/OUSD
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80186);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Complete(OUTS, None, None, data_size_);
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
case 0x70: Displacement(JO, DataSize::Byte); break;
case 0x71: Displacement(JNO, DataSize::Byte); break;
case 0x72: Displacement(JB, DataSize::Byte); break;
case 0x73: Displacement(JNB, DataSize::Byte); break;
Agree that JZ/JNZ are clearer (for me) of the synonyms.
2023-09-19 17:38:08 +00:00
case 0x74: Displacement(JZ, DataSize::Byte); break;
case 0x75: Displacement(JNZ, DataSize::Byte); break;
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
case 0x76: Displacement(JBE, DataSize::Byte); break;
case 0x77: Displacement(JNBE, DataSize::Byte); break;
case 0x78: Displacement(JS, DataSize::Byte); break;
case 0x79: Displacement(JNS, DataSize::Byte); break;
case 0x7a: Displacement(JP, DataSize::Byte); break;
case 0x7b: Displacement(JNP, DataSize::Byte); break;
case 0x7c: Displacement(JL, DataSize::Byte); break;
case 0x7d: Displacement(JNL, DataSize::Byte); break;
case 0x7e: Displacement(JLE, DataSize::Byte); break;
case 0x7f: Displacement(JNLE, DataSize::Byte); break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Clarify sign extension availability.
2022-03-05 21:44:26 +00:00
case 0x80: MemRegReg(Invalid, MemRegADD_to_CMP, DataSize::Byte); break;
case 0x81: MemRegReg(Invalid, MemRegADD_to_CMP, data_size_); break;
case 0x82: MemRegReg(Invalid, MemRegADD_to_CMP_SignExtend, DataSize::Byte); break;
case 0x83: MemRegReg(Invalid, MemRegADD_to_CMP_SignExtend, data_size_); break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Add the SETs.
2022-03-07 15:32:34 +00:00
case 0x84: MemRegReg(TEST, MemReg_Reg, DataSize::Byte); break;
case 0x85: MemRegReg(TEST, MemReg_Reg, data_size_); break;
case 0x86: MemRegReg(XCHG, Reg_MemReg, DataSize::Byte); break;
case 0x87: MemRegReg(XCHG, Reg_MemReg, data_size_); break;
case 0x88: MemRegReg(MOV, MemReg_Reg, DataSize::Byte); break;
case 0x89: MemRegReg(MOV, MemReg_Reg, data_size_); break;
case 0x8a: MemRegReg(MOV, Reg_MemReg, DataSize::Byte); break;
case 0x8b: MemRegReg(MOV, Reg_MemReg, data_size_); break;
case 0x8c: MemRegReg(MOV, MemReg_Seg, DataSize::Word); break;
case 0x8d: MemRegReg(LEA, Reg_MemReg, data_size_); break;
case 0x8e: MemRegReg(MOV, Seg_MemReg, DataSize::Word); break;
case 0x8f: MemRegReg(POP, MemRegSingleOperand, data_size_); break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0x90: Complete(NOP, None, None, DataSize::None); break; // Or XCHG AX, AX?
case 0x91: Complete(XCHG, eAX, eCX, data_size_); break;
case 0x92: Complete(XCHG, eAX, eDX, data_size_); break;
case 0x93: Complete(XCHG, eAX, eBX, data_size_); break;
case 0x94: Complete(XCHG, eAX, eSP, data_size_); break;
case 0x95: Complete(XCHG, eAX, eBP, data_size_); break;
case 0x96: Complete(XCHG, eAX, eSI, data_size_); break;
case 0x97: Complete(XCHG, eAX, eDI, data_size_); break;
Eliminate redundant CMPSD, CDQ, CWDE. Also removes IBTS for now, as I'm unclear where it should sit in the opcode map.
2022-03-12 17:24:44 +00:00
case 0x98: Complete(CBW, eAX, AH, data_size_); break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0x99: Complete(CWD, eAX, eDX, data_size_); break;
Clarify, unify and correct decoding and encoding of [CALL/RET/JMP][near/far/relative/absolute].
2022-03-09 21:48:06 +00:00
case 0x9a: Far(CALLfar); break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0x9b: Complete(WAIT, None, None, DataSize::None); break;
case 0x9c: Complete(PUSHF, None, None, data_size_); break;
case 0x9d: Complete(POPF, None, None, data_size_); break;
case 0x9e: Complete(SAHF, None, None, DataSize::Byte); break;
case 0x9f: Complete(LAHF, None, None, DataSize::Byte); break;
Fixed: INs and OUTs remain single byte.
2022-03-09 15:51:16 +00:00
case 0xa0: RegAddr(MOV, eAX, DataSize::Byte, data_size(address_size_)); break;
case 0xa1: RegAddr(MOV, eAX, data_size_, data_size(address_size_)); break;
case 0xa2: AddrReg(MOV, eAX, DataSize::Byte, data_size(address_size_)); break;
case 0xa3: AddrReg(MOV, eAX, data_size_, data_size(address_size_)); break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0xa4: Complete(MOVS, None, None, DataSize::Byte); break;
case 0xa5: Complete(MOVS, None, None, data_size_); break;
case 0xa6: Complete(CMPS, None, None, DataSize::Byte); break;
case 0xa7: Complete(CMPS, None, None, data_size_); break;
case 0xa8: RegData(TEST, eAX, DataSize::Byte); break;
case 0xa9: RegData(TEST, eAX, data_size_); break;
case 0xaa: Complete(STOS, None, None, DataSize::Byte); break;
case 0xab: Complete(STOS, None, None, data_size_); break;
case 0xac: Complete(LODS, None, None, DataSize::Byte); break;
case 0xad: Complete(LODS, None, None, data_size_); break;
case 0xae: Complete(SCAS, None, None, DataSize::Byte); break;
case 0xaf: Complete(SCAS, None, None, data_size_); break;
case 0xb0: RegData(MOV, eAX, DataSize::Byte); break;
case 0xb1: RegData(MOV, eCX, DataSize::Byte); break;
case 0xb2: RegData(MOV, eDX, DataSize::Byte); break;
case 0xb3: RegData(MOV, eBX, DataSize::Byte); break;
case 0xb4: RegData(MOV, AH, DataSize::Byte); break;
case 0xb5: RegData(MOV, CH, DataSize::Byte); break;
case 0xb6: RegData(MOV, DH, DataSize::Byte); break;
case 0xb7: RegData(MOV, BH, DataSize::Byte); break;
case 0xb8: RegData(MOV, eAX, data_size_); break;
case 0xb9: RegData(MOV, eCX, data_size_); break;
case 0xba: RegData(MOV, eDX, data_size_); break;
case 0xbb: RegData(MOV, eBX, data_size_); break;
case 0xbc: RegData(MOV, eSP, data_size_); break;
case 0xbd: RegData(MOV, eBP, data_size_); break;
case 0xbe: RegData(MOV, eSI, data_size_); break;
case 0xbf: RegData(MOV, eDI, data_size_); break;
Adds the missing shift group segues at c0 and c1.
2022-03-07 14:18:59 +00:00
case 0xc0: case 0xc1:
RequiresMin(i80186);
ShiftGroup();
source_ = Source::Immediate;
Fix shift group operand size.
2022-03-09 14:33:25 +00:00
operand_size_ = DataSize::Byte;
Adds the missing shift group segues at c0 and c1.
2022-03-07 14:18:59 +00:00
break;
Clarify, unify and correct decoding and encoding of [CALL/RET/JMP][near/far/relative/absolute].
2022-03-09 21:48:06 +00:00
case 0xc2: RegData(RETnear, None, data_size_); break;
case 0xc3: Complete(RETnear, None, None, DataSize::None); break;
case 0xc4: MemRegReg(LES, Reg_MemReg, data_size_); break;
case 0xc5: MemRegReg(LDS, Reg_MemReg, data_size_); break;
case 0xc6: MemRegReg(MOV, MemRegMOV, DataSize::Byte); break;
case 0xc7: MemRegReg(MOV, MemRegMOV, data_size_); break;
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
case 0xc8:
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80186);
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
Displacement16Operand8(ENTER);
break;
case 0xc9:
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
RequiresMin(i80186);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Complete(LEAVE, None, None, DataSize::None);
Attempts decoding of the 80186 set.
2022-02-09 22:51:48 +00:00
break;
Clarify, unify and correct decoding and encoding of [CALL/RET/JMP][near/far/relative/absolute].
2022-03-09 21:48:06 +00:00
case 0xca: RegData(RETfar, None, data_size_); break;
case 0xcb: Complete(RETfar, None, None, DataSize::DWord); break;
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
Eliminate INT3 special case.
2022-03-11 19:03:46 +00:00
case 0xcc:
// Encode INT3 as though it were INT with an
// immediate operand of 3.
Complete(INT, Immediate, None, DataSize::Byte);
operand_ = 3;
break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0xcd: RegData(INT, None, DataSize::Byte); break;
case 0xce: Complete(INTO, None, None, DataSize::None); break;
case 0xcf: Complete(IRET, None, None, DataSize::None); break;
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
Adds the missing shift group segues at c0 and c1.
2022-03-07 14:18:59 +00:00
case 0xd0: case 0xd1:
ShiftGroup();
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
source_ = Source::Immediate;
Marks intent for operand/displacement.
2021-01-09 03:45:27 +00:00
operand_ = 1;
Adds the missing shift group segues at c0 and c1.
2022-03-07 14:18:59 +00:00
break;
case 0xd2: case 0xd3:
ShiftGroup();
Albeit that it requires nuanced shift/roll semantics, eliminates `CL` constant. Shifts and rolls are already slightly semantically special for being undefined for values greater than 8/16/32 — i.e. in some implementations they don't even use the entirety of CL, just the low five bits. Which makes me feel a little better. The upside of no ambiguity between eCX size 1 and CL justifies the trade.
2022-02-20 22:52:19 +00:00
source_ = Source::eCX;
Adds the missing shift group segues at c0 and c1.
2022-03-07 14:18:59 +00:00
break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0xd4: RegData(AAM, eAX, DataSize::Byte); break;
case 0xd5: RegData(AAD, eAX, DataSize::Byte); break;
Add notes on all missing opcodes.
2022-03-05 22:16:13 +00:00
// Unused: 0xd6.
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0xd7: Complete(XLAT, None, None, DataSize::Byte); break;
case 0xd8: MemRegReg(ESC, MemReg_Reg, DataSize::None); break;
case 0xd9: MemRegReg(ESC, MemReg_Reg, DataSize::None); break;
case 0xda: MemRegReg(ESC, MemReg_Reg, DataSize::None); break;
case 0xdb: MemRegReg(ESC, MemReg_Reg, DataSize::None); break;
case 0xdc: MemRegReg(ESC, MemReg_Reg, DataSize::None); break;
case 0xdd: MemRegReg(ESC, MemReg_Reg, DataSize::None); break;
case 0xde: MemRegReg(ESC, MemReg_Reg, DataSize::None); break;
case 0xdf: MemRegReg(ESC, MemReg_Reg, DataSize::None); break;
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
case 0xe0: Displacement(LOOPNE, DataSize::Byte); break;
case 0xe1: Displacement(LOOPE, DataSize::Byte); break;
case 0xe2: Displacement(LOOP, DataSize::Byte); break;
Add missing substitutions.
2023-09-19 18:00:27 +00:00
case 0xe3: Displacement(JCXZ, DataSize::Byte); break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Fixed: INs and OUTs remain single byte.
2022-03-09 15:51:16 +00:00
case 0xe4: RegAddr(IN, eAX, DataSize::Byte, DataSize::Byte); break;
case 0xe5: RegAddr(IN, eAX, data_size_, DataSize::Byte); break;
case 0xe6: AddrReg(OUT, eAX, DataSize::Byte, DataSize::Byte); break;
case 0xe7: AddrReg(OUT, eAX, data_size_, DataSize::Byte); break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Clarify, unify and correct decoding and encoding of [CALL/RET/JMP][near/far/relative/absolute].
2022-03-09 21:48:06 +00:00
case 0xe8: Displacement(CALLrel, data_size_); break;
case 0xe9: Displacement(JMPrel, data_size_); break;
case 0xea: Far(JMPfar); break;
case 0xeb: Displacement(JMPrel, DataSize::Byte); break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0xec: Complete(IN, eDX, eAX, DataSize::Byte); break;
case 0xed: Complete(IN, eDX, eAX, data_size_); break;
case 0xee: Complete(OUT, eAX, eDX, DataSize::Byte); break;
case 0xef: Complete(OUT, eAX, eDX, data_size_); break;
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
Starts adjusting the concept of a `Source`.
2022-02-17 16:32:09 +00:00
case 0xf0: lock_ = true; break;
Add notes on all missing opcodes.
2022-03-05 22:16:13 +00:00
// Unused: 0xf1
Starts adjusting the concept of a `Source`.
2022-02-17 16:32:09 +00:00
case 0xf2: repetition_ = Repetition::RepNE; break;
case 0xf3: repetition_ = Repetition::RepE; break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0xf4: Complete(HLT, None, None, DataSize::None); break;
case 0xf5: Complete(CMC, None, None, DataSize::None); break;
case 0xf6: MemRegReg(Invalid, MemRegTEST_to_IDIV, DataSize::Byte); break;
case 0xf7: MemRegReg(Invalid, MemRegTEST_to_IDIV, data_size_); break;
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0xf8: Complete(CLC, None, None, DataSize::None); break;
case 0xf9: Complete(STC, None, None, DataSize::None); break;
case 0xfa: Complete(CLI, None, None, DataSize::None); break;
case 0xfb: Complete(STI, None, None, DataSize::None); break;
case 0xfc: Complete(CLD, None, None, DataSize::None); break;
case 0xfd: Complete(STD, None, None, DataSize::None); break;
Finally runs into the wall of trying to merge operands and offsets.
2021-01-04 01:08:13 +00:00
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0xfe: MemRegReg(Invalid, MemRegINC_DEC, DataSize::Byte); break;
case 0xff: MemRegReg(Invalid, MemRegINC_to_PUSH, data_size_); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
}
}
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
// MARK: - Additional F page of instructions.
Add instruction length limits.
2022-03-11 01:47:56 +00:00
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
if(phase_ == Phase::InstructionPageF && source != end) {
// Update the instruction acquired.
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
const uint8_t instr = *source;
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
++source;
++consumed_;
// NB: to reach here, the instruction set must be at least
// that of an 80286.
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
switch(instr) {
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
default: undefined();
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0x00: MemRegReg(Invalid, MemRegSLDT_to_VERW, data_size_); break;
case 0x01: MemRegReg(Invalid, MemRegSGDT_to_LMSW, data_size_); break;
case 0x02: MemRegReg(LAR, Reg_MemReg, data_size_); break;
case 0x03: MemRegReg(LSL, Reg_MemReg, data_size_); break;
Attempts a full decoding of the 80286 instruction set.
2022-02-10 22:13:50 +00:00
case 0x05:
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
Requires(i80286);
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
Complete(LOADALL, None, None, DataSize::None);
Attempts a full decoding of the 80286 instruction set.
2022-02-10 22:13:50 +00:00
break;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case 0x06: Complete(CLTS, None, None, DataSize::Byte); break;
Add notes on all missing opcodes.
2022-03-05 22:16:13 +00:00
Adds special test/control/debug MOVs. This'll do; it's not ideal but avoids bloating up the `Source` enum.
2022-03-07 22:04:05 +00:00
case 0x20:
RequiresMin(i80386);
MemRegReg(MOVfromCr, Reg_MemReg, DataSize::DWord);
break;
case 0x21:
RequiresMin(i80386);
MemRegReg(MOVfromDr, Reg_MemReg, DataSize::DWord);
break;
case 0x22:
RequiresMin(i80386);
MemRegReg(MOVtoCr, Reg_MemReg, DataSize::DWord);
break;
case 0x23:
RequiresMin(i80386);
MemRegReg(MOVtoDr, Reg_MemReg, DataSize::DWord);
break;
case 0x24:
RequiresMin(i80386);
MemRegReg(MOVfromTr, Reg_MemReg, DataSize::DWord);
break;
case 0x26:
RequiresMin(i80386);
MemRegReg(MOVtoTr, Reg_MemReg, DataSize::DWord);
break;
Add notes on all missing opcodes.
2022-03-05 22:16:13 +00:00
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
case 0x70: RequiresMin(i80386); Displacement(JO, data_size_); break;
case 0x71: RequiresMin(i80386); Displacement(JNO, data_size_); break;
case 0x72: RequiresMin(i80386); Displacement(JB, data_size_); break;
case 0x73: RequiresMin(i80386); Displacement(JNB, data_size_); break;
Agree that JZ/JNZ are clearer (for me) of the synonyms.
2023-09-19 17:38:08 +00:00
case 0x74: RequiresMin(i80386); Displacement(JZ, data_size_); break;
case 0x75: RequiresMin(i80386); Displacement(JNZ, data_size_); break;
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
case 0x76: RequiresMin(i80386); Displacement(JBE, data_size_); break;
case 0x77: RequiresMin(i80386); Displacement(JNBE, data_size_); break;
case 0x78: RequiresMin(i80386); Displacement(JS, data_size_); break;
case 0x79: RequiresMin(i80386); Displacement(JNS, data_size_); break;
case 0x7a: RequiresMin(i80386); Displacement(JP, data_size_); break;
case 0x7b: RequiresMin(i80386); Displacement(JNP, data_size_); break;
case 0x7c: RequiresMin(i80386); Displacement(JL, data_size_); break;
case 0x7d: RequiresMin(i80386); Displacement(JNL, data_size_); break;
case 0x7e: RequiresMin(i80386); Displacement(JLE, data_size_); break;
case 0x7f: RequiresMin(i80386); Displacement(JNLE, data_size_); break;
Add notes on all missing opcodes.
2022-03-05 22:16:13 +00:00
Add the SETs.
2022-03-07 15:32:34 +00:00
#define Set(x) \
RequiresMin(i80386); \
MemRegReg(SET##x, MemRegSingleOperand, DataSize::Byte);
case 0x90: Set(O); break;
case 0x91: Set(NO); break;
case 0x92: Set(B); break;
case 0x93: Set(NB); break;
case 0x94: Set(Z); break;
case 0x95: Set(NZ); break;
case 0x96: Set(BE); break;
case 0x97: Set(NBE); break;
case 0x98: Set(S); break;
case 0x99: Set(NS); break;
case 0x9a: Set(P); break;
case 0x9b: Set(NP); break;
case 0x9c: Set(L); break;
case 0x9d: Set(NL); break;
case 0x9e: Set(LE); break;
case 0x9f: Set(NLE); break;
#undef Set
Add notes on all missing opcodes.
2022-03-05 22:16:13 +00:00
Also 'easy': LSS, LFS, LGS. Though perhaps I'm off on LES and LDS?
2022-03-06 14:28:43 +00:00
case 0xa0: RequiresMin(i80386); Complete(PUSH, FS, None, data_size_); break;
case 0xa1: RequiresMin(i80386); Complete(POP, FS, None, data_size_); break;
Add BT, BTS, BTR, BTC, BSF, BSR.
2022-03-07 21:23:25 +00:00
case 0xa3: RequiresMin(i80386); MemRegReg(BT, MemReg_Reg, data_size_); break;
Adds special test/control/debug MOVs. This'll do; it's not ideal but avoids bloating up the `Source` enum.
2022-03-07 22:04:05 +00:00
case 0xa4:
RequiresMin(i80386);
MemRegReg(SHLDimm, Reg_MemReg, data_size_);
operand_size_ = DataSize::Byte;
break;
case 0xa5:
RequiresMin(i80386);
MemRegReg(SHLDCL, MemReg_Reg, data_size_);
break;
Also 'easy': LSS, LFS, LGS. Though perhaps I'm off on LES and LDS?
2022-03-06 14:28:43 +00:00
case 0xa8: RequiresMin(i80386); Complete(PUSH, GS, None, data_size_); break;
case 0xa9: RequiresMin(i80386); Complete(POP, GS, None, data_size_); break;
Add BT, BTS, BTR, BTC, BSF, BSR.
2022-03-07 21:23:25 +00:00
case 0xab: RequiresMin(i80386); MemRegReg(BTS, MemReg_Reg, data_size_); break;
Adds special test/control/debug MOVs. This'll do; it's not ideal but avoids bloating up the `Source` enum.
2022-03-07 22:04:05 +00:00
case 0xac:
RequiresMin(i80386);
MemRegReg(SHRDimm, Reg_MemReg, data_size_);
operand_size_ = DataSize::Byte;
break;
case 0xad:
RequiresMin(i80386);
MemRegReg(SHRDCL, MemReg_Reg, data_size_);
break;
Introduce additional forms of IMUL.
2022-03-07 14:05:22 +00:00
case 0xaf:
RequiresMin(i80386);
MemRegReg(IMUL_2, Reg_MemReg, data_size_);
break;
Flag up TODOs, for easier in-editor navigation.
2022-03-05 22:48:01 +00:00
Also 'easy': LSS, LFS, LGS. Though perhaps I'm off on LES and LDS?
2022-03-06 14:28:43 +00:00
case 0xb2: RequiresMin(i80386); MemRegReg(LSS, Reg_MemReg, data_size_); break;
Add BT, BTS, BTR, BTC, BSF, BSR.
2022-03-07 21:23:25 +00:00
case 0xb3: RequiresMin(i80386); MemRegReg(BTR, MemReg_Reg, data_size_); break;
Also 'easy': LSS, LFS, LGS. Though perhaps I'm off on LES and LDS?
2022-03-06 14:28:43 +00:00
case 0xb4: RequiresMin(i80386); MemRegReg(LFS, Reg_MemReg, data_size_); break;
case 0xb5: RequiresMin(i80386); MemRegReg(LGS, Reg_MemReg, data_size_); break;
Add MOVZX, MOVSX.
2022-03-07 21:25:44 +00:00
case 0xb6:
RequiresMin(i80386);
MemRegReg(MOVZX, Reg_MemReg, DataSize::Byte);
break;
case 0xb7:
RequiresMin(i80386);
MemRegReg(MOVZX, Reg_MemReg, DataSize::Word);
break;
Take a stab at group 8.
2022-03-07 21:34:56 +00:00
case 0xba: RequiresMin(i80386); MemRegReg(Invalid, MemRegBT_to_BTC, data_size_); break;
case 0xbb: RequiresMin(i80386); MemRegReg(BTC, MemReg_Reg, data_size_); break;
case 0xbc: RequiresMin(i80386); MemRegReg(BSF, MemReg_Reg, data_size_); break;
case 0xbd: RequiresMin(i80386); MemRegReg(BSR, MemReg_Reg, data_size_); break;
Add MOVZX, MOVSX.
2022-03-07 21:25:44 +00:00
case 0xbe:
RequiresMin(i80386);
MemRegReg(MOVSX, Reg_MemReg, DataSize::Byte);
break;
case 0xbf:
RequiresMin(i80386);
MemRegReg(MOVSX, Reg_MemReg, DataSize::Word);
break;
Introduces the easy F page instructions.
2022-02-10 14:35:05 +00:00
}
}
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
#undef Requires
#undef RequiresMin
Adds the missing shift group segues at c0 and c1.
2022-03-07 14:18:59 +00:00
#undef ShiftGroup
#undef Displacement16Operand8
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
#undef Far
Add the two immediate PUSHes.
2022-03-06 19:28:41 +00:00
#undef Immediate
#undef Displacement
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
#undef MemRegReg
#undef AddrReg
#undef RegAddr
#undef RegData
#undef Complete
#undef SetOpSrcDestSize
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// MARK: - ModRegRM byte, if any.
if(phase_ == Phase::ModRegRM && source != end) {
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
const uint8_t mod = *source >> 6; // i.e. mode.
const uint8_t reg = (*source >> 3) & 7; // i.e. register.
const uint8_t rm = *source & 7; // i.e. register/memory.
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 19:39:49 +00:00
bool expects_sib = false;
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
++source;
++consumed_;
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
Source memreg;
Fix $8e data size, add $8c.
2022-03-05 22:00:48 +00:00
Resolve TODO.
2022-03-11 18:10:44 +00:00
// These tables are fairly redundant due to the register ordering within
// Source, but act to improve readability and permit further Source
// reordering in the future.
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
constexpr Source reg_table[8] = {
Source::eAX, Source::eCX, Source::eDX, Source::eBX,
Source::eSPorAH, Source::eBPorCH, Source::eSIorDH, Source::eDIorBH,
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
};
Fix $8e data size, add $8c.
2022-03-05 22:00:48 +00:00
constexpr Source seg_table[6] = {
Source::ES, Source::CS, Source::SS, Source::DS, Source::FS, Source::GS
};
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 19:39:49 +00:00
// Mode 3 is the same regardless of 16/32-bit mode. So deal with that up front.
if(mod == 3) {
// Other operand is just a register.
memreg = reg_table[rm];
// LES, LDS, etc accept a memory argument only, not a register.
if(
operation_ == Operation::LES ||
operation_ == Operation::LDS ||
operation_ == Operation::LGS ||
operation_ == Operation::LSS ||
operation_ == Operation::LFS) {
undefined();
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
}
Fully handle rm = 6, mod = 0.
2023-09-16 02:08:20 +00:00
} else if(rm == 6 && mod == 0) {
// There's no BP direct; BP with ostensibly no offset means 'direct address' mode.
displacement_size_ = data_size(address_size_);
memreg = Source::DirectAddress;
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 19:39:49 +00:00
} else {
const DataSize sizes[] = {
DataSize::None,
DataSize::Byte,
Fix RegAddr/AddrRegs and group 2 decoding.
2022-03-09 13:38:34 +00:00
data_size(address_size_)
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 19:39:49 +00:00
};
displacement_size_ = sizes[mod];
memreg = Source::Indirect;
Extend SIB test, correct decoder.
2022-03-08 20:03:37 +00:00
if(address_size_ == AddressSize::b32) {
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 19:39:49 +00:00
// 32-bit decoding: the range of potential indirections is expanded,
// and may segue into obtaining a SIB.
sib_ = ScaleIndexBase(0, Source::None, reg_table[rm]);
expects_sib = rm == 4; // Indirect via eSP isn't directly supported; it's the
// escape indicator for reading a SIB.
} else {
// Classic 16-bit decoding: mode picks a displacement size,
// and a few fixed index+base pairs are defined.
Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase.
2022-02-21 16:45:46 +00:00
constexpr ScaleIndexBase rm_table[8] = {
Capture default segments, fix base/index confusion.
2023-09-22 15:07:09 +00:00
ScaleIndexBase(0, Source::eSI, Source::eBX),
ScaleIndexBase(0, Source::eDI, Source::eBX),
ScaleIndexBase(0, Source::eSI, Source::eBP),
ScaleIndexBase(0, Source::eDI, Source::eBP),
ScaleIndexBase(0, Source::eSI, Source::None),
ScaleIndexBase(0, Source::eDI, Source::None),
ScaleIndexBase(0, Source::eBP, Source::None),
ScaleIndexBase(0, Source::eBX, Source::None),
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
};
Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase.
2022-02-21 16:45:46 +00:00
sib_ = rm_table[rm];
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 19:39:49 +00:00
}
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
}
switch(modregrm_format_) {
case ModRegRMFormat::Reg_MemReg:
case ModRegRMFormat::MemReg_Reg: {
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
if(modregrm_format_ == ModRegRMFormat::Reg_MemReg) {
source_ = memreg;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
destination_ = reg_table[reg];
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
} else {
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
source_ = reg_table[reg];
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
destination_ = memreg;
}
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
} break;
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
case ModRegRMFormat::MemRegTEST_to_IDIV:
source_ = destination_ = memreg;
switch(reg) {
Attempts a full decoding of the 80286 instruction set.
2022-02-10 22:13:50 +00:00
default: undefined();
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
Eliminate redundant [space][tab] pairs.
2023-05-12 18:14:45 +00:00
case 0: operation_ = Operation::TEST; break;
case 2: operation_ = Operation::NOT; break;
case 3: operation_ = Operation::NEG; break;
case 4: operation_ = Operation::MUL; break;
case 5: operation_ = Operation::IMUL_1; break;
case 6: operation_ = Operation::DIV; break;
case 7: operation_ = Operation::IDIV; break;
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
}
break;
Fix $8e data size, add $8c.
2022-03-05 22:00:48 +00:00
case ModRegRMFormat::Seg_MemReg:
case ModRegRMFormat::MemReg_Seg:
// The 16-bit chips have four segment registers;
// the 80386 onwards has six.
if(!is_32bit(model) && reg > 3) {
undefined();
} else if(reg > 5) {
Attempts a full decoding of the 80286 instruction set.
2022-02-10 22:13:50 +00:00
undefined();
Decodes 8e.
2021-01-08 02:36:05 +00:00
}
Fix $8e data size, add $8c.
2022-03-05 22:00:48 +00:00
if(modregrm_format_ == ModRegRMFormat::Seg_MemReg) {
source_ = memreg;
destination_ = seg_table[reg];
// 80286 and later disallow MOV to CS.
if(model >= Model::i80286 && destination_ == Source::CS) {
undefined();
}
} else {
source_ = seg_table[reg];
destination_ = memreg;
}
break;
Decodes 8e.
2021-01-08 02:36:05 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
case ModRegRMFormat::MemRegROL_to_SAR:
destination_ = memreg;
switch(reg) {
Eliminate redundant [space][tab] pairs.
2023-05-12 18:14:45 +00:00
default: undefined();
case 0: operation_ = Operation::ROL; break;
case 1: operation_ = Operation::ROR; break;
case 2: operation_ = Operation::RCL; break;
case 3: operation_ = Operation::RCR; break;
case 4: operation_ = Operation::SAL; break;
case 5: operation_ = Operation::SHR; break;
case 7: operation_ = Operation::SAR; break;
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
}
break;
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
case ModRegRMFormat::MemRegINC_DEC:
source_ = destination_ = memreg;
switch(reg) {
Eliminate redundant [space][tab] pairs.
2023-05-12 18:14:45 +00:00
default: undefined();
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
case 0: operation_ = Operation::INC; break;
case 1: operation_ = Operation::DEC; break;
}
break;
case ModRegRMFormat::MemRegINC_to_PUSH:
source_ = destination_ = memreg;
switch(reg) {
Eliminate redundant [space][tab] pairs.
2023-05-12 18:14:45 +00:00
default: undefined();
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
Clarify, unify and correct decoding and encoding of [CALL/RET/JMP][near/far/relative/absolute].
2022-03-09 21:48:06 +00:00
case 0: operation_ = Operation::INC; break;
case 1: operation_ = Operation::DEC; break;
case 2: operation_ = Operation::CALLabs; break;
case 3: operation_ = Operation::CALLfar; break;
case 4: operation_ = Operation::JMPabs; break;
case 5: operation_ = Operation::JMPfar; break;
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
case 6: operation_ = Operation::PUSH; break;
}
break;
Add the SETs.
2022-03-07 15:32:34 +00:00
case ModRegRMFormat::MemRegSingleOperand:
Fills in 8f, c2, c3, ca and cb. Also switches to RETN and RETF for near/far RET as this seems idiomatic.
2021-01-07 02:18:24 +00:00
source_ = destination_ = memreg;
if(reg != 0) {
Attempts a full decoding of the 80286 instruction set.
2022-02-10 22:13:50 +00:00
undefined();
Fills in 8f, c2, c3, ca and cb. Also switches to RETN and RETF for near/far RET as this seems idiomatic.
2021-01-07 02:18:24 +00:00
}
break;
case ModRegRMFormat::MemRegMOV:
source_ = Source::Immediate;
destination_ = memreg;
operand_size_ = operation_size_;
break;
Implements 80 and 81.
2021-01-09 03:50:59 +00:00
case ModRegRMFormat::MemRegADD_to_CMP:
Clarify sign extension availability.
2022-03-05 21:44:26 +00:00
case ModRegRMFormat::MemRegADD_to_CMP_SignExtend:
source_ = Source::Immediate;
Implements 80 and 81.
2021-01-09 03:50:59 +00:00
destination_ = memreg;
Clarify sign extension availability.
2022-03-05 21:44:26 +00:00
operand_size_ = (modregrm_format_ == ModRegRMFormat::MemRegADD_to_CMP_SignExtend) ? DataSize::Byte : operation_size_;
sign_extend_ = true; // Will be effective only if modregrm_format_ == ModRegRMFormat::MemRegADD_to_CMP_SignExtend.
Implements 80 and 81.
2021-01-09 03:50:59 +00:00
switch(reg) {
default: operation_ = Operation::ADD; break;
case 1: operation_ = Operation::OR; break;
case 2: operation_ = Operation::ADC; break;
case 3: operation_ = Operation::SBB; break;
case 4: operation_ = Operation::AND; break;
case 5: operation_ = Operation::SUB; break;
case 6: operation_ = Operation::XOR; break;
case 7: operation_ = Operation::CMP; break;
}
break;
Attempts a full decoding of the 80286 instruction set.
2022-02-10 22:13:50 +00:00
case ModRegRMFormat::MemRegSLDT_to_VERW:
destination_ = source_ = memreg;
switch(reg) {
default: undefined();
Eliminate redundant [space][tab] pairs.
2023-05-12 18:14:45 +00:00
case 0: operation_ = Operation::SLDT; break;
case 1: operation_ = Operation::STR; break;
case 2: operation_ = Operation::LLDT; break;
case 3: operation_ = Operation::LTR; break;
case 4: operation_ = Operation::VERR; break;
case 5: operation_ = Operation::VERW; break;
Attempts a full decoding of the 80286 instruction set.
2022-02-10 22:13:50 +00:00
}
break;
case ModRegRMFormat::MemRegSGDT_to_LMSW:
destination_ = source_ = memreg;
switch(reg) {
default: undefined();
Eliminate redundant [space][tab] pairs.
2023-05-12 18:14:45 +00:00
case 0: operation_ = Operation::SGDT; break;
case 1: operation_ = Operation::SIDT; break;
case 2: operation_ = Operation::LGDT; break;
case 3: operation_ = Operation::LIDT; break;
case 4: operation_ = Operation::SMSW; break;
case 6: operation_ = Operation::LMSW; break;
Attempts a full decoding of the 80286 instruction set.
2022-02-10 22:13:50 +00:00
}
break;
Take a stab at group 8.
2022-03-07 21:34:56 +00:00
case ModRegRMFormat::MemRegBT_to_BTC:
destination_ = memreg;
source_ = Source::Immediate;
operand_size_ = DataSize::Byte;
switch(reg) {
default: undefined();
case 4: operation_ = Operation::BT; break;
case 5: operation_ = Operation::BTS; break;
case 6: operation_ = Operation::BTR; break;
case 7: operation_ = Operation::BTC; break;
}
break;
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
default: assert(false);
}
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
Correct SIB test.
2022-04-27 23:53:15 +00:00
if(expects_sib && (source_ == Source::Indirect || destination_ == Source::Indirect)) {
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 19:39:49 +00:00
phase_ = Phase::ScaleIndexBase;
} else {
phase_ = (displacement_size_ != DataSize::None || operand_size_ != DataSize::None) ? Phase::DisplacementOrOperand : Phase::ReadyToPost;
}
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
}
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 21:06:02 +00:00
#undef undefined
Adds a presently-unreachable step for SIB consumption.
2022-02-19 23:00:27 +00:00
// MARK: - ScaleIndexBase
if(phase_ == Phase::ScaleIndexBase && source != end) {
sib_ = *source;
++source;
++consumed_;
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 19:39:49 +00:00
Add test for switch to Source::IndirectNoBase.
2022-03-10 20:45:56 +00:00
// Potentially record the lack of a base.
if(displacement_size_ == DataSize::None && (uint8_t(sib_)&7) == 5) {
source_ = (source_ == Source::Indirect) ? Source::IndirectNoBase : source_;
destination_ = (destination_ == Source::Indirect) ? Source::IndirectNoBase : destination_;
}
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 19:39:49 +00:00
phase_ = (displacement_size_ != DataSize::None || operand_size_ != DataSize::None) ? Phase::DisplacementOrOperand : Phase::ReadyToPost;
Adds a presently-unreachable step for SIB consumption.
2022-02-19 23:00:27 +00:00
}
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// MARK: - Displacement and operand.
Add instruction length limits.
2022-03-11 01:47:56 +00:00
if(phase_ == Phase::DisplacementOrOperand) {
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
const auto required_bytes = int(byte_size(displacement_size_) + byte_size(operand_size_));
Proceeds to three instructions correctly decoded. 'Wow'.
2021-01-03 22:03:50 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
const int outstanding_bytes = required_bytes - operand_bytes_;
const int bytes_to_consume = std::min(int(end - source), outstanding_bytes);
Marks intent for operand/displacement.
2021-01-09 03:45:27 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
for(int c = 0; c < bytes_to_consume; c++) {
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
inward_data_ |= decltype(inward_data_)(source[0]) << next_inward_data_shift_;
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
++source;
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
next_inward_data_shift_ += 8;
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
}
Marks intent for operand/displacement.
2021-01-09 03:45:27 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
consumed_ += bytes_to_consume;
operand_bytes_ += bytes_to_consume;
Marks intent for operand/displacement.
2021-01-09 03:45:27 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
if(bytes_to_consume == outstanding_bytes) {
phase_ = Phase::ReadyToPost;
Adds operand/displacement capture. This gets unit test as far as a disagreement over how to handle bad 0xc4 suffixes.
2021-01-11 03:55:25 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
switch(displacement_size_) {
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
case DataSize::None: displacement_ = 0; break;
case DataSize::Byte: displacement_ = int8_t(inward_data_); break;
case DataSize::Word: displacement_ = int16_t(inward_data_); break;
case DataSize::DWord: displacement_ = int32_t(inward_data_); break;
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
}
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
inward_data_ >>= bit_size(displacement_size_);
// Use inequality of sizes as a test for necessary sign extension.
if(operand_size_ == data_size_ || !sign_extend_) {
operand_ = decltype(operand_)(inward_data_);
} else {
switch(operand_size_) {
case DataSize::None: operand_ = 0; break;
case DataSize::Byte: operand_ = decltype(operand_)(int8_t(inward_data_)); break;
case DataSize::Word: operand_ = decltype(operand_)(int16_t(inward_data_)); break;
case DataSize::DWord: operand_ = decltype(operand_)(int32_t(inward_data_)); break;
}
}
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
} else {
// Provide a genuine measure of further bytes required.
Template `Instruction` on its content size.
2022-02-21 17:36:03 +00:00
return std::make_pair(-(outstanding_bytes - bytes_to_consume), InstructionT());
Proceeds to three instructions correctly decoded. 'Wow'.
2021-01-03 22:03:50 +00:00
}
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
}
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// MARK: - Check for completion.
Attempts to consolidate source/destination ordering.
2021-01-03 22:28:29 +00:00
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
if(phase_ == Phase::ReadyToPost) {
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
const auto result = std::make_pair(
consumed_,
Template `Instruction` on its content size.
2022-02-21 17:36:03 +00:00
InstructionT(
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
operation_,
source_,
destination_,
Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase.
2022-02-21 16:45:46 +00:00
sib_,
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
lock_,
This is normatively called the address size.
2022-02-21 20:52:16 +00:00
address_size_,
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
segment_override_,
repetition_,
Simplify address size semantics. Since it'll no longer be a mode-dependant toggle, but a fully-retained value.
2022-03-01 22:29:26 +00:00
DataSize(operation_size_),
Adapts existing opcodes for 32-bit parsing.
2022-03-05 18:52:07 +00:00
static_cast<typename InstructionT::DisplacementT>(displacement_),
Incorporate length into `Instruction`.
2022-03-10 12:12:12 +00:00
static_cast<typename InstructionT::ImmediateT>(operand_),
consumed_
)
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
);
Attempts to consolidate source/destination ordering.
2021-01-03 22:28:29 +00:00
reset_parsing();
Proceeds to three instructions correctly decoded. 'Wow'.
2021-01-03 22:03:50 +00:00
return result;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
}
Add instruction length limits.
2022-03-11 01:47:56 +00:00
// Check for a too-long instruction.
Switch strategy on 8086 instruction lengths.
2022-03-11 14:48:26 +00:00
if(consumed_ == max_instruction_length) {
std::pair<int, InstructionT> result;
if(max_instruction_length == 65536) {
result = std::make_pair(consumed_, InstructionT(Operation::NOP, consumed_));
} else {
result = std::make_pair(consumed_, InstructionT());
}
Add instruction length limits.
2022-03-11 01:47:56 +00:00
reset_parsing();
return result;
}
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// i.e. not done yet.
Template `Instruction` on its content size.
2022-02-21 17:36:03 +00:00
return std::make_pair(0, InstructionT());
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
}
Switch `Decoder` into a template.
2022-02-21 17:21:57 +00:00
Sets up [ignored] memory and data size prefixes.
2022-03-03 01:23:35 +00:00
template <Model model> void Decoder<model>::set_32bit_protected_mode(bool enabled) {
if constexpr (!is_32bit(model)) {
assert(!enabled);
return;
}
if(enabled) {
default_address_size_ = address_size_ = AddressSize::b32;
default_data_size_ = data_size_ = DataSize::DWord;
} else {
default_address_size_ = address_size_ = AddressSize::b16;
default_data_size_ = data_size_ = DataSize::Word;
}
}
Switch `Decoder` into a template.
2022-02-21 17:21:57 +00:00
// Ensure all possible decoders are built.
template class InstructionSet::x86::Decoder<InstructionSet::x86::Model::i8086>;
template class InstructionSet::x86::Decoder<InstructionSet::x86::Model::i80186>;
template class InstructionSet::x86::Decoder<InstructionSet::x86::Model::i80286>;
template class InstructionSet::x86::Decoder<InstructionSet::x86::Model::i80386>;
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