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11,428 Commits 8 Branches 121 Tags 496 MiB
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Author SHA1 Message Date
Thomas Harte
0e4615564d Make bit masks easily testable; expand logging. 2024-03-13 14:31:26 -04:00
Thomas Harte
7aeea535a1 Reduce branchiness. 2024-03-13 11:02:52 -04:00
Thomas Harte
6b18d775ab Eliminate unused variables. 2024-03-12 21:53:26 -04:00
Thomas Harte
2ed031e440 Prepare for additional devices. 2024-03-12 21:23:22 -04:00
Thomas Harte
5d6bb11eb7 Add return. 2024-03-12 11:37:15 -04:00
Thomas Harte
c6b91559e1 Attempt to wire up timer interrupts. 2024-03-12 11:34:31 -04:00
Thomas Harte
6efc41ded7 Come to conclusion on R15; fix link values. 2024-03-12 10:42:09 -04:00
Thomas Harte
e9c5582fe1 Add note on ambiguity to be resolved. 2024-03-12 10:04:02 -04:00
Thomas Harte
8b3c0abe93 Take another swing at R15 as a destination. 2024-03-12 09:13:05 -04:00
Thomas Harte
a5ebac1b29 Add RISC OS 3.11 to catalogue, while bug hunting. 2024-03-11 22:19:14 -04:00
Thomas Harte
1ccfae885c Remove extra slashes. 2024-03-11 15:06:17 -04:00
Thomas Harte
971bfb2ecb Unify subtractions. 2024-03-11 14:52:48 -04:00
Thomas Harte
e7457461ba Reduce magic constants. 2024-03-11 14:49:03 -04:00
Thomas Harte
e8c1e8fd3f Fix RSB carry; unify set_pc. 2024-03-11 14:48:43 -04:00
Thomas Harte
ca779bc841 Expand test set. 2024-03-11 14:48:18 -04:00
Thomas Harte
a28c97c0de Simplify privilege test. 2024-03-11 12:14:00 -04:00
Thomas Harte
db49146efe Figure out what's going on with TEQ. 2024-03-11 09:51:09 -04:00
Thomas Harte
830d70d3aa Trust tests on immediate-opcode ROR 0; limit shift by register. 2024-03-10 23:38:31 -04:00
Thomas Harte
336292bc49 Further correct R15 as a destination. 2024-03-10 22:56:02 -04:00
Thomas Harte
bd62228cc6 The test set doesn't seem to do word rotation. 2024-03-10 22:40:37 -04:00
Thomas Harte
ccdd340c9a Reads also may or may not be aligned. *sigh* 2024-03-10 22:34:56 -04:00
Thomas Harte
0b42f5fb30 Make further test-set allowances. 2024-03-10 22:29:40 -04:00
Thomas Harte
e9e1db7a05 Change LDR writeback to destination. 2024-03-10 22:29:19 -04:00
Thomas Harte
21278d028c Correct unaligned accesses. 2024-03-10 21:56:19 -04:00
Thomas Harte
fbc273f114 Add invented model for tests. 2024-03-10 21:45:56 -04:00
Thomas Harte
06a5df029d Summarise failures. 2024-03-10 16:56:39 -04:00
Thomas Harte
e17700b495 Permit digression for 03110002, temporarily. 2024-03-10 14:47:02 -04:00
Thomas Harte
655b1e516c Test PSR and PC. 2024-03-10 14:14:18 -04:00
Thomas Harte
4e7a63f792 Do a de minimis checking of memory accesses. 2024-03-09 15:18:35 -05:00
Thomas Harte
a2896b9bd0 Test register values. 2024-03-09 15:11:12 -05:00
Thomas Harte
a4cf86268e Provide full access to stored registers. 2024-03-09 15:11:04 -05:00
Thomas Harte
d059e7c5d8 Disallow copying. 2024-03-09 15:10:55 -05:00
Thomas Harte
d6f882a8bb Integrate PC and PSR, guarantee invisible register values. 2024-03-09 14:59:44 -05:00
Thomas Harte
08f50f3eff Box in flags. 2024-03-08 23:01:29 -05:00
Thomas Harte
47f7340dfc Start hacking in some ARM tests. 2024-03-08 22:54:42 -05:00
Thomas Harte
fdef8901ab Double down on uint32_t. 2024-03-08 14:13:34 -05:00
Thomas Harte
ca1c3dc005 Add extra comments. 
To persuade myself in the future.
 2024-03-08 11:36:17 -05:00
Thomas Harte
9406a97141 Add some register switch tests. 2024-03-08 11:34:10 -05:00
Thomas Harte
a46ec4cffb Up clock rate to 24Mhz. 2024-03-07 22:16:58 -05:00
Thomas Harte
9bb5dc3c2b Fix inclusive range. 2024-03-07 19:40:34 -05:00
Thomas Harte
f6ea442606 Include various debugging detritus. 2024-03-07 14:28:39 -05:00
Thomas Harte
fa8fcd2218 Take another swing at popcount. 2024-03-07 14:28:31 -05:00
Thomas Harte
2a36d0fcbc Adjust user-mode test. 2024-03-07 14:00:38 -05:00
Thomas Harte
0e92885ed5 Fix ad hoc popcount; ARM does carry 'backwards'. 2024-03-07 13:27:41 -05:00
Thomas Harte
f5225b69e5 Add note to self. 2024-03-07 11:48:44 -05:00
Thomas Harte
15ee84b2eb Fix MUL ambiguity. 2024-03-07 11:45:39 -05:00
Thomas Harte
d380cecdb7 Add timers that count. 2024-03-07 11:39:26 -05:00
Thomas Harte
ae3cd924e8 Add a 2Mhz tick for timers. 2024-03-07 11:12:40 -05:00
Thomas Harte
a0f0f73bde Fix MOV as unconditional branch. 2024-03-07 10:31:26 -05:00
Thomas Harte
7cdceb7b4f Add a specific shout-out on prefetch abort, for debugging. 2024-03-07 10:23:46 -05:00