Thomas Harte
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7b164de6fd
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Reenables interrupts.
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2021-03-06 18:53:39 -05:00 |
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Thomas Harte
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24e68166c6
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Minor clean-ups of my temporary cruft.
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2021-03-06 17:11:06 -05:00 |
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Thomas Harte
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b72474f418
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Reduces debugging shout outs a touch.
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2021-03-03 20:53:05 -05:00 |
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Thomas Harte
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38046d49aa
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Increases debugging noise.
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2021-03-03 20:52:14 -05:00 |
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Thomas Harte
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267e28e012
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Adds various bits of debugging detritus.
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2021-02-27 22:27:57 -05:00 |
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Thomas Harte
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60cfec6a65
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Amongst ever more cruft, adds a couple of extra asserts.
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2021-02-18 22:49:48 -05:00 |
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Thomas Harte
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28bd620e7f
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Adds joystick support to the IIgs.
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2021-02-16 19:39:22 -05:00 |
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Thomas Harte
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fa8236741d
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Takes a shot at an ADB mouse.
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2021-02-15 20:49:16 -05:00 |
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Thomas Harte
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99c21925f4
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Makes attempt at keyboard mapping.
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2021-02-15 15:00:12 -05:00 |
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Thomas Harte
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eccf5ca043
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Makes first effort to wire up the ADB vertical blank input.
However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
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2021-02-14 22:20:58 -05:00 |
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Thomas Harte
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52cf15c3e6
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Attempts to route out modifier state.
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2021-02-14 21:15:31 -05:00 |
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Thomas Harte
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acfab1dfb3
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Starts to make some effort at timers.
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2021-02-06 21:02:44 -05:00 |
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Thomas Harte
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b8c6d4b153
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Rips out my high-level ADB microcontroller protocol implementation.
Adds just enough that the main computer validates the ADB controller as present and talking.
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2021-01-30 17:53:27 -05:00 |
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Thomas Harte
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c8beb59172
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Attempts properly to track ADB bus activity.
Output is not yet a valid ADB stream. Work to do.
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2021-01-25 17:43:22 -05:00 |
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Thomas Harte
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57e0fdfadc
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Ensures ADB microcontroller is clocked.
And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).
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2021-01-23 22:55:12 -05:00 |
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Thomas Harte
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ec0018df79
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Routes in the ADB keyboard ROM. This should get as far as parsing.
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2021-01-18 16:59:49 -05:00 |
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Thomas Harte
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12784a71e2
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A stab in the dark: does the IOLC inhibit also affect vector fetches?
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2020-12-29 20:53:56 -05:00 |
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Thomas Harte
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114d48b076
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This register appears to be read/write.
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2020-12-11 21:43:34 -05:00 |
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Thomas Harte
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049a78c667
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Slightly restricts video flushing test.
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2020-12-08 18:47:15 -05:00 |
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Thomas Harte
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65ca931e83
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Throws in a new assert, against the unimplemented bit 0 of new video.
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2020-12-06 20:26:24 -05:00 |
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Thomas Harte
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6273ef8ba2
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Adds means to force specific ROM 03 self tests.
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2020-12-02 20:48:19 -05:00 |
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Thomas Harte
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24fcb0c24b
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Corrects video counter values.
The built-in speed test now passes.
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2020-12-01 18:35:55 -05:00 |
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Thomas Harte
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03e2b6a265
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Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
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2020-12-01 17:46:30 -05:00 |
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Thomas Harte
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ee22cf7ca1
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Ensures that PAGE2 propagates from the state register to video.
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2020-11-30 22:56:19 -05:00 |
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Thomas Harte
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187f507532
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The soft switch is LCBANK2, not LCBANK1.
[This also jimmys the IIgs into always entering its extended self test, for now]
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2020-11-30 22:35:51 -05:00 |
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Thomas Harte
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6000bd3a5e
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Adds a bonus debugging assert. Let's see.
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2020-11-30 18:15:02 -05:00 |
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Thomas Harte
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35aa7612bb
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Ensures that auxiliary/language-card soft switches don't trigger my assert.
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2020-11-29 21:32:24 -05:00 |
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Thomas Harte
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acaa841822
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Adds guaranteed trip to ROM for vector pulls.
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2020-11-29 21:29:15 -05:00 |
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Thomas Harte
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4bdbca64b2
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Takes a shot at the Mega II-style video interrupts.
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2020-11-29 21:21:46 -05:00 |
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Thomas Harte
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11fe8ab6db
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Corrects counter scales, adds a read for $c032.
Albeit that I have no idea what that's supposed to read as.
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2020-11-29 20:08:59 -05:00 |
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Thomas Harte
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a9ce43d244
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Takes a shot at the two video counter registers.
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2020-11-29 19:57:35 -05:00 |
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Thomas Harte
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af667c718e
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Gets a bit more rigorous in remaining missing parts.
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2020-11-26 22:36:32 -05:00 |
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Thomas Harte
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f4d13d1f6f
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Takes a run at the bus side of honouring Ensoniq sequence points.
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2020-11-26 17:14:46 -05:00 |
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Thomas Harte
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8093f67173
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Ensures video interrupts can't be missed by a suitably-timed access.
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2020-11-26 16:11:03 -05:00 |
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Thomas Harte
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fdd102df52
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Resolves border colour resets.
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2020-11-26 13:13:48 -05:00 |
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Thomas Harte
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03a893dc74
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Quick refactor: this clearly isn't a VideoBase, it's the full implementation.
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2020-11-26 12:54:20 -05:00 |
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Thomas Harte
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cdc2311045
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Enables fuzzing, adds a definite no-op write.
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2020-11-25 23:33:55 -05:00 |
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Thomas Harte
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3cba3a5ac0
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Corrects card mask test outside of bank $00.
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2020-11-21 22:22:27 -05:00 |
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Thomas Harte
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4a42de4f18
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Attempts to add 5.25" drive support to the IIgs.
I want to try some classic software.
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2020-11-20 21:37:17 -05:00 |
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Thomas Harte
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1d288b08b6
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Attempts the two most basic forms of DOC output.
Sans interrupts. Or register reads of any variety.
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2020-11-19 21:19:27 -05:00 |
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Thomas Harte
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34794223b4
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For now, at least, c800–cfff is always built-in ROM.
Otherwise I probably need to extend my c3 logic to cover the other built-in cards (?)
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2020-11-18 19:49:45 -05:00 |
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Thomas Harte
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98347cb1c3
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Starts in the direction of audio support.
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2020-11-18 18:39:11 -05:00 |
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Thomas Harte
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bb80e53021
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Reduces frequency of video flushes.
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2020-11-16 21:55:41 -05:00 |
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Thomas Harte
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6dfad6a44b
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Slightly reduces logging.
Hopefully soon I can tear the whole lot out.
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2020-11-16 21:46:19 -05:00 |
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Thomas Harte
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9206ab5dc3
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Adds notes to self; implements get_next_sequence_point for video, allowing per-line interrupts.
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2020-11-16 14:42:50 -05:00 |
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Thomas Harte
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7e39550fc0
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Attempts to make JustInTimeActor sequence-point aware.
With the objective of chopping out a lot of future boilerplate.
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2020-11-15 21:58:18 -05:00 |
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Thomas Harte
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cdacf280e1
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After much extra logging, corrects destination bank for MVN and MVP.
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2020-11-15 16:08:29 -05:00 |
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Thomas Harte
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1538a02e18
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Better explains concern.
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2020-11-14 19:27:20 -05:00 |
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Thomas Harte
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f9cec9a102
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Attempts also to implement 1Mhz access costs.
Subject to TODO, and same observation as before: this is as to my current understanding only.
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2020-11-14 19:23:01 -05:00 |
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Thomas Harte
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adda3d8f42
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Attempts a 'full' model of 2.8Mhz access timing.
i.e. full to my current understanding.
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2020-11-14 19:10:41 -05:00 |
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