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10,422 Commits 7 Branches 121 Tags 500 MiB
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605 Commits

Author SHA1 Message Date
Thomas Harte
8578dfbf22 Eliminate various other errant spaces. 2023-05-16 16:40:09 -04:00
Thomas Harte
50343dec43 Eliminate all whitespace-only lines. 2023-05-12 14:16:39 -04:00
Thomas Harte
28c79b2885 Eliminate redundant [space][tab] pairs. 2023-05-12 14:14:45 -04:00
Thomas Harte
60bec3d4c0 Eliminate trailing whitespace, fix tabs. 2023-05-12 14:03:38 -04:00
Thomas Harte
2b56b7be0d Simplify namespace syntax. 2023-05-10 16:02:18 -05:00
Thomas Harte
315e0b4545 Add experimental 6809 opcode decoder. 
Just a pleasant distraction, for now.
 2023-03-17 21:20:35 -04:00
Thomas Harte
8808014a85 Add AddressingMode::ExtensionWord to the executor. 2022-12-19 11:07:58 -05:00
Thomas Harte
6832cbeb31 Attempt fully to tie together 68020+ addressing. 2022-12-19 10:38:51 -05:00
Thomas Harte
08b3c42a5c Edge further towards supporting full extension words. 2022-12-10 16:22:16 -05:00
Thomas Harte
95c526d957 Start arrangements for full extension words. 2022-11-30 16:21:35 -05:00
Thomas Harte
5813e2b6c6 Round out the list of operand flags. 2022-11-14 15:58:58 -05:00
Thomas Harte
ccadf69630 Add test of operand_flags and operand_size; add entries for missing 68000 and 68010 instructions. 2022-10-31 15:15:05 -04:00
Thomas Harte
bbd2cd47ea Decode [MUL/DIV][U/S].l. 2022-10-30 11:32:36 -04:00
Thomas Harte
63ad2e8263 Decode EXTB.l. 2022-10-30 11:20:43 -04:00
Thomas Harte
255d2f3486 Attempt LINK.l and CHK.l. 2022-10-29 21:42:53 -04:00
Thomas Harte
6ad1d74ddd Parse and record duality of CHK2/CMP2. 2022-10-29 21:32:48 -04:00
Thomas Harte
12ca79e645 Decode CAS2. 2022-10-28 14:02:49 -04:00
Thomas Harte
85df54ee7d Decode CAS. 2022-10-28 13:57:00 -04:00
Thomas Harte
8a8c044976 Support up to 15 extension words on a Preinstruction; use that to describe PACK/UNPK. 
TODO: reconcile when to use that field versus the ExtensionWord operand. Probably only when operands are full?
 2022-10-28 13:36:40 -04:00
Thomas Harte
f6a72dc2b4 Switch BFEXTU and BFFFO. 2022-10-27 12:13:13 -04:00
Thomas Harte
7d82b2ad12 Fix PACK operation code. 2022-10-27 10:52:07 -04:00
Thomas Harte
c2b8cbfefc Add text conversions. 2022-10-27 10:12:52 -04:00
Thomas Harte
53140c016e Disable bitcodes for operations that aren't otherwise yet present. 2022-10-27 10:09:16 -04:00
Thomas Harte
3f80df1feb Additional TST modes become available on the 68020. 2022-10-27 09:49:20 -04:00
Thomas Harte
cabf1a052c Fill in operand sizes and flags for the 68010 extensions. 2022-10-27 09:39:00 -04:00
Thomas Harte
8ff9f27b91 Decode MOVES. 2022-10-26 13:34:01 -04:00
Thomas Harte
ae2419e283 Decode MOVEC. 2022-10-26 12:50:15 -04:00
Thomas Harte
c1f0eed0a3 Decode MOVE from CCR. 2022-10-26 12:39:40 -04:00
Thomas Harte
4e5a80e23a Fix model tests. 2022-10-25 22:36:00 -04:00
Thomas Harte
46fee9c53a Add BKPT and RTD. 2022-10-25 22:35:44 -04:00
Thomas Harte
7ba6c78d14 MOVE from CCR, MOVEC and MOVES are on the 68010. 2022-10-25 21:27:23 -04:00
Thomas Harte
83b9fc3318 Declare TRAPcc operand size. 2022-10-25 12:20:40 -04:00
Thomas Harte
1ceabb30b0 Fully decode TRAPcc. 2022-10-25 12:19:03 -04:00
Thomas Harte
f8cb3ca8b5 Resolve transient GCC warning. 2022-10-25 10:20:06 -04:00
Thomas Harte
d8a11eaba7 Avoid explicit specialisation in non-namespace scope. 2022-10-25 10:13:12 -04:00
Thomas Harte
ab37b00356 Add model constraint to DIVS.l. 2022-10-25 10:04:36 -04:00
Thomas Harte
b4fcf92a62 Output extension words as if immediates. 2022-10-25 09:58:01 -04:00
Thomas Harte
38c531fd5a Accept that a uint8_t isn't always going to be large enough; split decoding by minimum processor. 2022-10-25 09:50:19 -04:00
Thomas Harte
8c670d2105 Add decodes for TRAPcc and PACK, discovering it's three operand (sort of). 2022-10-23 11:46:47 -04:00
Thomas Harte
9a56d053f8 Introduce/extend 68k enums to cover 68020 instruction set. 2022-10-22 15:20:30 -04:00
Thomas Harte
cb0e259339 Start the process of decoding 68020 operations. 2022-10-21 15:28:29 -04:00
Thomas Harte
ec728ad573 Fix ADD/SUBX carry. 2022-10-19 22:17:51 -04:00
Thomas Harte
bc9ddacb8d Improve commentary. 2022-10-19 14:40:29 -04:00
Thomas Harte
979bf42541 Fix ASL overflow test. 2022-10-18 22:43:17 -04:00
Thomas Harte
d09473b66f Move common negative and zero logic into Status. 2022-10-18 14:51:51 -04:00
Thomas Harte
b31b4a5d10 Reformulate NOT in terms of EOR, and clean up elsewhere. 2022-10-18 12:17:55 -04:00
Thomas Harte
5560a0ed39 Fix overflow test for ASL. 2022-10-18 11:47:36 -04:00
Thomas Harte
a1ae7c28b2 Add various insurances against undefined behaviour. 2022-10-18 11:30:40 -04:00
Thomas Harte
fb2b7969a2 Add TODO to self on undefined behaviour. 2022-10-17 23:14:14 -04:00
Thomas Harte
abb19e6670 Populate carry whenever count != 0, regardless of modulo. 2022-10-17 22:57:21 -04:00
Thomas Harte
555250dbd9 Don't trample on X before use. 2022-10-17 22:19:35 -04:00
Thomas Harte
8148397f62 Fill in comments, eliminate u/s_extend16 macros. 2022-10-17 15:37:13 -04:00
Thomas Harte
f095bba1ca Eliminate bitwise macros. 2022-10-17 15:21:54 -04:00
Thomas Harte
ee3a3df0b5 Eliminate SBCD macro. 2022-10-17 15:12:38 -04:00
Thomas Harte
aff1caed15 Clean up formatting. 2022-10-17 15:05:23 -04:00
Thomas Harte
da03cd58c1 Add overt casting. 2022-10-17 15:04:28 -04:00
Thomas Harte
ce98ca4bdd Pull RO[L/R][X]m out of their macro stupor. 2022-10-17 11:27:04 -04:00
Thomas Harte
cc55f0586d Clean up ASL/ASR/LSL/LSRm. 2022-10-17 11:18:10 -04:00
Thomas Harte
47e8f3c0f1 Collapse [A/L]S[L/R].[bwl] into a template. 2022-10-16 22:21:20 -04:00
Thomas Harte
d5ceb934d2 Fix overflow flags, avoid bigger-word usage. 2022-10-16 21:52:00 -04:00
Thomas Harte
17c1e51231 Commute ROL/ROR to templates. 2022-10-16 12:19:09 -04:00
Thomas Harte
fee072b404 Commute ROXL and ROXR into a template. 2022-10-16 12:06:28 -04:00
Thomas Harte
0a9c392371 Remove unused bit_count. 2022-10-13 15:01:06 -04:00
Thomas Harte
06dbb7167b Unify TST. 2022-10-11 21:31:14 -04:00
Thomas Harte
eff9a09b9f Collapse MOVE and NEG[X] similarities. 2022-10-11 21:27:18 -04:00
Thomas Harte
1f19141746 Eliminate BiggerInt. 2022-10-11 16:19:47 -04:00
Thomas Harte
28093196b9 Convert DIVU/DIVS logic to a template. 2022-10-11 16:16:53 -04:00
Thomas Harte
eb206a08d9 Templatise MULU/MULS. 2022-10-11 16:02:20 -04:00
Thomas Harte
b2f005da1b Collapse SR/CCR bitwise operations into a template. 2022-10-11 15:53:11 -04:00
Thomas Harte
8305a3b46a Consolidate compare logic. 2022-10-11 12:57:02 -04:00
Thomas Harte
f3f23f90a3 Consolidate repetition in CLR. 2022-10-11 11:22:34 -04:00
Thomas Harte
77bc60bf86 Consolidate BCLR, BCHG and BSET into a macro. 2022-10-11 10:47:55 -04:00
Thomas Harte
ec5d57fefe Eliminate 64-bit work. 2022-10-11 10:33:28 -04:00
Thomas Harte
58396f0c52 Perform a prima facie conversion of ADD/SUB[/X] from macros to templates. 2022-10-10 22:21:13 -04:00
Thomas Harte
451b730c8e Avoid returning without value in release builds. 2022-09-09 16:48:12 -04:00
Thomas Harte
72b6ab4389 Provide a route to operation that factors in addressing mode. 2022-09-06 11:26:16 -04:00
Thomas Harte
effe8c102d Provide a direct to_string on Operation. 2022-09-05 21:52:20 -04:00
Thomas Harte
b6f45d9a90 Fix struct/class confusion. 2022-08-10 15:40:46 -04:00
Thomas Harte
8ada73b283 Use the outer switch for addressing mode dispatch, saving a lot of syntax. 2022-06-13 08:57:49 -04:00
Thomas Harte
71e38a6781 Fix decoding of RESET. 2022-06-03 11:15:50 -04:00
Thomas Harte
02b6ea6c46 Factor out would-accept-interrupt test, per uncertainty re: level 7. 2022-06-03 08:31:56 -04:00
Thomas Harte
c3b436fe96 Use int64_t as an intermediary to avoid x86 exception on INT_MIN/-1. 2022-06-02 21:39:52 -04:00
Thomas Harte
659e4f6987 Include fixed cost of rolls. Which includes providing slightly more information to did_shift. 2022-06-01 20:30:51 -04:00
Thomas Harte
75e85b80aa Factor out the common stuff of exception state. 2022-06-01 08:20:33 -04:00
Thomas Harte
73815ba1dd No need for this hoop jumping here. 2022-06-01 08:20:06 -04:00
Thomas Harte
8ffaf1a8e4 Ensure did_divu/s are performed even upon divide by zero. 2022-05-29 21:18:19 -04:00
Thomas Harte
7788a109b0 Tweak more overtly to avoid divide by zero. 2022-05-29 20:51:50 -04:00
Thomas Harte
3ef53315a2 Don't try to append operands to 'None'. 2022-05-29 15:28:16 -04:00
Thomas Harte
3da720c789 Make requires_supervisor explicitly compile-time usable. 2022-05-29 14:55:24 -04:00
Thomas Harte
c97245e626 Fix CalcEA timing; make MOVEfromSR a read-modify-write. 2022-05-27 10:32:28 -04:00
Thomas Harte
463fbb07f9 Adapt remaining 68000 tests to use Mk2. 2022-05-25 10:55:17 -04:00
Thomas Harte
9e3c2b68d7 Eliminate potential future implicit conversion warnings. 2022-05-24 11:05:24 -04:00
Thomas Harte
3349bcaaed Attempt interrupt support. 2022-05-24 10:53:59 -04:00
Thomas Harte
6a442e0136 MOVEM has an immediate first operand. 2022-05-20 20:34:51 -04:00
Thomas Harte
cb77519af8 Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode. 2022-05-20 12:40:09 -04:00
Thomas Harte
ba8592ceae At least on the 68000, Scc is read-modify-write. 2022-05-20 11:43:26 -04:00
Thomas Harte
452dd3ccfd Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000. 2022-05-20 11:20:23 -04:00
Thomas Harte
eeb6a088b8 Add a tag to avoid duplication. 2022-05-19 15:49:42 -04:00
Thomas Harte
e4c0a89889 Just use the four-bit register number directly. 2022-05-19 15:01:09 -04:00
Thomas Harte
c6c6213460 Bifurcate the fetch-operand flow. 
Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.
 2022-05-19 10:27:51 -04:00