4134463094
The ACIA now receives bits.
2019-10-20 23:34:30 -04:00
83d73fb088
The keyboard now responds to a reset on its serial line.
2019-10-20 23:13:44 -04:00
cf07982a9b
Ensures good serial line and ACIA behaviour.
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Next stop: having the intelligent keyboard react.
2019-10-20 22:10:05 -04:00
2e86dada1d
Ensures updates even when the event queue is empty.
2019-10-20 20:38:56 -04:00
696af5c3a6
Starts to transfer serial line decoding logic into the line itself.
2019-10-20 20:38:56 -04:00
f08b38d0ae
Silences, temporarily.
2019-10-20 20:38:55 -04:00
9a8352282d
Mostly but not quite fixes serial work.
2019-10-20 20:38:55 -04:00
3d03cce6b1
Starts working on the GPIP functionality block.
2019-10-20 20:38:55 -04:00
34075a7674
Attempts to tie an intelligent keyboard to the other end of its serial line.
2019-10-20 20:38:55 -04:00
f79c87659f
Corrects documentation error.
2019-10-20 20:38:55 -04:00
c10b64e1c0
Adds a received_data_ register, that presently can never fill.
2019-10-20 20:38:55 -04:00
5d5fe52144
Corrects transmission logic — exactly hitting write_data_time_remaining now works properly.
2019-10-20 20:38:55 -04:00
d461331fd2
Ensures remaining_delays_ is set properly after [reset/flush]_writing.
2019-10-20 20:38:55 -04:00
ff62eb6dce
The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.
2019-10-20 20:38:55 -04:00
374439693e
Ensures serial lines know their writer's clock rate.
2019-10-20 20:38:55 -04:00
c4ef33b23f
JustInTimeActors can now specify a clock divider.
2019-10-20 20:38:55 -04:00
a7ed357569
Attempts to implement transmission interrupts and ClockingHint::Source.
2019-10-20 20:38:55 -04:00
4e5b440145
Attempts mostly to implement 6850 output.
2019-10-20 20:38:55 -04:00
2bd7be13b5
Decodes the 6850 control register, and starts working on standardised serial ports.
2019-10-20 20:38:55 -04:00
4b09d7c41d
Nudges 6850 towards coherence.
2019-10-20 20:38:55 -04:00
b0f5f7bd37
Attempts to start producing actual video.
2019-10-20 20:38:55 -04:00
4ead905c3c
Adds an empty shell for the ACIA.
2019-10-20 20:38:55 -04:00
127bb043e7
Adds enough logic to advance to an ACIA access error.
2019-10-20 20:38:55 -04:00
2cf52fb89c
Makes an unsuccessful first attempt at some timer functionality.
2019-10-20 20:38:54 -04:00
6e1b606adf
Adds a target for MFP read/write operations.
...
Completely without any implementation, so far.
2019-10-20 20:38:54 -04:00
929475d31e
Minor correction: round down, not up.
2019-09-28 23:49:32 -04:00
7758f9d0a9
Improves nomenclature.
2019-09-24 22:31:36 -04:00
8d4a96683a
Reduces output noise.
2019-09-18 21:41:29 -04:00
f53411a319
Removes local NDEBUG.
2019-09-18 21:35:26 -04:00
962275c22a
Removes clock for NCR 5380.
...
It doesn't have one in real life, and now can live off the time counting that occurs on the SCSI bus.
2019-09-18 20:17:47 -04:00
2f6c366668
Makes a concerted effort at properly wrapping a hard disk image.
2019-09-17 21:30:04 -04:00
2ce1f0a3b1
Implements multi-sector read/write.
...
This once again unblocks Apple HD SC Setup. Progress!
2019-09-16 22:20:42 -04:00
960b289e70
Edges closer towards proper DMA operation.
...
Specifically: differentiates the three kinds of DMA operation. Still doesn't act correctly with regard to DACK though, and leaves the bus instantaneously improperly formed. Which I'm tempted to try to fix on the target side by properly obeying delays.
2019-09-15 15:03:06 -04:00
243e40cd79
Adds signalling of DACK.
2019-09-14 13:48:33 -04:00
64dad35026
Decreases logging, at least temporarily.
2019-09-03 22:40:32 -04:00
1c7e0f3c9d
Fixes control line modification by the 5380 and SCSI target command chaining.
...
So now I'm back to trying to guess how a SCSI command terminates re: the relative meanings of a message phase and a status phase.
2019-09-02 23:14:37 -04:00
ca08716c52
Introduces real hard disk images to the nascent world of SCSI.
2019-08-25 17:03:41 -04:00
c86db12f1c
Starts implementing DMA support on the 5380.
...
The Macintosh doesn't actually use the DMA signals, but uses pseudo-DMA mode so they nevertheless need to be appropriate.
2019-08-24 22:47:11 -04:00
2d82855f26
Attempts to provide a data out phase.
2019-08-22 23:16:58 -04:00
faec516a2c
Starts pushing towards figuring out a proper infrastructure for mass storage.
2019-08-21 23:22:58 -04:00
bb1a0a0b76
Sketches out further SCSI infrastructure.
2019-08-21 22:37:39 -04:00
252650808d
Starts seeking to unbind SCSI bus logic and command performance.
2019-08-19 22:47:01 -04:00
e3d9254555
Implements phase-match bit.
...
Seemingly causing the command phase to proceed.
2019-08-18 23:15:54 -04:00
955e909e61
Attempts to nudge the command phase further towards functioning.
2019-08-18 22:39:27 -04:00
8339e2044c
Switches to proper SCSI terminology and better attempts a command phase.
2019-08-18 15:10:07 -04:00
0e0c789b02
Starts attempting to introduce a direct access device.
...
Without having access to the SCSI-1 standard, a lot of this is guesswork.
2019-08-17 23:43:42 -04:00
7e001c1d03
Corrects data line loading.
...
Also adds some extra temporary logging. Outstanding question: why is ATN not being signalled? Is SEL enough?
2019-08-17 21:30:59 -04:00
9047932b81
Corrected basic error. Arbitration now seems to succeed.
...
This is seemingly followed by a pattern of signalling BUSY+SEL followed by just SEL with the various other potential device IDs in turn. To which nothing ever responds as currently implemented.
2019-08-15 23:28:30 -04:00
f668e4a54c
Makes an attempt at getting the 5380 past arbitration.
...
Not entirely successful. Also gets a bit smarter with `final` on ClockingHint::Sources.
2019-08-15 23:14:40 -04:00
ce1c96d68c
Starts thinking out the mechanics of emulating a SCSI-1 bus.
2019-08-13 23:09:11 -04:00
Thomas Harte