Thomas Harte
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681d1e2f8d
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Breaking its typer for now, adapted the ZX80/81 to having a Z80, not being one.
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2017-08-02 22:12:59 -04:00 |
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Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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968d2bb8ba
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Brought Typer into the new run_for orthodoxy, making it easier to clock consistently regardless of unit. Which necessitated adding a negative operator for WrappedInts.
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2017-07-27 21:53:45 -04:00 |
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Thomas Harte
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8848ebbd4f
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Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81.
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2017-07-27 21:10:14 -04:00 |
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Thomas Harte
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8361756dc4
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Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
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2017-07-27 07:40:02 -04:00 |
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Thomas Harte
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81a3899381
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Adjusted the Z80 formally to communicate in terms of half cycles rather than whole.
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2017-07-26 19:42:00 -04:00 |
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Thomas Harte
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966b5e6372
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Adapted the Z80's perform_machine_cycle to return Cycles.
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2017-07-25 22:25:44 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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a1e9a54765
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Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
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2017-07-25 20:09:13 -04:00 |
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Thomas Harte
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8a2bdb8d22
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Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
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2017-07-24 21:19:05 -04:00 |
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Thomas Harte
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b82bef95f3
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Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
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2017-07-24 20:10:05 -04:00 |
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Thomas Harte
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ba088e5545
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Adapted the Z80 into a clock receiver, which also vends Cycles rather than a raw int within its PartialMachineCycle struct. The objective is to update it to vend HalfCycles within its struct, but I think I need to do some work on cycle/half-cycle arithmetic first.
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2017-07-23 22:15:04 -04:00 |
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Thomas Harte
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c2a7dffa7d
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Converted the ZX80/81 video component into a ClockReceiver. As it happens, it's most convenient to take the half-cycle bus here.
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2017-07-22 23:02:28 -04:00 |
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Thomas Harte
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2ff157cf7a
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Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
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2017-07-22 22:17:29 -04:00 |
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Thomas Harte
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3f609e17b3
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Factored out the table-lookup approach to being a typer, and adjusted so as definitely to limit myself to positive offset table lookups.
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2017-07-21 21:18:51 -04:00 |
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Thomas Harte
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2471ef805b
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Fixed signed/unsigned comparison and potential negative table reference.
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2017-07-21 20:45:49 -04:00 |
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Thomas Harte
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a3e0024980
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Chopped time accumulation out of the default Tape process because it's proving to be sufficiently expensive for a TZX as not to be worthwhile. Introduced a cheaper position capturing/restoring method.
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2017-07-21 18:55:03 -04:00 |
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Thomas Harte
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44e5a03cf2
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Removed just-don't-power-the-tape approach to pausing and playing, in favour of being fully communicative.
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2017-07-19 19:21:27 -04:00 |
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Thomas Harte
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ac59dd8b1d
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Added enough typing to issue a load command. No thoughts as to running yet though.
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2017-07-09 22:07:12 -04:00 |
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Thomas Harte
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3e5c209039
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Added basic Typer support for the ZX80 and '81.
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2017-07-09 22:00:34 -04:00 |
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Thomas Harte
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ed28260aaf
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Hardens the ZX80/81 video routines to ensure they never try to push data into the future and don't double-count time when pixels would ostensibly run into sync. You could previously see the CRT being handed negative run lengths if sync interrupted pixels or if a run of more than 320 pixels (my arbitrary buffer size) occurred, with corresponding poor behaviour given my use of unsigned numbers.
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2017-07-09 19:33:05 -04:00 |
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Thomas Harte
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87658e83c1
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Moved line counter reset logic; I think this is actually correct.
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2017-07-09 00:05:30 -04:00 |
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Thomas Harte
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4509c3ce34
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By observation, it appears that disabling vsync occurs on any port output whatsoever, as long as NMI isn't blocking it.
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2017-07-08 21:01:52 -04:00 |
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Thomas Harte
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30e93979d2
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Removed data work if sync is enabled; in that case no data is output.
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2017-07-08 21:01:07 -04:00 |
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Thomas Harte
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d6b87053bf
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Introduced an explicit record of whether a video byte is latched. It's definitely incorrect to treat the latching of 0 as equivalent to no latching, as the byte that will eventually become video is not strongly implied.
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2017-07-08 20:40:19 -04:00 |
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Thomas Harte
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22389a5d2d
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Merge branch 'master' into HiRes
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2017-07-08 20:38:25 -04:00 |
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Thomas Harte
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54efcb7e2f
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Made a game attempt at automatic motor control and ensured setting is initialised correctly from the user defaults.
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2017-07-08 19:31:20 -04:00 |
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Thomas Harte
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e2575d6de4
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Routed tape motor selections through to the C++ side of the world, and ensured that manual tape playback works properly.
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2017-07-08 19:21:12 -04:00 |
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Thomas Harte
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46fff8e8a2
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Ensured bit 8 is uniquely from the latched video byte, not an OR of that with the refresh address.
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2017-07-06 22:48:48 -04:00 |
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Thomas Harte
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a3684545b5
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Added a block on the tape motor for a short period after each time the ROM routine is intercepted for a substituted byte read. To reduce the collision between fast tape and real tape loading.
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2017-07-06 22:33:54 -04:00 |
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Thomas Harte
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a72a2e0a1a
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Ensured tape doesn't proceed of its own volition when in fast-loading mode.
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2017-06-23 20:21:37 -04:00 |
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Thomas Harte
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50375fb373
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Ensured tape position is unaffected if the attempt at loading quickly fails.
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2017-06-23 20:18:19 -04:00 |
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Thomas Harte
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cb105fdeb4
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Took a first stab at high-res support.
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2017-06-22 22:48:17 -04:00 |
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Thomas Harte
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acfd4dde36
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Reduced port writes which can adjust programmatic sync, and prevented anything while NMI generation is active. Moved line counter increment from triggered by interrupt acknowledge to triggered by horizontal sync. In both cases, cribbing from my own earlier work. Initial results suggest that sync issues are resolved in third-party software.
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2017-06-22 22:44:06 -04:00 |
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Thomas Harte
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644ef13acd
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Connected up the fast-tape GUI option for the ZX80 and '81.
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2017-06-22 20:20:31 -04:00 |
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Thomas Harte
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b7c978e078
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Added getters for most of the input lines, and attempted to round out the ZX81's wait logic.
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2017-06-22 20:11:19 -04:00 |
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Thomas Harte
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52d9ddf9e5
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Gave the binary tape player a more logical assignment of wave level to output level. Which miraculously appears to have been the issue with the ZX80/81 tape loading — the inconsistency of silences seems to have been the issue.
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2017-06-21 22:13:24 -04:00 |
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Thomas Harte
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a6810fc3ef
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Removed some minor duplicity and ensured that hsync/NMI ends on the nominated cycle, not one afterwards.
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2017-06-21 21:44:42 -04:00 |
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Thomas Harte
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15f6c51062
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Added the most trivial implementation of the ZX81 wait line.
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2017-06-21 21:28:14 -04:00 |
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Thomas Harte
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e1355d4b62
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Restored proper video output.
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2017-06-21 21:18:09 -04:00 |
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Thomas Harte
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4bf13610ce
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Reinstated interrupts by moving the refresh test back into the refresh cycle.
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2017-06-21 21:03:39 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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08a542a324
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Reenabled the fast-loading hack.
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2017-06-15 18:30:12 -04:00 |
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Thomas Harte
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9b3d05e05f
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Simplified decoding logic.
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2017-06-14 22:24:44 -04:00 |
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Thomas Harte
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d8e3103a2b
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Fixes: switched ZX80 and ZX81 timing to the correct way around, ensured that my wait takes effect if HALT **isn't** set, and made sure to recover from it.
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2017-06-13 21:48:17 -04:00 |
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Thomas Harte
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76a64d13a0
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Made a first attempt at ZX81 emulation.
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2017-06-13 21:25:55 -04:00 |
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Thomas Harte
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1e975859c2
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Started splitting ZX80 and ZX81 paths. Also the '80 fires its horizontal sync a little earlier than the '81, so pulled that back a little.
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2017-06-13 20:09:09 -04:00 |
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Thomas Harte
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4c5261bfa0
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Made first attempt to use the horizontal counter for something; here for sync timing only, even though I've gone exclusively with '81-style timing for now.
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2017-06-12 22:28:30 -04:00 |
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