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262 Commits

Author SHA1 Message Date
Thomas Harte
0eebfdb4cc Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines. 2017-06-04 15:39:37 -04:00
Thomas Harte
7811374b0f Started sneaking in memptr emulation, hopefully to get to a working BIT (hl). 2017-06-04 15:07:07 -04:00
Thomas Harte
a2f01b4a46 Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL) with the famous MEMPTR reliance is preventing a complete pass by Zexall now. 2017-06-04 14:59:18 -04:00
Thomas Harte
f5c910beb7 Fixed LDIR/LDDR bit 3/5 flags. This seems once again to satisfy FUSE. 2017-06-04 14:18:04 -04:00
Thomas Harte
4e014ca748 Ensured BIT takes bits 5 and 3 from the computed address if used on indexed pages. That seems to cover 97 failures out of 100? 2017-06-04 14:13:38 -04:00
Thomas Harte
1a811b1ab1 Eliminated the function call inherent to every decode, and also moved the fixed table of operations into a non-templated base class. 2017-06-03 22:19:35 -04:00
Thomas Harte
c26349624c This, of course, should be inline to gain any benefit from the slightly-tortured private implementation. 2017-06-03 22:00:57 -04:00
Thomas Harte
b642d9f712 Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs. 2017-06-03 21:54:42 -04:00
Thomas Harte
fd6623b5a5 Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502. 2017-06-03 21:22:16 -04:00
Thomas Harte
b304c3a4b9 Eliminated the 6502's reliance on the micro-op scheduler. 2017-06-03 20:30:07 -04:00
Thomas Harte
3ceef2005b Pulled the Z80 from the MicroOpScheduler inheritance tree as it barely uses the thing, and that allows me to make the MicroOp structure private. 2017-06-03 19:17:34 -04:00
Thomas Harte
24c84ca6f5 Commented out as-yet-unimplemented features. 2017-06-03 19:10:23 -04:00
Thomas Harte
7898f643ac Added bus request/acknowledge logic. 2017-06-03 19:09:47 -04:00
Thomas Harte
7bd45d308a Error was simply failure of the interrupt-mode setter. Fixed. 2017-06-03 18:58:13 -04:00
Thomas Harte
b3da16911f Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2. 2017-06-03 18:42:54 -04:00
Thomas Harte
8c41a0f0ed Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine. 2017-06-03 17:53:44 -04:00
Thomas Harte
3e9212aaff Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed. 2017-06-03 17:41:45 -04:00
Thomas Harte
a2ec902773 Made an attempt at implementing all three modes of IRQ. 2017-06-03 17:07:05 -04:00
Thomas Harte
1c0130fd02 Cleaned up with a macro, and decided to make absolutely sure that DecodeOperation is functioning as intended by removing the MoveToNextProgram from fetch-decode-execute. 2017-06-03 12:19:25 -04:00
Thomas Harte
3e3d6f97f4 Edged towards being able to implement interrupt mode 0: created a special-case micro-op for incrementing the PC, and formalised that DecodeOperation is a terminal operation. 2017-06-03 12:16:21 -04:00
Thomas Harte
9c3bda0111 Attempted to round out NMI handling. 2017-06-03 11:30:12 -04:00
Thomas Harte
d14902700a Minor syntax and wiring fixes. 2017-06-01 22:33:05 -04:00
Thomas Harte
c95c32a9fe Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine. 2017-06-01 22:31:04 -04:00
Thomas Harte
35e045d7a7 Made a first attempt at the correct segue into the three main kinds of interrupt, though the programs aren't written yet. So undefined behaviour would abound were an interrupt to occur. But it lets me figure out what effect the check has on performance. I hope little. 2017-06-01 22:16:22 -04:00
Thomas Harte
084e1f3d51 Added a latching of interrupt status before each bus operation, and reset and power-on inputs. 2017-06-01 21:40:08 -04:00
Thomas Harte
5b43cefb85 Started filling an appropriate mask variable with the interrupt request status right now. Which is step one towards implementing interrupts. 2017-06-01 20:34:52 -04:00
Thomas Harte
aab637c9e7 Made check_address_for_trap inlineable. 2017-06-01 18:28:34 -04:00
Thomas Harte
7d9b197383 Pulled the .get() call for fetch-decode-execute out of the main loop. 2017-06-01 18:28:04 -04:00
Thomas Harte
c9dd267ec1 Sketched an interface for signalling interrupts and pulled out some of the repetition in flag setting from ADD/ADC/SUB/SBC/CP. 2017-05-31 22:51:32 -04:00
Thomas Harte
a5254989f8 Rewired the Z80 not to use the program queue, as it's not proven a useful abstraction in practice and doing so yields an immediate 22% speed increase. 2017-05-31 20:15:56 -04:00
Thomas Harte
494ce073b5 Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging. 2017-05-31 19:58:57 -04:00
Thomas Harte
b99e4210ba Eliminated pointless abstraction; I ended up going indirect on instruction pages rather than scheduling methods. 2017-05-31 19:57:03 -04:00
Thomas Harte
d3b74cbc91 Set proper initial value for number_of_cycles_. 2017-05-31 19:55:51 -04:00
Thomas Harte
2f7f11e2e5 Added diagnosis props. 2017-05-31 06:54:25 -04:00
Thomas Harte
5119997122 Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function. 2017-05-30 22:41:23 -04:00
Thomas Harte
b5c1773d59 Eliminated another conditional. Albeit a very predictable one. 2017-05-30 22:15:43 -04:00
Thomas Harte
dfb5057342 Moved repetition group conditions explicitly into the switch statement. 2017-05-30 22:12:10 -04:00
Thomas Harte
7bddd294c9 Resolved an unpredictable conditional and temporarily disabled the Zexalltest as part of the default suite, since it takes so long to run. 2017-05-30 21:03:02 -04:00
Thomas Harte
01f7394f7f Corrected 6502 scheduling when flushing the pipeline. 2017-05-30 20:58:07 -04:00
Thomas Harte
5aa8b03349 Attempted to regularise the 6502 with the Z80 as to scheduling. I think that at least one bug remains. 2017-05-30 20:36:53 -04:00
Thomas Harte
b5ad910b81 Merge branch 'Z80' into StraightPointer 2017-05-30 19:25:38 -04:00
Thomas Harte
da65bae86e Switched to supplying the bus operation by reference, go guarantee that it isn't null. 2017-05-30 19:24:58 -04:00
Thomas Harte
a0189a6fe1 Switched to following the current program via address. 2017-05-30 18:49:40 -04:00
Thomas Harte
c6185baa99 Fixed R incrementation and attempted to make the status flags cheaper to write to. 2017-05-29 22:23:19 -04:00
Thomas Harte
9d29cefe75 Evicted manual memory management. 2017-05-29 21:44:33 -04:00
Thomas Harte
35f535b9a3 Noodled around with initial state. 2017-05-29 19:25:08 -04:00
Thomas Harte
8bfaa487ce Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit). 2017-05-29 17:13:24 -04:00
Thomas Harte
0d067d2f01 Adjusted OTI/etc timing; 23 failures outstanding. 2017-05-29 16:54:45 -04:00
Thomas Harte
d66755fd1e Corrected INI/D[r] timing. Down to 45 failures. 2017-05-29 16:50:52 -04:00
Thomas Harte
d290e3d99e Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!) 2017-05-29 16:35:00 -04:00
Thomas Harte
a6a4c5a936 Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures. 2017-05-29 15:57:27 -04:00
Thomas Harte
8a8f0cef20 With all intentional opcode entry points now covered, commuted XX into NOP to give proper meaning to otherwise undefined codes. 2017-05-29 12:25:10 -04:00
Thomas Harte
91dc0d5f4a Adjusted HALT to issue never-ending M1 fetches on the next instruction. 2017-05-29 12:20:33 -04:00
Thomas Harte
ed7b07c8b1 Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct. 2017-05-29 11:54:27 -04:00
Thomas Harte
3f880fa769 Fixed [FD/DD][74/75], which always store H or L, never IXh, IXl, IYh or IYl. 2017-05-29 11:44:26 -04:00
Thomas Harte
d83dd17738 [DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed. 2017-05-29 11:40:56 -04:00
Thomas Harte
c322410783 Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation. 2017-05-29 10:52:54 -04:00
Thomas Harte
b67331e018 Fixing the OUT repetition group reduces the code to one failing test. 2017-05-29 10:48:53 -04:00
Thomas Harte
a47b339668 Made an attempt at OUT[I/D]R. 10 failures remaining. None of which, I guess, are due to unimplemented operations. 2017-05-29 10:28:04 -04:00
Thomas Harte
ad56a9215c Implemented IN[I/D]x. 18 failures remaining. 2017-05-29 10:12:33 -04:00
Thomas Harte
c56a5344b9 Implemented CP[I/D]x. 2017-05-29 08:54:00 -04:00
Thomas Harte
1f62cbe21a Reduced LD[I/D}{R} repetition. 2017-05-29 08:24:10 -04:00
Thomas Harte
47845f8c19 Tried to complete the LD[I/D]{R} group. 32 issues remain. 2017-05-28 23:55:54 -04:00
Thomas Harte
409c82ce73 Implemented RLD and RRD. 34 failures remaining. 2017-05-28 16:46:27 -04:00
Thomas Harte
dc3f5b6211 Fixed flag setting for LD A, I and LD A, R, and corrected typo affecting LD DE, (nn). 2017-05-28 16:32:10 -04:00
Thomas Harte
fb02b77e63 Implemented RETI/RETN. 40 warnings remaining. 2017-05-28 16:07:25 -04:00
Thomas Harte
f974d54c7a Implemented IM. 48 failures remain. 2017-05-28 15:55:21 -04:00
Thomas Harte
68978c6e25 Implemented NEG and filled in the load/store and copy parts of the ED page that roll directly off the tongue. 53 issues outstanding. 2017-05-28 15:47:48 -04:00
Thomas Harte
5a4d448cc1 Corrected logical flags; now down to 68 failures, all of them on the ED page. 2017-05-28 15:09:58 -04:00
Thomas Harte
743eac8c55 Implemented EXX to complete the base page. 83 failures. 2017-05-28 14:55:14 -04:00
Thomas Harte
6b66c8f304 Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84. 2017-05-28 14:50:51 -04:00
Thomas Harte
c976fbfcd5 Implemented the base-page IN and OUT instructions, bringing FUSE test failures down to 91. 2017-05-28 14:20:05 -04:00
Thomas Harte
ed3e38ac31 Performed some quick tidying. 2017-05-28 00:12:42 -04:00
Thomas Harte
76f03900d2 Implemented EX HL, (SP) so as, allowing for indexed pages, to bring issues below the psychological 100 barrier. To 99. 2017-05-28 00:02:14 -04:00
Thomas Harte
9759a04c7d Timing fixes: the fetch-decode-execute pattern is now per-page, since that on [DD/FD]CB not only doesn't increment R but doesn't take four cycles, so is probably a normal read cycle. Adjusted timing all around. 2017-05-27 23:54:06 -04:00
Thomas Harte
0d2d04e17b Seeking proper [F/D]DCB emulation: the offset comes before the final byte of opcode, and adding seems to overlap with the opcode fetch, which does not increment R. Also needs to duplicate the result to visible registers. 2017-05-27 21:06:56 -04:00
Thomas Harte
98423c6e41 Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues. 2017-05-27 16:19:15 -04:00
Thomas Harte
33c3fa21e3 Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672. 2017-05-27 15:54:24 -04:00
Thomas Harte
2141d52794 Corrected typo. Now at 696 failures. 2017-05-27 15:41:26 -04:00
Thomas Harte
16b8021401 Made a stab at the CB pages. 2017-05-27 15:39:22 -04:00
Thomas Harte
151b09b5ca Fixed various other obvious cases for indexing. 2017-05-26 23:37:17 -04:00
Thomas Harte
9bc2b48d9b Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures. 2017-05-26 23:23:33 -04:00
Thomas Harte
ab8a98f1df Implemented RST. 2017-05-26 07:29:19 -04:00
Thomas Harte
efe354a7b1 Fixed half carry after logical operation.s 2017-05-25 22:55:04 -04:00
Thomas Harte
d50d3fc837 Implemented CPL, SCF and CCF. 2017-05-25 22:51:08 -04:00
Thomas Harte
83ee92af1a Made DAA work sufficiently well for the FUSE test. 2017-05-25 22:41:05 -04:00
Thomas Harte
ea0ad9fd87 Took a shot at DAA, seemingly not to Fuse's liking though. 2017-05-25 22:17:48 -04:00
Thomas Harte
ff3c60c0e1 Implemented the conditional JRs. 2017-05-25 21:51:30 -04:00
Thomas Harte
399703a471 Implemented JR. 2017-05-25 21:48:28 -04:00
Thomas Harte
82017c4aea Implemented DJNZ. 2017-05-25 21:44:24 -04:00
Thomas Harte
bdf07c3dc9 Implemented EX AF, AF'. 2017-05-25 21:26:32 -04:00
Thomas Harte
598be24644 Fixed overflow for 8-bit decrementing. 2017-05-25 21:23:38 -04:00
Thomas Harte
c668ff9472 Added incrementing of the refresh register. 2017-05-25 21:01:52 -04:00
Thomas Harte
6575091a78 Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly. 2017-05-22 21:50:34 -04:00
Thomas Harte
9e25d014d2 Made an attempt to log bus activity for comparison with FUSE results. 2017-05-22 19:49:38 -04:00
Thomas Harte
41d5dd8679 Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured. 2017-05-22 19:24:11 -04:00
Thomas Harte
c3ea6dc1f5 Added respect for limiting to the requested number of cycles in the Z80. 2017-05-22 19:15:55 -04:00
Thomas Harte
22afa509ca Got to a parsing and towards an attempt to run FUSE tests. 2017-05-22 19:14:46 -04:00
Thomas Harte
f2aae72cc2 Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least. 2017-05-21 20:43:36 -04:00
Thomas Harte
fe8db1873c Added 16-bit ADC and SBC table entries; once again extended logging. 2017-05-21 20:32:06 -04:00