Thomas Harte
54103f1f34
Fix SH=1 reset; appropriate TCS.
2023-08-05 15:06:18 -04:00
Thomas Harte
c0eb401d04
Add a between-instructions enforcement of SH = 1.
2023-08-05 14:57:43 -04:00
Thomas Harte
3a02c22072
Provide an always-16bit-address route to the stack.
2023-07-30 16:25:51 -04:00
Thomas Harte
0f1468adfd
Correct wrapping behaviour for (d, x).
2023-07-28 13:39:21 -04:00
Thomas Harte
e9347168e6
Don't alter the data bank upon BRK, COP, IRQ, etc.
2023-07-28 10:53:02 -04:00
Thomas Harte
28c79b2885
Eliminate redundant [space][tab] pairs.
2023-05-12 14:14:45 -04:00
Thomas Harte
ed2d4ebb0c
Fix test (and commentary) for shortened emulated branches.
2023-04-15 23:30:30 -04:00
Thomas Harte
107cb18df4
Fix perceives S in emulated stack-relative mode.
2023-04-14 00:04:44 -04:00
Thomas Harte
98d3da62b5
Apply E mode wrap for d,x and d,y only when DL = 0.
2022-09-09 16:02:35 -04:00
Thomas Harte
4ddbf095f3
Fully banish flush from the processors.
2022-07-12 10:49:53 -04:00
Thomas Harte
c2938a4f63
Avoid potential classic macro error with address.
2022-06-29 15:09:52 -04:00
Thomas Harte
4467eb1c41
Ensure relevant throwaway stack reads use the previous stack address.
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TODO: can CycleFetchPreviousThrowaway be used more widely?
2022-06-24 14:00:03 -04:00
Thomas Harte
069a057a94
Resolve assumption of arithmetic shifts.
2022-06-24 07:26:07 -04:00
Thomas Harte
4ed3b21bf3
Decimal SBC tweak: negative partial results don't cause carry.
2022-06-23 21:58:09 -04:00
Thomas Harte
da552abf75
Fix BIT overflow flag.
2022-06-23 15:24:51 -04:00
Thomas Harte
380b5141fb
Be overt about conversion wanted here.
2022-06-23 13:03:26 -04:00
Thomas Harte
66775b2c4e
Always consume a second cycle in 16-bit mode.
2022-06-23 12:46:51 -04:00
Thomas Harte
2c12a7d968
Make absolutely sure there's no address bit 24.
2022-06-23 12:12:02 -04:00
Thomas Harte
5a97c09238
Flip internal presumption on the BRK flag.
2022-06-23 11:23:00 -04:00
Thomas Harte
3112376943
Don't include DBR in direct indexed indirect.
2022-06-23 11:03:37 -04:00
Thomas Harte
a72dd96dc6
Page boundary crossing is free outside of emulation mode.
2022-06-22 15:31:30 -04:00
Thomas Harte
76767110b7
Fix overflow for 8-bit calculations; essentially a revert for ADC.
2022-06-22 15:18:47 -04:00
Thomas Harte
7dcfa9eb65
65816: improve decimal calculations, posted IO addresses, read/write during redundant read-modify-write cycle.
2022-06-21 14:33:06 -04:00
Thomas Harte
ec98736bd7
Ensure IO cycles don't produce an address of (PC+1).
2022-06-21 11:41:05 -04:00
Thomas Harte
586ef4810b
Add restart_operation_fetch, to aid with testing.
2022-06-18 16:25:57 -04:00
Thomas Harte
c8471eb993
Adds various asserts, some comments.
2021-03-03 20:47:45 -05:00
Thomas Harte
f6466fd657
Remove temporary hackery.
2021-02-19 22:47:50 -05:00
Thomas Harte
72d7901c88
Takes a shot at the keyboard data full flag.
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Just a guess. But likely?
2021-02-19 20:06:12 -05:00
Thomas Harte
992ee6d631
Don't zero out the program bank until after it has headed stackward.
2021-02-17 22:08:08 -05:00
Thomas Harte
3c887aff95
Improves consistency.
2021-01-21 18:58:22 -05:00
Thomas Harte
e0b36c9c3d
Corrects PBR/DBR resetting upon an exception.
2020-12-29 15:27:49 -05:00
Thomas Harte
574a37814c
Attempts to fix exception selection and timing.
2020-12-08 18:46:30 -05:00
Thomas Harte
c72bdd776e
Adds a new assert: I think this is the issue getting into GS/OS.
2020-12-07 22:43:24 -05:00
Thomas Harte
8ace258fbc
Tackles outstanding GCC warnings.
2020-11-22 21:43:56 -05:00
Thomas Harte
cdacf280e1
After much extra logging, corrects destination bank for MVN and MVP.
2020-11-15 16:08:29 -05:00
Thomas Harte
d3c7253981
Shifts size-limiting of X and Y to transitions and mutations, away from reads.
...
Primarily to remove potential bug-causing complexity — this is easier to debug. But let's see.
2020-11-04 20:35:41 -05:00
Thomas Harte
d50b059a17
Imports 6502-esque test for decimal SBC overflow.
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All applicable krom tests now pass.
2020-11-03 20:37:30 -05:00
Thomas Harte
cc5ec78156
Provides something on WAI/STP; sizes STY by the x flag; disables MSC test.
2020-11-03 20:17:44 -05:00
Thomas Harte
5cbb91f352
Fixes COP vector, ensures WDM skips a byte.
2020-11-03 20:01:02 -05:00
Thomas Harte
91ea2eff4c
Corrects MVN/MVP off-by-one and failure to store what was read.
2020-11-03 18:29:35 -05:00
Thomas Harte
bf85d71674
Brings ADC into conformance. Fixes JML.
2020-11-03 18:12:10 -05:00
Thomas Harte
7f3f6c339f
Corrects stacked program bank during native-mode exceptions.
2020-10-30 20:11:39 -04:00
Thomas Harte
1df2ce513a
Ensures that reset doesn't push to the stack.
2020-10-28 21:23:35 -04:00
Thomas Harte
1e4679ae14
Corrects JSL and RTL.
2020-10-28 17:25:40 -04:00
Thomas Harte
b3ab9fff9b
Imports a custom-built copy of Klaus Dormann's 65C02 test, with only 65816-compatible parts.
...
Thereby fixes another couple of 65816 issues — BRK(, etc) not clearing the decimal flag, and `TRB d` being mismapped.
2020-10-19 19:27:16 -04:00
Thomas Harte
76d9893866
Declares address-bus sizes formally.
...
This allows me to fix the final two implicit conversion warnings, albeit that it would have been nice to find a templatey way just to get the type directly from the declaration of `perform_bus_operation`.
2020-10-18 15:08:21 -04:00
Thomas Harte
c3f8982c62
Resolves all internal implicit type-conversion warnings.
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Chasing those down, it looks like flags were wrong for PLB and PLD. So it's official: warnings help.
2020-10-18 14:55:17 -04:00
Thomas Harte
99eba2f8ba
Ensures intended 65816 exception behaviour.
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i.e. the relevant micro-op sequence exists, and its operation isn't lost. Also sets the 65816 by default to jump straight into power-on, not to execute an instruction first. That shouldn't make a functional difference, but it makes debugging easier because it makes startup fully deterministic.
2020-10-18 14:43:47 -04:00
Thomas Harte
3b398f7a9a
Attempts to complete all 65816 bus signalling.
2020-10-16 21:56:20 -04:00
Thomas Harte
096add7551
Exposes non-BusOperation bus outputs.
2020-10-16 21:05:42 -04:00
