2848 Commits

Author	SHA1	Message	Date
Thomas Harte	2f78a1c7af	Add SCSI controller inclusion logic.	2022-09-15 12:17:50 -04:00
Thomas Harte	dc35ec8fa0	Merge branch 'master' into AppleIISCSI	2022-09-15 12:05:58 -04:00
Thomas Harte	36c3cb1f70	Deal with pre-ROM03 case, now that it's easy.	2022-09-13 16:31:06 -04:00
Thomas Harte	6773a321c1	Switch to portable direct bitwise logic.	2022-09-13 16:02:49 -04:00
Thomas Harte	ffdf44ad4f	Switch to overt use of std::fill.	2022-09-13 15:39:17 -04:00
Thomas Harte	cbfd8e18e8	Eliminate repetitive magic constants.	2022-09-02 15:54:16 -04:00
Thomas Harte	8dc1aca67c	Add TODO shout-outs.	2022-08-31 21:20:08 -04:00
Thomas Harte	df29a50738	Attempt to support the DMA interface.	2022-08-31 15:33:48 -04:00
Thomas Harte	7996fe6dab	'Clock' the SCSI bus (i.e. make it aware of passing time).	2022-08-30 16:40:25 -04:00
Thomas Harte	4df2a29a1f	Add storage to the bus.	2022-08-24 15:23:50 -04:00
Thomas Harte	6010c971a1	Provide a volume to the SCSI card if one is received.	2022-08-23 15:11:56 -04:00
Thomas Harte	ea4bf5f31a	Provide card's SCSI ID.	2022-08-23 15:05:36 -04:00
Thomas Harte	f4c242d5e9	Attempt to offer centralised C8 region decoding.	2022-08-23 14:50:44 -04:00
Thomas Harte	0595773355	Invents a new virtual select line for extended handling card ROM areas.	2022-08-23 14:41:45 -04:00
Thomas Harte	f89ca84902	Add missing include.	2022-08-22 21:44:33 -04:00
Thomas Harte	246bd5a6ac	Merge branch 'master' into AppleIISCSI	2022-08-22 17:09:57 -04:00
Thomas Harte	3c2d01451a	Remove dead comment.	2022-08-22 17:01:52 -04:00
Thomas Harte	c2c81162a1	Sketch out some of the easy stuff.	2022-08-22 16:48:51 -04:00
Thomas Harte	3d234147a6	Add in collected specs.	2022-08-22 10:22:19 -04:00
Thomas Harte	8e7f53751d	Add Apple II SCSI ROM to the catalogue.	2022-08-21 22:03:52 -04:00
Thomas Harte	bfc77f1606	Add workaround that further isolates whatever bug Spindizzy reveals.	2022-08-19 16:38:42 -04:00
Thomas Harte	a6b8285d9c	Factor out the blitter sequencer.	2022-08-19 16:38:15 -04:00
Thomas Harte	837acdcf60	Experimentally decline immediate blits.	2022-08-16 21:51:13 -04:00
Thomas Harte	7289192130	Fix refresh slots: they're taken, not open.	2022-08-16 21:51:02 -04:00
Thomas Harte	bb54ac14b8	Prove that new output errors are [probably] external to the Blitter.	2022-08-15 11:10:17 -04:00
Thomas Harte	856e3d97bf	Merge branch 'master' into SerialisedBlitter	2022-08-15 10:54:36 -04:00
Thomas Harte	94231ca3e3	Put word-sizing responsibility on the caller.	2022-08-10 16:41:45 -04:00
Thomas Harte	e2a8b26b57	Display properly from greater RAM sizes.	2022-08-10 16:36:11 -04:00
Thomas Harte	6d1c954623	Make ST RAM size selectable, default to 1MB.	2022-08-10 12:00:06 -04:00
Thomas Harte	bdb35b6191	Add an easier hook for debugging.	2022-08-08 21:00:28 -04:00
Thomas Harte	892580c183	Clarify test.	2022-08-08 15:57:36 -04:00
Thomas Harte	d4b7d73fc4	Further reduces lines to one access per slot, max.	2022-08-07 19:19:00 -04:00
Thomas Harte	867769f6e7	Reduces line drawing to two accesses per slot. ... Still a fiction, but a better one.	2022-08-07 19:15:03 -04:00
Thomas Harte	3781b5eb0e	Provide further context.	2022-08-06 14:40:12 -04:00
Thomas Harte	318cea4ccd	Attempt a full bus-transaction comparison.	2022-08-06 10:06:49 -04:00
Thomas Harte	45892f3584	Add optional transaction records to the Blitter.	2022-08-06 09:51:20 -04:00
Thomas Harte	612413cb1c	Remove redundant state.	2022-08-04 10:06:14 -04:00
Thomas Harte	511ec5a736	Apply modulos at end of final line. ... Possibly I need to rethink the sequence logic?	2022-07-30 21:35:26 -04:00
Thomas Harte	4fb9dec381	Fix use of bool.	2022-07-30 21:02:44 -04:00
Thomas Harte	82476bdabe	Avoid 'complete' repetition.	2022-07-30 21:02:04 -04:00
Thomas Harte	58ee8e2460	Minor tidy-up. No fixes.	2022-07-30 21:00:50 -04:00
Thomas Harte	94a90b7a89	Attempt a real slot-by-slot blit.	2022-07-30 20:34:37 -04:00
Thomas Harte	5d992758f8	Ensure blitter with all flags disabled terminates.	2022-07-30 20:13:37 -04:00
Thomas Harte	27b8c29096	Apply modulos at end of line, not beginning.	2022-07-30 10:27:53 -04:00
Thomas Harte	93d2a612ee	Add an explicit flush-pipeline step; some tests now pass.	2022-07-29 16:33:46 -04:00
Thomas Harte	03d4960a03	Begin a full-synchronous usage of the sequencer, at least exposing poor handling of the pipeline.	2022-07-29 16:15:18 -04:00
Thomas Harte	1ac0a4e924	Provide a loop count directly from the sequencer. ... This avoids the caller having to take a guess at iterations.	2022-07-29 12:14:59 -04:00
Thomas Harte	d85d70a133	Add documentation, formal begin function.	2022-07-26 22:01:43 -04:00
Thomas Harte	2c95dea4db	Introduce putative blitter sequencer.	2022-07-26 17:05:05 -04:00
Thomas Harte	804c12034c	Apply blitter priority bit.	2022-07-26 16:07:26 -04:00