Thomas Harte
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e3e461d7cb
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Added a test class for running the FUSE tests. With nothing much in it.
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2017-05-21 22:49:24 -04:00 |
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Thomas Harte
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c16fccb317
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Fixed file names.
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2017-05-21 22:43:07 -04:00 |
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Thomas Harte
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b9cffdf2bd
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Imported the FUSE tests.
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2017-05-21 22:42:20 -04:00 |
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Thomas Harte
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f2aae72cc2
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Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least.
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2017-05-21 20:43:36 -04:00 |
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Thomas Harte
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fe8db1873c
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Added 16-bit ADC and SBC table entries; once again extended logging.
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2017-05-21 20:32:06 -04:00 |
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Thomas Harte
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c66c715ac9
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Starts to try to figure out how to implemented the index register pages, but doesn't yet read offsets.
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2017-05-21 19:26:40 -04:00 |
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Thomas Harte
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5dcfd85642
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Added a compact and copy stage for instruction pages, both [mostly] eliminating the mistake of letting static data structures contain pointers to instance storage and opening the door for addition of the DD and FD pages.
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2017-05-21 19:15:52 -04:00 |
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Thomas Harte
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c70dfe1b09
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Implemented the two variations of loading between (nn) and SP.
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2017-05-21 13:20:28 -04:00 |
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Thomas Harte
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232c591655
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Threw in a little macro documentation and a missing macro.
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2017-05-21 13:13:21 -04:00 |
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Thomas Harte
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790614b544
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Added EI and DI.
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2017-05-21 12:53:17 -04:00 |
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Thomas Harte
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32c032cd97
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Implemented a couple of easy-to-add missing base page instructions.
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2017-05-21 10:18:43 -04:00 |
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Thomas Harte
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e48ee16366
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Continued cleaning efforts, added conditional RET.
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2017-05-21 10:13:59 -04:00 |
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Thomas Harte
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e92d936ce8
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Added conditional calls.
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2017-05-21 10:03:46 -04:00 |
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Thomas Harte
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4e210c5396
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Added LD A, (nn).
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2017-05-21 10:00:10 -04:00 |
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Thomas Harte
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3d3e60b1fc
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Implemented LD (HL), r.
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2017-05-21 09:56:41 -04:00 |
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Thomas Harte
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f3f0e2f1a9
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Implemented RRA and RRCA.
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2017-05-21 09:52:19 -04:00 |
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Thomas Harte
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08206eea56
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This logging has outlived its usefulness for now.
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2017-05-21 09:47:53 -04:00 |
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Thomas Harte
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78296246e8
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Added ALU n.
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2017-05-21 09:46:18 -04:00 |
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Thomas Harte
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85b5dd35b1
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Took a shot at 8-bit arithmetic.
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2017-05-21 09:43:17 -04:00 |
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Thomas Harte
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11cfaa3e3d
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Performed light syntactic cleaning on the first part of the base page table, eliminated redundant temporary variables, implemented 8-bit increment and decrement.
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2017-05-21 09:17:30 -04:00 |
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Thomas Harte
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103c863534
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Through temporarily dramatically increased logging, fixed conditional JP.
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2017-05-20 23:03:52 -04:00 |
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Thomas Harte
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6688f83226
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Took a shot at LDIR.
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2017-05-20 21:58:24 -04:00 |
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Thomas Harte
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01a064dd63
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Added an empty ED page.
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2017-05-20 17:29:30 -04:00 |
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Thomas Harte
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7b234078ae
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Implemented EX DE, HL and shuffled to allow instruction pages.
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2017-05-20 17:04:25 -04:00 |
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Thomas Harte
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add02a7897
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Added LD (nn), A, and reduced double logging to single for now.
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2017-05-19 23:13:28 -04:00 |
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Thomas Harte
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19167df692
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Consolidated and filled in AND and XOR.
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2017-05-19 23:03:34 -04:00 |
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Thomas Harte
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6766845e21
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Filled in most of the loads.
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2017-05-19 22:57:43 -04:00 |
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Thomas Harte
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bc3b5f3e35
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Added 16-bit INCs and DECs. Which don't set flags, so are easy.
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2017-05-19 22:13:36 -04:00 |
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Thomas Harte
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5fe23113ec
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Moved RET to the correct place, implemented POP AF.
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2017-05-19 22:03:12 -04:00 |
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Thomas Harte
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c55e1c1d17
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Implemented POP and therefore RET; corrected timing of PUSH.
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2017-05-19 21:59:45 -04:00 |
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Thomas Harte
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d910405648
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Added enough infrastructure to be able to react to the two CP/M calls this cares about.
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2017-05-19 21:53:39 -04:00 |
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Thomas Harte
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62b432c046
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Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
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2017-05-19 21:20:28 -04:00 |
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Thomas Harte
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eae1f78221
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Implemented the main page pushes.
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2017-05-19 19:28:38 -04:00 |
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Thomas Harte
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11d05fb3b8
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Expanded a little on operations, added an implementation or two.
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2017-05-19 19:18:35 -04:00 |
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Thomas Harte
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58efca835f
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Sought to add a further opcode.
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2017-05-18 22:53:43 -04:00 |
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Thomas Harte
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da6e520b91
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Merge branch 'master' into Z80
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2017-05-18 22:30:51 -04:00 |
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Thomas Harte
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a5099f69d8
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Merge pull request #127 from TomHarte/OricShift
Maps either Mac shift key to both Oric shifts
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2017-05-18 22:27:47 -04:00 |
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Thomas Harte
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9398b6c2c8
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Unable to differentiate, decided to map a Mac shift key to both Oric shifts.
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2017-05-18 22:25:59 -04:00 |
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Thomas Harte
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99f2060fc1
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Further improved macros.
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2017-05-18 22:11:54 -04:00 |
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Thomas Harte
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5d3ebcb35a
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Made a first attempt at LD HL, (nn).
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2017-05-17 22:42:30 -04:00 |
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Thomas Harte
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509d011fbe
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Implemented JP, my first Z80 operation.
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2017-05-17 22:31:41 -04:00 |
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Thomas Harte
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17ffd604bf
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Made an attempt to get the Z80 at least as far as rejecting an opcode.
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2017-05-17 21:45:23 -04:00 |
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Thomas Harte
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a3dafa9056
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Abbreviated uses of enumerations.
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2017-05-17 21:44:08 -04:00 |
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Thomas Harte
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21d0602305
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Restored the all RAM 6502's lack of power-on reset.
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2017-05-17 21:43:40 -04:00 |
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Thomas Harte
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64d6ee1be5
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Adjusted slightly to adapt to latest Swift warnings.
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2017-05-17 07:49:48 -04:00 |
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Thomas Harte
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1378ab7278
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Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access.
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2017-05-17 07:36:06 -04:00 |
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Thomas Harte
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87a021ec2d
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Made further attempt to get as fas as having the Z80 attempt to do something.
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2017-05-16 22:19:40 -04:00 |
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Thomas Harte
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189317b80c
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Added enough of a Z80 test machine to bridge up into Swift.
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2017-05-16 22:05:42 -04:00 |
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Thomas Harte
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4f0775cc7c
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Imported the Zexall.com tester, as a first thing to throw at the Z80 to be.
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2017-05-16 21:37:09 -04:00 |
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Thomas Harte
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7190f927b7
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Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
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2017-05-16 21:28:17 -04:00 |
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