6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-04 15:05:36 +00:00
Code Issues Projects Releases Wiki Activity
9,298 Commits 8 Branches 121 Tags 496 MiB
a59ad06438
Commit Graph

9298 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Thomas Harte
c367ddff1b Merge branch '68000Mk2' into InMacintosh 2022-05-27 10:34:11 -04:00
Thomas Harte
67b340fa5e Fix interrupt request address. 2022-05-27 10:33:36 -04:00
Thomas Harte
c97245e626 Fix CalcEA timing; make MOVEfromSR a read-modify-write. 2022-05-27 10:32:28 -04:00
Thomas Harte
79e2c17f93 Fix interrupt request address. 2022-05-26 20:20:28 -04:00
Thomas Harte
5937737bb7 Merge branch '68000Mk2' into InMacintosh 2022-05-26 19:37:44 -04:00
Thomas Harte
5f030edea4 Simplify transaction. 2022-05-26 19:37:30 -04:00
Thomas Harte
88e33353a1 Fix instruction and time counting, and initial state. 2022-05-26 09:17:37 -04:00
Thomas Harte
f3c0c62c79 Switch register-setting interface. 2022-05-26 07:52:14 -04:00
Thomas Harte
866787c5d3 Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence. 2022-05-25 20:22:38 -04:00
Thomas Harte
367ad8079a Add a call to set register state with population of the prefetch. 2022-05-25 20:22:05 -04:00
Thomas Harte
64491525b4 Work further to guess at caller's intention for set_state. 
Probably I should just eliminate the initial reset, somehow.
 2022-05-25 17:01:18 -04:00
Thomas Harte
68b184885f Reapply only the status. 2022-05-25 16:54:25 -04:00
Thomas Harte
06f3c716f5 Make better effort to establish initial state. 2022-05-25 16:47:41 -04:00
Thomas Harte
22714b8c7f Capture state at instruction end, for potential inspection. 2022-05-25 16:32:26 -04:00
Thomas Harte
80c1bedffb Eliminate false prefetch for BSR. 2022-05-25 16:32:02 -04:00
Thomas Harte
56ad6d24ee Fix ANDI/ORI/EORI to CCR/SR timing. 2022-05-25 16:20:26 -04:00
Thomas Harte
4ad0e04c23 Fix macro for n being an expression. 2022-05-25 16:05:45 -04:00
Thomas Harte
f9d1c554b7 Fix for the actual number of cycles in a standard reset. 2022-05-25 16:05:28 -04:00
Thomas Harte
ee58301a46 Add RaiseException macro. 2022-05-25 15:45:09 -04:00
Thomas Harte
f2a7660390 Merge branch 'master' into 68000Mk2 2022-05-25 15:40:10 -04:00
Thomas Harte
d4c7ce2d6f
Merge pull request #1035 from TomHarte/68000TestIssues 
Add details on gaps in coverage.
 2022-05-25 15:39:42 -04:00
Thomas Harte
4961e39fb6 Mention DIVU/DIVS flags. 2022-05-25 15:39:00 -04:00
Thomas Harte
0bedf608c0 Add details on gaps in coverage. 2022-05-25 15:36:27 -04:00
Thomas Harte
1ab831f571 Add the option to log a list of all untested instructions. 2022-05-25 13:17:01 -04:00
Thomas Harte
b90f1a48ce Merge branch '68000Mk2' into InMacintosh 2022-05-25 13:02:44 -04:00
Thomas Harte
72425fc2e1 Fix bus data size of MOVE.b xx, -(An). 2022-05-25 13:00:36 -04:00
Thomas Harte
a5f2dfbc0c Initialise registers to 0 for better testability. 
TODO: is this the real initial state?
 2022-05-25 11:47:42 -04:00
Thomas Harte
5db6a937cb Have TRAP and TRAPV push the next instruction address to the stack. 2022-05-25 11:47:21 -04:00
Thomas Harte
9709b9b1b1 Standard exceptions don't raise the interrupt level. 2022-05-25 11:37:39 -04:00
Thomas Harte
2c6b9b4c9d Switch comparative trace tests to 68000 Mk2. 2022-05-25 11:32:00 -04:00
Thomas Harte
463fbb07f9 Adapt remaining 68000 tests to use Mk2. 2022-05-25 10:55:17 -04:00
Thomas Harte
b6e473a515 Adapt remaining 68000 tests to use Mk2. 2022-05-25 10:55:03 -04:00
Thomas Harte
24f7b5806c Merge branch '68000Mk2' into InMacintosh 2022-05-25 08:15:41 -04:00
Thomas Harte
5872e0ea4a Resolve MOVE.l xx, -(An) write target. 2022-05-25 08:15:18 -04:00
Thomas Harte
04d2d6012a Merge branch '68000Mk2' into InMacintosh 2022-05-24 16:08:56 -04:00
Thomas Harte
f43d27541b Avoid attempt to establish operand flags for undefined opcodes. 2022-05-24 15:53:12 -04:00
Thomas Harte
c8d3d980ba Avoid attempt to establish operand flags for undefined opcodes. 2022-05-24 15:52:53 -04:00
Thomas Harte
f93bf06b99 Merge branch '68000Mk2' into InMacintosh 2022-05-24 15:51:22 -04:00
Thomas Harte
0f7cb2fa5a Attempt to honour the trace flag. 2022-05-24 15:47:47 -04:00
Thomas Harte
01e93ba916 Make an attempt at bus/address error. 2022-05-24 15:42:50 -04:00
Thomas Harte
780954f27b Add TRAP, TRAPV. 2022-05-24 15:14:46 -04:00
Thomas Harte
19d69bdbb5 Add TRAP, TRAPV. 2022-05-24 15:14:20 -04:00
Thomas Harte
27fac7af86 Merge branch '68000Mk2' into InMacintosh 2022-05-24 12:48:54 -04:00
Thomas Harte
6f048de973 Pull unrecognised instruction handling into the usual switch table. 2022-05-24 12:42:34 -04:00
Thomas Harte
a611a745e7 Switch the Macintosh to 68000 mk2. 2022-05-24 12:35:36 -04:00
Thomas Harte
0dfaa7d9cf Interrupt fixes: supply proper address, raise level, fetch from vector. 2022-05-24 12:16:06 -04:00
Thomas Harte
eab720f6ea Ensure proper transition from unrecognised instructions. 2022-05-24 12:16:00 -04:00
Thomas Harte
8ad1d6b813 Interrupt fixes: supply proper address, raise level, fetch from vector. 2022-05-24 12:15:35 -04:00
Thomas Harte
be684d66fd Ensure proper transition from unrecognised instructions. 2022-05-24 11:36:11 -04:00
Thomas Harte
a7e8aef9d3 Add MOVEA, be slightly more careful about next_operand_. 2022-05-24 11:30:09 -04:00