136 Commits

Author	SHA1	Message	Date
Thomas Harte	b312a61a81	Add two dummy reads.	2021-10-16 13:30:45 -07:00
Thomas Harte	4917556a99	The shift goes the other way in descending mode.	2021-10-16 11:09:40 -07:00
Thomas Harte	aa6b0f07b7	Correct filename.	2021-10-16 05:37:46 -07:00
Thomas Harte	e27a10bde4	Simplify control flow.	2021-10-14 16:47:18 -07:00
Thomas Harte	253a199f27	Fire sync-match interrupt upon any match.	2021-10-14 16:36:17 -07:00
Thomas Harte	61e5702520	Remove dead TODO.	2021-10-14 16:09:11 -07:00
Thomas Harte	b12c640807	Makes drives non-copyable. ... To avoid error in the future.	2021-10-14 12:37:55 -07:00
Thomas Harte	9be23ecc34	Add end-of-Blit interrupt. ... Along with a slightly easier path for posting interrupts, in C++ compilation unit terms.	2021-10-13 15:09:19 -07:00
Thomas Harte	eec068914e	Slightly improve logging.	2021-10-11 18:05:57 -07:00
Thomas Harte	39b8285ba5	Trust the HRM on step bit, but catch rising edge.	2021-10-11 07:42:42 -07:00
Thomas Harte	7733fef3bd	DSKLEN has to be written twice.	2021-10-11 06:16:01 -07:00
Thomas Harte	6acddfdb98	Add the sync match interrupt. ... Albeit that it doesn't yet unblock disk DMA.	2021-10-11 03:37:56 -07:00
Thomas Harte	99492c2ec2	Further tweak logging.	2021-10-10 18:19:50 -07:00
Thomas Harte	846b505d27	Reduce logging; disk data probably isn't the immediate obstacle.	2021-10-10 13:04:10 -07:00
Thomas Harte	8d43b4a98d	Expands Disk DMA access window.	2021-10-10 11:47:02 -07:00
Thomas Harte	9336ffe216	Take a stab at index-hole sync.	2021-10-09 08:01:02 -07:00
Thomas Harte	eb157f15f3	Adds index hole interrupt.	2021-10-09 04:08:59 -07:00
Thomas Harte	d6e2a3f425	Make a first attempt to spool into RAM.	2021-10-08 18:11:47 -07:00
Thomas Harte	b47ca13ed3	Push disk data onwards.	2021-10-08 17:18:11 -07:00
Thomas Harte	67546c4d6e	Per the HRM, the index hole is connected to CIA B, potentially to raise an interrupt.	2021-10-08 17:12:37 -07:00
Thomas Harte	f72deb0a5c	Correct RDY position.	2021-10-08 04:32:13 -07:00
Thomas Harte	616ccbb878	Correct ID bit placement, multiplex with motor state. ... The latter per my reading of http://www.primrosebank.net/computers/amiga/upgrades/amiga_upgrades_storage_fdis.htm	2021-10-08 04:05:57 -07:00
Thomas Harte	5899af0038	Starts accumulating disk data.	2021-10-07 05:11:32 -07:00
Thomas Harte	33ff4f3b5c	Eliminate drive copies.	2021-10-06 13:40:28 -07:00
Thomas Harte	20bad38d42	Add drive activity lights.	2021-10-06 04:54:40 -07:00
Thomas Harte	92a07398cd	I think CHNG works the other way around.	2021-10-06 04:47:52 -07:00
Thomas Harte	e961d0b4a3	Switch RDY type.	2021-10-06 04:41:09 -07:00
Thomas Harte	2253ff656a	Adds route for inserting disks.	2021-10-05 16:12:30 -07:00
Thomas Harte	18631399ad	Attempts to clock the disk controller.	2021-10-05 15:38:56 -07:00
Thomas Harte	ad4afcdcd5	Switch stepping direction. ... Empirically, based on the actions of Kickstart, and assuming my confusion is because the relevant signal is active low.	2021-10-05 15:23:48 -07:00
Thomas Harte	2cf5bcc5db	Clarify logic somewhat.	2021-10-05 15:20:05 -07:00
Thomas Harte	1180ad7662	Disables a couple of now-trustworthy LOGs.	2021-10-05 06:51:47 -07:00
Thomas Harte	5463cd1ae3	Attempts to support stepping and head selection.	2021-10-05 06:36:17 -07:00
Thomas Harte	647ec770ce	Implements motor latching, drive ID shift registers.	2021-10-05 05:12:01 -07:00
Thomas Harte	e47bec2e65	Switch CIA B ports over.	2021-10-05 03:38:11 -07:00
Thomas Harte	674941abdf	Starts to add a disk controller.	2021-10-04 16:45:05 -07:00
Thomas Harte	b3f0ca39ed	Adds some unused drives.	2021-10-04 08:12:13 -07:00
Thomas Harte	5ccb512883	Moves the CIAs into the Chipset class. ... This reflects the routing of interrupt signals for now, but also prepares for the addition of disk drives.	2021-10-04 06:44:54 -07:00
Thomas Harte	a282a51673	Remove last of the direct printf'ing.	2021-09-30 02:42:59 -04:00
Thomas Harte	b7b13e20d1	Single column blits should use both masks.	2021-09-29 22:49:35 -04:00
Thomas Harte	402fa41bc0	Corrects initial error value.	2021-09-29 22:19:17 -04:00
Thomas Harte	0b9ebafc0f	Flip bit deserialisation order.	2021-09-28 22:12:13 -04:00
Thomas Harte	140e24ef15	Grab further copy flags.	2021-09-28 22:11:58 -04:00
Thomas Harte	ffcd2ea10c	Attempts more properly to implement line mode.	2021-09-28 21:39:09 -04:00
Thomas Harte	cb460de94d	Makes bad first attempt at a Bresenham inner loop.	2021-09-27 22:06:00 -04:00
Thomas Harte	f6624bf776	Edges mildly closer to line output.	2021-09-26 19:18:12 -04:00
Thomas Harte	b4b6c4d86f	Attempts to support left and right masks.	2021-09-26 18:42:08 -04:00
Thomas Harte	759689ff31	Fix line mode flag, add busy status.	2021-09-26 18:16:00 -04:00
Thomas Harte	c4ab2bbeed	Hard-code fetch window width. For now.	2021-09-23 22:06:13 -04:00
Thomas Harte	42ef459e20	Resolve resting values.	2021-09-23 22:05:59 -04:00