112 Commits

Author	SHA1	Message	Date
Thomas Harte	c66c715ac9	Starts to try to figure out how to implemented the index register pages, but doesn't yet read offsets.	2017-05-21 19:26:40 -04:00
Thomas Harte	5dcfd85642	Added a compact and copy stage for instruction pages, both [mostly] eliminating the mistake of letting static data structures contain pointers to instance storage and opening the door for addition of the DD and FD pages.	2017-05-21 19:15:52 -04:00
Thomas Harte	c70dfe1b09	Implemented the two variations of loading between (nn) and SP.	2017-05-21 13:20:28 -04:00
Thomas Harte	232c591655	Threw in a little macro documentation and a missing macro.	2017-05-21 13:13:21 -04:00
Thomas Harte	790614b544	Added EI and DI.	2017-05-21 12:53:17 -04:00
Thomas Harte	32c032cd97	Implemented a couple of easy-to-add missing base page instructions.	2017-05-21 10:18:43 -04:00
Thomas Harte	e48ee16366	Continued cleaning efforts, added conditional RET.	2017-05-21 10:13:59 -04:00
Thomas Harte	e92d936ce8	Added conditional calls.	2017-05-21 10:03:46 -04:00
Thomas Harte	4e210c5396	Added LD A, (nn).	2017-05-21 10:00:10 -04:00
Thomas Harte	3d3e60b1fc	Implemented LD (HL), r.	2017-05-21 09:56:41 -04:00
Thomas Harte	f3f0e2f1a9	Implemented RRA and RRCA.	2017-05-21 09:52:19 -04:00
Thomas Harte	08206eea56	This logging has outlived its usefulness for now.	2017-05-21 09:47:53 -04:00
Thomas Harte	78296246e8	Added ALU n.	2017-05-21 09:46:18 -04:00
Thomas Harte	85b5dd35b1	Took a shot at 8-bit arithmetic.	2017-05-21 09:43:17 -04:00
Thomas Harte	11cfaa3e3d	Performed light syntactic cleaning on the first part of the base page table, eliminated redundant temporary variables, implemented 8-bit increment and decrement.	2017-05-21 09:17:30 -04:00
Thomas Harte	103c863534	Through temporarily dramatically increased logging, fixed conditional JP.	2017-05-20 23:03:52 -04:00
Thomas Harte	6688f83226	Took a shot at LDIR.	2017-05-20 21:58:24 -04:00
Thomas Harte	01a064dd63	Added an empty ED page.	2017-05-20 17:29:30 -04:00
Thomas Harte	7b234078ae	Implemented EX DE, HL and shuffled to allow instruction pages.	2017-05-20 17:04:25 -04:00
Thomas Harte	add02a7897	Added LD (nn), A, and reduced double logging to single for now.	2017-05-19 23:13:28 -04:00
Thomas Harte	19167df692	Consolidated and filled in AND and XOR.	2017-05-19 23:03:34 -04:00
Thomas Harte	6766845e21	Filled in most of the loads.	2017-05-19 22:57:43 -04:00
Thomas Harte	bc3b5f3e35	Added 16-bit INCs and DECs. Which don't set flags, so are easy.	2017-05-19 22:13:36 -04:00
Thomas Harte	5fe23113ec	Moved RET to the correct place, implemented POP AF.	2017-05-19 22:03:12 -04:00
Thomas Harte	c55e1c1d17	Implemented POP and therefore RET; corrected timing of PUSH.	2017-05-19 21:59:45 -04:00
Thomas Harte	d910405648	Added enough infrastructure to be able to react to the two CP/M calls this cares about.	2017-05-19 21:53:39 -04:00
Thomas Harte	62b432c046	Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.	2017-05-19 21:20:28 -04:00
Thomas Harte	eae1f78221	Implemented the main page pushes.	2017-05-19 19:28:38 -04:00
Thomas Harte	11d05fb3b8	Expanded a little on operations, added an implementation or two.	2017-05-19 19:18:35 -04:00
Thomas Harte	58efca835f	Sought to add a further opcode.	2017-05-18 22:53:43 -04:00
Thomas Harte	99f2060fc1	Further improved macros.	2017-05-18 22:11:54 -04:00
Thomas Harte	5d3ebcb35a	Made a first attempt at LD HL, (nn).	2017-05-17 22:42:30 -04:00
Thomas Harte	509d011fbe	Implemented JP, my first Z80 operation.	2017-05-17 22:31:41 -04:00
Thomas Harte	17ffd604bf	Made an attempt to get the Z80 at least as far as rejecting an opcode.	2017-05-17 21:45:23 -04:00
Thomas Harte	21d0602305	Restored the all RAM 6502's lack of power-on reset.	2017-05-17 21:43:40 -04:00
Thomas Harte	1378ab7278	Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access.	2017-05-17 07:36:06 -04:00
Thomas Harte	87a021ec2d	Made further attempt to get as fas as having the Z80 attempt to do something.	2017-05-16 22:19:40 -04:00
Thomas Harte	7190f927b7	Factored out the stuff that both all-RAM processors would share, rather than duplicating it.	2017-05-16 21:28:17 -04:00
Thomas Harte	d559d8b901	Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.	2017-05-16 21:19:17 -04:00
Thomas Harte	50bb4f0142	There's finally a loop in here, at least.	2017-05-15 22:25:52 -04:00
Thomas Harte	7da51602d5	Moved flush, added run_for_cycles, which does nothing right now.	2017-05-15 07:59:21 -04:00
Thomas Harte	5152517887	Added the boilerplate stuff necessary to query registers.	2017-05-15 07:55:53 -04:00
Thomas Harte	eb8a2de5d6	Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.	2017-05-15 07:38:59 -04:00
Thomas Harte	f2a1a906ff	Adapted what negligible amount there is of the z80 as per the new CPU namespace.	2017-05-14 22:15:16 -04:00
Thomas Harte	0808e9b6fb	Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.	2017-05-14 22:08:15 -04:00
Thomas Harte	b81a2cc273	First tentative steps towards adding a Z80 implementation.	2017-05-14 17:46:41 -04:00
Thomas Harte	defec2c9b0	Fixed: operation reads now fulfil the promise of seeding the value to be read with 0xff.	2017-03-26 20:56:27 -04:00
Thomas Harte	e01f3f06c8	Completed curly bracket movement.	2017-03-26 14:34:47 -04:00
Thomas Harte	55ce851bb2	Fixed types of the 8k cartridges, ensured the 6502 starts without an IRQ request history.	2017-03-18 17:04:01 -04:00
Thomas Harte	36b58d03b7	Formalised read bus value guarantee from the 6502, fixed missing clock signal wiring on the Atari cartridge class, reintroduced CommaVid support.	2017-03-18 14:46:46 -04:00