Thomas Harte
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f3c0c62c79
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Switch register-setting interface.
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2022-05-26 07:52:14 -04:00 |
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Thomas Harte
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866787c5d3
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Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence.
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2022-05-25 20:22:38 -04:00 |
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Thomas Harte
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367ad8079a
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Add a call to set register state with population of the prefetch.
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2022-05-25 20:22:05 -04:00 |
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Thomas Harte
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64491525b4
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Work further to guess at caller's intention for set_state.
Probably I should just eliminate the initial reset, somehow.
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2022-05-25 17:01:18 -04:00 |
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Thomas Harte
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68b184885f
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Reapply only the status.
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2022-05-25 16:54:25 -04:00 |
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Thomas Harte
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06f3c716f5
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Make better effort to establish initial state.
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2022-05-25 16:47:41 -04:00 |
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Thomas Harte
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22714b8c7f
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Capture state at instruction end, for potential inspection.
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2022-05-25 16:32:26 -04:00 |
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Thomas Harte
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80c1bedffb
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Eliminate false prefetch for BSR.
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2022-05-25 16:32:02 -04:00 |
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Thomas Harte
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56ad6d24ee
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Fix ANDI/ORI/EORI to CCR/SR timing.
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2022-05-25 16:20:26 -04:00 |
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Thomas Harte
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4ad0e04c23
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Fix macro for n being an expression.
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2022-05-25 16:05:45 -04:00 |
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Thomas Harte
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f9d1c554b7
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Fix for the actual number of cycles in a standard reset.
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2022-05-25 16:05:28 -04:00 |
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Thomas Harte
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ee58301a46
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Add RaiseException macro.
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2022-05-25 15:45:09 -04:00 |
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Thomas Harte
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f2a7660390
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Merge branch 'master' into 68000Mk2
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2022-05-25 15:40:10 -04:00 |
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Thomas Harte
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d4c7ce2d6f
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Merge pull request #1035 from TomHarte/68000TestIssues
Add details on gaps in coverage.
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2022-05-25 15:39:42 -04:00 |
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Thomas Harte
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4961e39fb6
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Mention DIVU/DIVS flags.
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2022-05-25 15:39:00 -04:00 |
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Thomas Harte
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0bedf608c0
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Add details on gaps in coverage.
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2022-05-25 15:36:27 -04:00 |
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Thomas Harte
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1ab831f571
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Add the option to log a list of all untested instructions.
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2022-05-25 13:17:01 -04:00 |
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Thomas Harte
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72425fc2e1
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Fix bus data size of MOVE.b xx, -(An).
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2022-05-25 13:00:36 -04:00 |
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Thomas Harte
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a5f2dfbc0c
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Initialise registers to 0 for better testability.
TODO: is this the real initial state?
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2022-05-25 11:47:42 -04:00 |
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Thomas Harte
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5db6a937cb
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Have TRAP and TRAPV push the next instruction address to the stack.
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2022-05-25 11:47:21 -04:00 |
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Thomas Harte
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9709b9b1b1
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Standard exceptions don't raise the interrupt level.
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2022-05-25 11:37:39 -04:00 |
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Thomas Harte
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2c6b9b4c9d
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Switch comparative trace tests to 68000 Mk2.
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2022-05-25 11:32:00 -04:00 |
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Thomas Harte
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463fbb07f9
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Adapt remaining 68000 tests to use Mk2.
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2022-05-25 10:55:17 -04:00 |
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Thomas Harte
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5872e0ea4a
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Resolve MOVE.l xx, -(An) write target.
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2022-05-25 08:15:18 -04:00 |
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Thomas Harte
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f43d27541b
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Avoid attempt to establish operand flags for undefined opcodes.
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2022-05-24 15:53:12 -04:00 |
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Thomas Harte
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0f7cb2fa5a
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Attempt to honour the trace flag.
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2022-05-24 15:47:47 -04:00 |
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Thomas Harte
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01e93ba916
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Make an attempt at bus/address error.
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2022-05-24 15:42:50 -04:00 |
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Thomas Harte
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780954f27b
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Add TRAP, TRAPV.
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2022-05-24 15:14:46 -04:00 |
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Thomas Harte
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6f048de973
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Pull unrecognised instruction handling into the usual switch table.
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2022-05-24 12:42:34 -04:00 |
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Thomas Harte
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0dfaa7d9cf
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Interrupt fixes: supply proper address, raise level, fetch from vector.
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2022-05-24 12:16:06 -04:00 |
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Thomas Harte
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eab720f6ea
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Ensure proper transition from unrecognised instructions.
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2022-05-24 12:16:00 -04:00 |
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Thomas Harte
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a7e8aef9d3
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Add MOVEA, be slightly more careful about next_operand_.
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2022-05-24 11:30:09 -04:00 |
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Thomas Harte
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4b07c41df9
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Ensure alignment of storage.
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2022-05-24 11:29:28 -04:00 |
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Thomas Harte
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df54f1f1b7
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Update TODO.
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2022-05-24 11:06:05 -04:00 |
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Thomas Harte
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9e3c2b68d7
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Eliminate potential future implicit conversion warnings.
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2022-05-24 11:05:24 -04:00 |
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Thomas Harte
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3349bcaaed
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Attempt interrupt support.
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2022-05-24 10:53:59 -04:00 |
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Thomas Harte
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3a4fb81242
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Add a dummy STOP state.
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2022-05-24 10:25:40 -04:00 |
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Thomas Harte
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1df3ad0671
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Ensure TAS responds to VPA, BERR.
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2022-05-24 09:17:58 -04:00 |
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Thomas Harte
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523cdd859b
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Add bus and address error, and VPA checks.
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2022-05-24 09:08:31 -04:00 |
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Thomas Harte
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b037c76da6
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Add public interface for everything except HALT and BUS REQ/etc.
... neither of which are used by machines I currently implement.
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2022-05-23 20:55:01 -04:00 |
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Thomas Harte
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9cac4ca317
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Add MOVE to/from USP.
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2022-05-23 20:42:41 -04:00 |
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Thomas Harte
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34e5f39571
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Ensure that running exactly up to a boundary gives the bus handler the next microcycle to contemplate.
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2022-05-23 15:11:33 -04:00 |
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Thomas Harte
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e0a279344c
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Codify the existence of special cases, implement NOP and RESET.
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2022-05-23 15:09:46 -04:00 |
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Thomas Harte
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e2f4db3e45
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Shuffle more of the flow controller methods into their proper place.
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2022-05-23 12:06:14 -04:00 |
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Thomas Harte
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cdb9eae1ee
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Merge branch 'master' into 68000Mk2
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2022-05-23 11:02:57 -04:00 |
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Thomas Harte
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c1837af84a
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Add notes to self on work remaining.
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2022-05-23 11:02:31 -04:00 |
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Thomas Harte
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a87f6a28c9
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Fix LINK A7.
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2022-05-23 10:43:17 -04:00 |
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Thomas Harte
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98325325b1
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Fix UNLINK A7.
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2022-05-23 10:27:44 -04:00 |
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Thomas Harte
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26bf66e3f8
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Fix shifts and rolls.
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2022-05-23 10:09:46 -04:00 |
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Thomas Harte
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363cd97154
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Resolve double definition of did_shift .
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2022-05-23 10:07:24 -04:00 |
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