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5,380 Commits 9 Branches 118 Tags 496 MiB
f86dc082bb
Commit Graph

1578 Commits

Author SHA1 Message Date
Thomas Harte
f86dc082bb Ensures serial lines know their writer's clock rate. 2019-10-13 20:41:08 -04:00
Thomas Harte
d7982aa84e JustInTimeActors can now specify a clock divider. 2019-10-13 18:19:39 -04:00
Thomas Harte
8b50a7d6e3 Attempts mostly to implement 6850 output. 2019-10-12 23:14:29 -04:00
Thomas Harte
fda99d9c5f Ensures all 16 data lines reach the video. 2019-10-10 23:29:46 -04:00
Thomas Harte
c5ebf75351 Attempts to start producing actual video. 2019-10-10 22:46:58 -04:00
Thomas Harte
52e5296544 Provides a token something where DMA should be. 2019-10-10 21:04:41 -04:00
Thomas Harte
d7ce2c26e8 Adds an empty shell for the ACIA. 2019-10-10 20:54:29 -04:00
Thomas Harte
f88e1b1373 Adds enough logic to advance to an ACIA access error. 2019-10-09 23:01:11 -04:00
Thomas Harte
021d4dbaf1 Makes an attempt at tracking video sequence points. 2019-10-08 23:06:50 -04:00
Thomas Harte
dbde8f2ee7 Takes a shot at other display outputs. 2019-10-08 22:29:58 -04:00
Thomas Harte
5d06930df4 Corrects sync generation. 2019-10-08 21:29:17 -04:00
Thomas Harte
7722596a3b Makes a first attempt to box out the ST display area. 2019-10-08 21:18:08 -04:00
Thomas Harte
1de1818ebb Makes an unsuccessful first attempt at some timer functionality. 2019-10-07 22:44:35 -04:00
Thomas Harte
885f890df1 Adds a target for MFP read/write operations. 
Completely without any implementation, so far.
 2019-10-06 23:14:05 -04:00
Thomas Harte
e195497ab7 Adds some semblance of an AY. 2019-10-06 22:30:48 -04:00
Thomas Harte
fcd2143697 Starts to formalise the ST memory map a little. 2019-10-06 17:15:29 -04:00
Thomas Harte
3f45cd2380 Starts forming an Atari ST memory map. 2019-10-04 22:38:46 -04:00
Thomas Harte
a8a34497ff Gifts the Atari ST a 68000 and non-functional video. 2019-10-04 21:34:15 -04:00
Thomas Harte
953423cc02 Starts to create an actual shell of a machine. 2019-10-03 22:47:57 -04:00
Thomas Harte
fe621d7e52 Adds a route through the static analyser to the Atari ST. 2019-10-03 22:10:10 -04:00
Thomas Harte
814bb4ec63 Adds an Atari ST enumeration and factory method. 2019-10-03 20:17:26 -04:00
Thomas Harte
3c146a3fb2 Adds missing Master System enumerations. 2019-09-30 21:10:30 -04:00
Thomas Harte
4ac3839185 Seeks to ensure that card transitions between real-time and just-in-time don't break timing. 2019-09-28 18:34:04 -04:00
Thomas Harte
fbf95ec2b8 Removes the now empty local namespace. 2019-09-24 22:48:47 -04:00
Thomas Harte
077c7d767f Shifts essential modifiers up to the Keyboard class. 
I had forgotten that mappers are not exposed.
 2019-09-22 13:48:50 -04:00
Thomas Harte
a416bc0058 Adds an interface allowing keyboard mappers to declare modifiers that are 'essential'. 
i.e. ones that, if not delivered reliably, will cause the related machine to behave unexpectedly.
 2019-09-22 13:14:09 -04:00
Thomas Harte
5f16fa8c08 Removes dead reference to video from VIAPortHandler. 2019-09-21 17:39:45 -04:00
Thomas Harte
e7bf0799b6 Implements every-other-cycle-during-pixels RAM timing. 2019-09-21 17:25:20 -04:00
Thomas Harte
2e24da4614 Implements quick booting, and edges towards exposing it on the Mac. 
It should already work in kiosk mode.
 2019-09-19 22:32:12 -04:00
Thomas Harte
e46601872b Establishes that the Macintosh offers the quick-boot option. 2019-09-19 21:50:39 -04:00
Thomas Harte
776b819a5a Adds the SCSI bus as an Activity::Source. 2019-09-19 19:31:22 -04:00
Thomas Harte
962275c22a Removes clock for NCR 5380. 
It doesn't have one in real life, and now can live off the time counting that occurs on the SCSI bus.
 2019-09-18 20:17:47 -04:00
Thomas Harte
243e40cd79 Adds signalling of DACK. 2019-09-14 13:48:33 -04:00
Thomas Harte
1c7e0f3c9d Fixes control line modification by the 5380 and SCSI target command chaining. 
So now I'm back to trying to guess how a SCSI command terminates re: the relative meanings of a message phase and a status phase.
 2019-09-02 23:14:37 -04:00
Thomas Harte
318cdb41ea Adds SCSI bus clocking to the Macintosh, and fixes its internal counting. 2019-09-02 16:03:33 -04:00
Thomas Harte
2f8e31bc8b Takes a first bash at implementing the new SCSI::Bus timing infrastructure. 2019-09-02 13:00:01 -04:00
Thomas Harte
1a60ced61b Starts trying to deal with creating a whole volume from merely a partition. 2019-08-25 23:03:54 -04:00
Thomas Harte
ca08716c52 Introduces real hard disk images to the nascent world of SCSI. 2019-08-25 17:03:41 -04:00
Thomas Harte
90cf99b626 Takes a wild swings at speeding up startup. 
With no success.
 2019-08-18 22:40:16 -04:00
Thomas Harte
f668e4a54c Makes an attempt at getting the 5380 past arbitration. 
Not entirely successful. Also gets a bit smarter with `final` on ClockingHint::Sources.
 2019-08-15 23:14:40 -04:00
Thomas Harte
0f67e490e8 Adjusts NCR address decoding to produce a more plausible initial interaction. 2019-08-11 22:43:25 -04:00
Thomas Harte
895c315fa5 Increases the Mac Plus too 4mb. 2019-08-11 21:41:12 -04:00
Thomas Harte
a90a74a512 Stubs in just enough of the 5380 to get a Mac Plus too boot. 2019-08-11 20:55:20 -04:00
Thomas Harte
bbd4e4d3dc Enhances memory map fidelity to allow for ROM holes on the Mac Plus. 
This is how the ROM detects the difference between the Plus and the 512ke, it seems.
 2019-08-10 23:53:34 -04:00
Thomas Harte
bac0461f7f Switches the drive-speed accumulator to the delegate pattern. 
This allows the Macintosh to ensure that the IWM is kept up just-in-time with drive speed changes.
 2019-08-07 21:39:23 -04:00
Thomas Harte
f26a200d78 Switches to a JustInTimeActor to wrap the IWM. 
Also simplifies potential future usage of the IWM template.
 2019-08-07 21:28:02 -04:00
Thomas Harte
0e293e4983 Relocates RAM delay test in order to scrape out a minor performance win. 2019-08-03 21:46:45 -04:00
Thomas Harte
478f2533b5 Corrects 68000 address bus during interrupt acknowledge. 
All unused bits should be 1, not 0.
 2019-08-03 15:38:36 -04:00
Thomas Harte
a07488cf1b Introduces the Mac Plus memory map. 
Albeit with no SCSI support yet.
 2019-08-02 22:26:40 -04:00
Thomas Harte
d67c5145c0 Introduces RAM access delays. 2019-08-02 22:12:34 -04:00