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2016-10-20

2016-11-03

2016-11-08

2016-12-06

2016-12-31

2017-01-01

2017-01-27

2017-01-30

2017-03-26

2017-03-26.2

2017-05-14

2017-05-16

2017-07-15

2017-07-30

2017-08-16

2017-08-27

2017-10-24

2017-11-03

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2018-04-07

2018-04-13

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2018-07-11

2018-07-22

2018-08-05

2018-08-26

2018-08-31

2018-09-09

2018-09-15

2018-10-26

2018-10-29

2019-03-02

2019-03-03

2019-03-10

2019-07-27

2019-07-28

2019-08-01

2019-08-04

2019-09-22

2019-09-28

2019-11-05

2019-11-17

2019-12-25

2019-12-26

2020-01-01

2020-01-05

2020-01-06

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2020-02-12

2020-02-16

2020-03-07

2020-03-10

2020-03-21

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2020-09-16

2020-09-17

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2020-11-07

2020-11-13

2020-11-21

2020-11-29

2020-12-09

2021-02-02

2021-03-07

2021-03-23

2021-03-25

2021-04-06

2021-04-16

2021-04-16.2

2021-04-19

2021-04-21

2021-05-05

2021-06-13

2021-07-03

2021-07-09

2021-07-16

2021-08-09

2021-12-19

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2022-03-26

2022-04-17

2022-07-01

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2022-08-22

2022-09-16

2022-11-25

2023-05-08

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2023-10-29

2023-12-26

2023-12-28

2024-01-22

2024-04-20

2024-05-05

2024-05-27

2024-06-02

2024-06-03

untagged-83a648386d4da3db578a

fc880ac130 Double down on trans mode. Thomas Harte 2024-03-25 21:32:56 -0400
a2d95cb982 Shuffle notes. Thomas Harte 2024-03-25 21:31:59 -0400
d2776071e4 Speed up debug mode. Thomas Harte 2024-03-25 21:31:33 -0400
72a645ec1e Fix trans; take further crack at MEMC permissions. Thomas Harte 2024-03-25 15:50:59 -0400
1154ffd072 Add a 'drive in use' indicator LED. Thomas Harte 2024-03-25 15:03:54 -0400
8ba9708942 Hopefully resolve the mystery of the latch writes. Thomas Harte 2024-03-25 14:54:30 -0400
521fca6089 Expose full bus to IOC dependents; add notes. Thomas Harte 2024-03-25 11:07:44 -0400
ae684edbe1 Formally decode bank/offset/type. Thomas Harte 2024-03-25 10:16:36 -0400
fa0a9aa611 Eliminate 'has_moved_rom_'. Thomas Harte 2024-03-24 22:36:11 -0400
5da9e0486a Simplify control flow. Thomas Harte 2024-03-24 22:30:26 -0400
6980fd760c Add further heavily-manual debugging aids. Thomas Harte 2024-03-24 22:18:30 -0400
3549488b7a Add round-trip test for status flags. Thomas Harte 2024-03-24 22:18:16 -0400
c1602cc8fe The keyboard and interrupts are currently trusted. Thomas Harte 2024-03-23 21:49:52 -0400
189dd176de Reguess state machine, fixing startup display. Thomas Harte 2024-03-23 21:38:35 -0400
3cf262d1f7 Improve terminology, add more documentation. Thomas Harte 2024-03-23 21:12:01 -0400
ccfc389274 Quieten where now confident. Thomas Harte 2024-03-23 21:03:06 -0400
0e07f802ac Use BACK state; accept other ACKs at any time. Thomas Harte 2024-03-23 21:02:35 -0400
55f92e2411 Adjust data abort address. Thomas Harte 2024-03-23 20:31:25 -0400
c720f3910a Avoid implicit sign cast. Thomas Harte 2024-03-23 20:13:25 -0400
4215edd11b Reduce noise. Thomas Harte 2024-03-23 20:12:56 -0400
09a61cf1a7 Don't expect an ACK after identifying. Thomas Harte 2024-03-23 20:12:38 -0400
5967ad0865 Sketch out whole protocol, albeit faulty. Thomas Harte 2024-03-23 17:08:03 -0400
eb34c38332 Add very faulty key input. Thomas Harte 2024-03-23 15:58:48 -0400
5ccb18225a Provide key states to the keyboard. Thomas Harte 2024-03-23 15:43:04 -0400
58bbce1a15 Avoid display errors upon back-pressure. Thomas Harte 2024-03-22 22:01:12 -0400
9ea3e547ee Fix IRQ/FIQ return addresses. Thomas Harte 2024-03-22 21:42:34 -0400
fb5fdc9f10 Actually apply video divider. Thomas Harte 2024-03-22 10:24:24 -0400
de7b7818f4 Add 4bpp output. Thomas Harte 2024-03-22 10:18:25 -0400
c4e6b18294 Manage pixel buffers. Thomas Harte 2024-03-22 10:10:13 -0400
ae6cf69449 Move responsibility for clock division; reinstate vsync interrupt. Thomas Harte 2024-03-22 10:01:34 -0400
4a2dcff028 Endeavour to map colours properly. Thomas Harte 2024-03-21 21:53:50 -0400
aa6acec8fa Don't hoard cycles per line value. Thomas Harte 2024-03-21 21:47:27 -0400
4ac4da908c Reduce TODOs, do _something_ with border colour. Thomas Harte 2024-03-21 21:40:11 -0400
66e62857c4 Give ostensibly clean timing to the CRT. Thomas Harte 2024-03-21 21:29:53 -0400
bbc0d8b050 Count time in phase correctly. Thomas Harte 2024-03-21 21:15:25 -0400
0f8bc416d1 Make first, faulty step into displaying a field. Thomas Harte 2024-03-21 21:10:55 -0400
2ec235170e Finish the thought on magic constants. Thomas Harte 2024-03-21 20:43:55 -0400
2de1a2dd0d Install and properly clock a CRT. Thomas Harte 2024-03-21 20:41:24 -0400
1f49c3b113 Give sound and video somewhere to read from. Thomas Harte 2024-03-21 20:22:20 -0400
5c645fb3c2 Switch to a fixed output clock; retain addresses. Thomas Harte 2024-03-21 11:51:29 -0400
40b5227f0b Deliver all addresses to the video outputter. Thomas Harte 2024-03-21 11:24:47 -0400
847dba8f07 Divide input pixel rate. Thomas Harte 2024-03-21 11:03:28 -0400
417c6c4629 Announce changes. Thomas Harte 2024-03-21 10:51:52 -0400
2d6a4d490e Add dummy retrace interrupt. Thomas Harte 2024-03-21 10:02:56 -0400
a6ec870872 Capture more audio detail. Thomas Harte 2024-03-21 09:47:53 -0400
389541be6d Pipe further sound parameters; obey divider. Thomas Harte 2024-03-20 14:43:47 -0400
208f3e24de Audio ticks are now included. Thomas Harte 2024-03-20 14:30:21 -0400
f7e36a1e03 Merge branch 'Archimedes' of github.com:TomHarte/CLK into Archimedes Thomas Harte 2024-03-20 14:27:32 -0400
1341816791 Break apart, switching to delegates for interrupts. Thomas Harte 2024-03-20 14:25:20 -0400
b986add74a Break apart, switching to delegates for interrupts. Thomas Harte 2024-03-20 14:25:20 -0400
08673ff021 Switch to macro blocks of execution; flail around audio. Thomas Harte 2024-03-20 11:42:37 -0400
3a2d9c6082 Give user access to ROM; clean up a touch. Thomas Harte 2024-03-19 20:26:17 -0400
43a3959b8f Don't data abort on missing low ROM. Thomas Harte 2024-03-19 15:06:01 -0400
85a738acff Get rigorous on exception addresses. Thomas Harte 2024-03-19 15:03:31 -0400
17dbdce230 Eliminate SDL/scons targets for which brew is broken. Thomas Harte 2024-03-19 14:27:46 -0400
9d084782ae Document. Thomas Harte 2024-03-19 12:22:19 -0400
106937b679 Run into the shifts wall with LDR/STR. Thomas Harte 2024-03-19 12:19:49 -0400
623eda7162 Output branches and nops correctly. Thomas Harte 2024-03-19 11:42:41 -0400
2ad6bb099b Begin foray into disassembly. Thomas Harte 2024-03-19 11:34:10 -0400
9d858bc61b IRQ and FIQ should also store PC+4. Thomas Harte 2024-03-18 14:08:08 -0400
612c9ce49a Transfer logging responsibility. Thomas Harte 2024-03-18 11:09:29 -0400
64e025484a Adjust means of waiting out address. Thomas Harte 2024-03-17 22:14:07 -0400
7b1f800387 Extend I2C state machine. Thomas Harte 2024-03-17 21:55:19 -0400
2712d50e05 Attempt some inspection. Thomas Harte 2024-03-16 22:02:16 -0400
47e9279bd4 Add a target for I2C activity. Thomas Harte 2024-03-16 15:00:23 -0400
635efd0212 Clear keyboard interrupts. Thomas Harte 2024-03-15 23:19:26 -0400
1c1d2891c7 Adjust IRQ/FIQ return addresses. Thomas Harte 2024-03-15 21:59:38 -0400
1979d2e5ba Don't set interrupt flags before capture. Thomas Harte 2024-03-15 21:34:39 -0400
c25d0e8843 Correctly capture mode upon exception. Thomas Harte 2024-03-15 18:39:56 -0400
3a899ea4be Add test coverage for STM descending, proving nothing. Thomas Harte 2024-03-15 14:55:17 -0400
9d08282e28 Add enough of a keyboard to respond to reset. Thomas Harte 2024-03-15 10:57:18 -0400
18154278d1 Add minor note on where next. Thomas Harte 2024-03-14 21:54:20 -0400
9063852857 Undo spurious text change. Thomas Harte 2024-03-14 21:16:38 -0400
bc27e3998d Fix downward block data transfers. Thomas Harte 2024-03-14 21:09:51 -0400
19fa0b8945 Shush logging, momentarily. Thomas Harte 2024-03-14 10:53:38 -0400
4987bdfec9 Throw less. Thomas Harte 2024-03-14 10:43:51 -0400
0e4615564d Make bit masks easily testable; expand logging. Thomas Harte 2024-03-13 14:31:26 -0400
7aeea535a1 Reduce branchiness. Thomas Harte 2024-03-13 11:02:52 -0400
6b18d775ab Eliminate unused variables. Thomas Harte 2024-03-12 21:53:26 -0400
2ed031e440 Prepare for additional devices. Thomas Harte 2024-03-12 21:23:22 -0400
5d6bb11eb7 Add return. Thomas Harte 2024-03-12 11:37:15 -0400
c6b91559e1 Attempt to wire up timer interrupts. Thomas Harte 2024-03-12 11:34:31 -0400
6efc41ded7 Come to conclusion on R15; fix link values. Thomas Harte 2024-03-12 10:42:09 -0400
e9c5582fe1 Add note on ambiguity to be resolved. Thomas Harte 2024-03-12 10:04:02 -0400
8b3c0abe93 Take another swing at R15 as a destination. Thomas Harte 2024-03-12 09:13:05 -0400
a5ebac1b29 Add RISC OS 3.11 to catalogue, while bug hunting. Thomas Harte 2024-03-11 22:19:14 -0400
1ccfae885c Remove extra slashes. Thomas Harte 2024-03-11 15:06:17 -0400
971bfb2ecb Unify subtractions. Thomas Harte 2024-03-11 14:52:48 -0400
e7457461ba Reduce magic constants. Thomas Harte 2024-03-11 14:49:03 -0400
e8c1e8fd3f Fix RSB carry; unify set_pc. Thomas Harte 2024-03-11 14:48:43 -0400
ca779bc841 Expand test set. Thomas Harte 2024-03-11 14:48:18 -0400
a28c97c0de Simplify privilege test. Thomas Harte 2024-03-11 12:14:00 -0400
db49146efe Figure out what's going on with TEQ. Thomas Harte 2024-03-11 09:51:09 -0400
830d70d3aa Trust tests on immediate-opcode ROR 0; limit shift by register. Thomas Harte 2024-03-10 23:38:31 -0400
336292bc49 Further correct R15 as a destination. Thomas Harte 2024-03-10 22:56:02 -0400
bd62228cc6 The test set doesn't seem to do word rotation. Thomas Harte 2024-03-10 22:40:37 -0400
ccdd340c9a Reads also may or may not be aligned. *sigh* Thomas Harte 2024-03-10 22:34:56 -0400
0b42f5fb30 Make further test-set allowances. Thomas Harte 2024-03-10 22:29:40 -0400
e9e1db7a05 Change LDR writeback to destination. Thomas Harte 2024-03-10 22:29:19 -0400
21278d028c Correct unaligned accesses. Thomas Harte 2024-03-10 21:56:19 -0400