2010-12-08 03:26:16 +00:00
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//===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RAGreedy function pass for register allocation in
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// optimized builds.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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2010-12-10 22:21:05 +00:00
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#include "AllocationOrder.h"
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2011-04-02 06:03:35 +00:00
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#include "InterferenceCache.h"
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2011-04-05 21:40:37 +00:00
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#include "LiveDebugVariables.h"
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2010-12-17 23:16:32 +00:00
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#include "LiveRangeEdit.h"
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2010-12-08 03:26:16 +00:00
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#include "RegAllocBase.h"
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#include "Spiller.h"
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2011-01-18 21:13:27 +00:00
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#include "SpillPlacement.h"
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2010-12-15 23:46:13 +00:00
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#include "SplitKit.h"
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2010-12-08 03:26:16 +00:00
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#include "VirtRegMap.h"
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2011-06-26 21:41:06 +00:00
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#include "RegisterCoalescer.h"
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2011-02-17 22:53:48 +00:00
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#include "llvm/ADT/Statistic.h"
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2010-12-08 03:26:16 +00:00
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Function.h"
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#include "llvm/PassAnalysisSupport.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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2011-01-18 21:13:27 +00:00
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#include "llvm/CodeGen/EdgeBundles.h"
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2010-12-08 03:26:16 +00:00
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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2010-12-17 23:16:32 +00:00
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#include "llvm/CodeGen/MachineDominators.h"
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2010-12-08 03:26:16 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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2011-07-26 23:41:46 +00:00
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#include "llvm/Support/CommandLine.h"
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2010-12-08 03:26:16 +00:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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2010-12-11 00:19:56 +00:00
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#include "llvm/Support/Timer.h"
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2010-12-08 03:26:16 +00:00
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2011-02-22 23:01:52 +00:00
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#include <queue>
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2010-12-08 03:26:16 +00:00
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using namespace llvm;
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2011-02-17 22:53:48 +00:00
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STATISTIC(NumGlobalSplits, "Number of split global live ranges");
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STATISTIC(NumLocalSplits, "Number of split local live ranges");
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STATISTIC(NumEvicted, "Number of interferences evicted");
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2011-07-30 17:19:14 +00:00
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cl::opt<bool> CompactRegions("compact-regions");
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2011-07-26 23:41:46 +00:00
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2010-12-08 03:26:16 +00:00
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static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
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createGreedyRegisterAllocator);
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namespace {
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2011-03-09 00:57:29 +00:00
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class RAGreedy : public MachineFunctionPass,
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public RegAllocBase,
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private LiveRangeEdit::Delegate {
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2010-12-08 03:26:16 +00:00
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// context
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MachineFunction *MF;
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// analyses
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2011-01-18 21:13:27 +00:00
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SlotIndexes *Indexes;
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2010-12-08 03:26:16 +00:00
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LiveStacks *LS;
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2010-12-17 23:16:32 +00:00
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MachineDominatorTree *DomTree;
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2010-12-15 23:46:13 +00:00
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MachineLoopInfo *Loops;
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2011-01-18 21:13:27 +00:00
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EdgeBundles *Bundles;
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SpillPlacement *SpillPlacer;
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2011-05-06 18:00:02 +00:00
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LiveDebugVariables *DebugVars;
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2010-12-17 23:16:32 +00:00
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2010-12-08 03:26:16 +00:00
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// state
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std::auto_ptr<Spiller> SpillerInstance;
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2011-02-22 23:01:52 +00:00
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std::priority_queue<std::pair<unsigned, unsigned> > Queue;
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2011-07-02 01:37:09 +00:00
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unsigned NextCascade;
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2011-03-01 21:10:07 +00:00
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// Live ranges pass through a number of stages as we try to allocate them.
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// Some of the stages may also create new live ranges:
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//
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// - Region splitting.
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// - Per-block splitting.
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// - Local splitting.
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// - Spilling.
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//
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// Ranges produced by one of the stages skip the previous stages when they are
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// dequeued. This improves performance because we can skip interference checks
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// that are unlikely to give any results. It also guarantees that the live
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// range splitting algorithm terminates, something that is otherwise hard to
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// ensure.
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enum LiveRangeStage {
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2011-07-25 15:25:41 +00:00
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/// Newly created live range that has never been queued.
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RS_New,
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/// Only attempt assignment and eviction. Then requeue as RS_Split.
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RS_Assign,
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/// Attempt live range splitting if assignment is impossible.
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RS_Split,
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2011-07-25 15:25:43 +00:00
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/// Attempt more aggressive live range splitting that is guaranteed to make
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/// progress. This is used for split products that may not be making
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/// progress.
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RS_Split2,
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2011-07-25 15:25:41 +00:00
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/// Live range will be spilled. No more splitting will be attempted.
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RS_Spill,
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/// There is nothing more we can do to this live range. Abort compilation
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/// if it can't be assigned.
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RS_Done
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2011-03-01 21:10:07 +00:00
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};
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2011-05-25 23:58:36 +00:00
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static const char *const StageName[];
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2011-07-02 01:37:09 +00:00
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// RegInfo - Keep additional information about each live range.
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struct RegInfo {
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LiveRangeStage Stage;
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// Cascade - Eviction loop prevention. See canEvictInterference().
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unsigned Cascade;
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RegInfo() : Stage(RS_New), Cascade(0) {}
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};
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IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
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2011-03-01 21:10:07 +00:00
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LiveRangeStage getStage(const LiveInterval &VirtReg) const {
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2011-07-02 01:37:09 +00:00
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return ExtraRegInfo[VirtReg.reg].Stage;
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}
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void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
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ExtraRegInfo.resize(MRI->getNumVirtRegs());
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ExtraRegInfo[VirtReg.reg].Stage = Stage;
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2011-03-01 21:10:07 +00:00
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}
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template<typename Iterator>
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void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
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2011-07-02 01:37:09 +00:00
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ExtraRegInfo.resize(MRI->getNumVirtRegs());
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2011-03-30 02:52:39 +00:00
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for (;Begin != End; ++Begin) {
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unsigned Reg = (*Begin)->reg;
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2011-07-02 01:37:09 +00:00
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if (ExtraRegInfo[Reg].Stage == RS_New)
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ExtraRegInfo[Reg].Stage = NewStage;
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2011-03-30 02:52:39 +00:00
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}
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2011-03-01 21:10:07 +00:00
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}
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2010-12-08 03:26:16 +00:00
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2011-07-08 20:46:18 +00:00
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/// Cost of evicting interference.
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struct EvictionCost {
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unsigned BrokenHints; ///< Total number of broken hints.
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float MaxWeight; ///< Maximum spill weight evicted.
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EvictionCost(unsigned B = 0) : BrokenHints(B), MaxWeight(0) {}
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bool operator<(const EvictionCost &O) const {
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if (BrokenHints != O.BrokenHints)
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return BrokenHints < O.BrokenHints;
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return MaxWeight < O.MaxWeight;
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}
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};
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2011-01-18 21:13:27 +00:00
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// splitting state.
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2011-03-01 21:10:07 +00:00
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std::auto_ptr<SplitAnalysis> SA;
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2011-03-03 01:29:13 +00:00
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std::auto_ptr<SplitEditor> SE;
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2011-01-18 21:13:27 +00:00
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2011-04-02 06:03:38 +00:00
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/// Cached per-block interference maps
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InterferenceCache IntfCache;
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2011-04-07 17:27:46 +00:00
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/// All basic blocks where the current register has uses.
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2011-03-05 01:10:31 +00:00
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SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
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2011-01-18 21:13:27 +00:00
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2011-03-05 01:10:31 +00:00
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/// Global live range splitting candidate info.
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struct GlobalSplitCandidate {
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2011-07-26 23:41:46 +00:00
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// Register intended for assignment, or 0.
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2011-03-05 01:10:31 +00:00
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unsigned PhysReg;
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2011-07-26 23:41:46 +00:00
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// SplitKit interval index for this candidate.
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unsigned IntvIdx;
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// Interference for PhysReg.
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2011-07-14 00:17:10 +00:00
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InterferenceCache::Cursor Intf;
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2011-07-26 23:41:46 +00:00
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// Bundles where this candidate should be live.
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2011-03-05 01:10:31 +00:00
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BitVector LiveBundles;
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2011-04-12 21:30:53 +00:00
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SmallVector<unsigned, 8> ActiveBlocks;
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2011-07-14 00:17:10 +00:00
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void reset(InterferenceCache &Cache, unsigned Reg) {
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2011-04-12 21:30:53 +00:00
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PhysReg = Reg;
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2011-07-26 23:41:46 +00:00
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IntvIdx = 0;
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2011-07-14 00:17:10 +00:00
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Intf.setPhysReg(Cache, Reg);
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2011-04-12 21:30:53 +00:00
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LiveBundles.clear();
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ActiveBlocks.clear();
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}
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2011-07-26 23:41:46 +00:00
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// Set B[i] = C for every live bundle where B[i] was NoCand.
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unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
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unsigned Count = 0;
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for (int i = LiveBundles.find_first(); i >= 0;
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i = LiveBundles.find_next(i))
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if (B[i] == NoCand) {
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B[i] = C;
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Count++;
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}
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return Count;
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}
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2011-03-05 01:10:31 +00:00
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};
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/// Candidate info for for each PhysReg in AllocationOrder.
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/// This vector never shrinks, but grows to the size of the largest register
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/// class.
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SmallVector<GlobalSplitCandidate, 32> GlobalCand;
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2011-07-26 23:41:46 +00:00
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enum { NoCand = ~0u };
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/// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
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/// NoCand which indicates the stack interval.
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SmallVector<unsigned, 32> BundleCand;
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2010-12-08 03:26:16 +00:00
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public:
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RAGreedy();
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/// Return the pass name.
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virtual const char* getPassName() const {
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2010-12-11 00:19:56 +00:00
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return "Greedy Register Allocator";
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2010-12-08 03:26:16 +00:00
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}
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/// RAGreedy analysis usage.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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virtual Spiller &spiller() { return *SpillerInstance; }
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2011-02-22 23:01:52 +00:00
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virtual void enqueue(LiveInterval *LI);
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virtual LiveInterval *dequeue();
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2011-01-19 22:11:48 +00:00
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virtual unsigned selectOrSplit(LiveInterval&,
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SmallVectorImpl<LiveInterval*>&);
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2010-12-08 03:26:16 +00:00
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/// Perform register allocation.
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virtual bool runOnMachineFunction(MachineFunction &mf);
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static char ID;
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2010-12-09 18:15:21 +00:00
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private:
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2011-03-09 00:57:29 +00:00
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void LRE_WillEraseInstruction(MachineInstr*);
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2011-03-13 01:23:11 +00:00
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bool LRE_CanEraseVirtReg(unsigned);
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2011-03-16 22:56:16 +00:00
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void LRE_WillShrinkVirtReg(unsigned);
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2011-03-30 02:52:39 +00:00
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void LRE_DidCloneVirtReg(unsigned, unsigned);
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2011-03-09 00:57:29 +00:00
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2011-04-22 22:47:40 +00:00
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float calcSpillCost();
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2011-04-09 02:59:09 +00:00
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bool addSplitConstraints(InterferenceCache::Cursor, float&);
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void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
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2011-07-14 00:17:10 +00:00
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void growRegion(GlobalSplitCandidate &Cand);
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float calcGlobalSplitCost(GlobalSplitCandidate&);
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2011-07-23 03:41:57 +00:00
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bool calcCompactRegion(GlobalSplitCandidate&);
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2011-07-26 23:41:46 +00:00
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void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
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2011-02-17 19:13:53 +00:00
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void calcGapWeights(unsigned, SmallVectorImpl<float>&);
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2011-07-08 20:46:18 +00:00
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bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
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bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
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void evictInterference(LiveInterval&, unsigned,
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SmallVectorImpl<LiveInterval*>&);
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2010-12-14 00:37:44 +00:00
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2011-04-20 18:19:48 +00:00
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unsigned tryAssign(LiveInterval&, AllocationOrder&,
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SmallVectorImpl<LiveInterval*>&);
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2011-02-23 00:29:52 +00:00
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unsigned tryEvict(LiveInterval&, AllocationOrder&,
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2011-04-20 18:19:48 +00:00
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SmallVectorImpl<LiveInterval*>&, unsigned = ~0u);
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2011-01-18 21:13:27 +00:00
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unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
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SmallVectorImpl<LiveInterval*>&);
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2011-02-17 19:13:53 +00:00
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unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
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SmallVectorImpl<LiveInterval*>&);
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2010-12-14 00:37:44 +00:00
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unsigned trySplit(LiveInterval&, AllocationOrder&,
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SmallVectorImpl<LiveInterval*>&);
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2010-12-08 03:26:16 +00:00
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};
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} // end anonymous namespace
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char RAGreedy::ID = 0;
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2011-05-25 23:58:36 +00:00
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#ifndef NDEBUG
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const char *const RAGreedy::StageName[] = {
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2011-07-25 15:25:41 +00:00
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"RS_New",
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"RS_Assign",
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"RS_Split",
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2011-07-25 15:25:43 +00:00
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"RS_Split2",
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2011-07-25 15:25:41 +00:00
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"RS_Spill",
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"RS_Done"
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2011-05-25 23:58:36 +00:00
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};
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#endif
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2011-04-22 22:47:40 +00:00
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// Hysteresis to use when comparing floats.
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// This helps stabilize decisions based on float comparisons.
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const float Hysteresis = 0.98f;
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2010-12-08 03:26:16 +00:00
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FunctionPass* llvm::createGreedyRegisterAllocator() {
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return new RAGreedy();
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}
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2011-07-02 01:37:09 +00:00
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RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
|
2011-04-05 21:40:37 +00:00
|
|
|
initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
|
2011-01-18 21:13:27 +00:00
|
|
|
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
|
2010-12-08 03:26:16 +00:00
|
|
|
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
|
|
|
|
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
|
|
|
|
initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
|
2011-06-26 22:34:10 +00:00
|
|
|
initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
|
2010-12-08 03:26:16 +00:00
|
|
|
initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
|
|
|
|
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
|
|
|
|
initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
|
|
|
|
initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
|
|
|
|
initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
|
2011-01-18 21:13:27 +00:00
|
|
|
initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
|
|
|
|
initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
|
2010-12-08 03:26:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
|
|
AU.setPreservesCFG();
|
|
|
|
AU.addRequired<AliasAnalysis>();
|
|
|
|
AU.addPreserved<AliasAnalysis>();
|
|
|
|
AU.addRequired<LiveIntervals>();
|
2011-01-18 21:13:27 +00:00
|
|
|
AU.addRequired<SlotIndexes>();
|
2010-12-08 03:26:16 +00:00
|
|
|
AU.addPreserved<SlotIndexes>();
|
2011-04-05 21:40:37 +00:00
|
|
|
AU.addRequired<LiveDebugVariables>();
|
|
|
|
AU.addPreserved<LiveDebugVariables>();
|
2010-12-08 03:26:16 +00:00
|
|
|
if (StrongPHIElim)
|
|
|
|
AU.addRequiredID(StrongPHIEliminationID);
|
|
|
|
AU.addRequiredTransitive<RegisterCoalescer>();
|
|
|
|
AU.addRequired<CalculateSpillWeights>();
|
|
|
|
AU.addRequired<LiveStacks>();
|
|
|
|
AU.addPreserved<LiveStacks>();
|
2010-12-17 23:16:32 +00:00
|
|
|
AU.addRequired<MachineDominatorTree>();
|
|
|
|
AU.addPreserved<MachineDominatorTree>();
|
2010-12-08 03:26:16 +00:00
|
|
|
AU.addRequired<MachineLoopInfo>();
|
|
|
|
AU.addPreserved<MachineLoopInfo>();
|
|
|
|
AU.addRequired<VirtRegMap>();
|
|
|
|
AU.addPreserved<VirtRegMap>();
|
2011-01-18 21:13:27 +00:00
|
|
|
AU.addRequired<EdgeBundles>();
|
|
|
|
AU.addRequired<SpillPlacement>();
|
2010-12-08 03:26:16 +00:00
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
|
|
}
|
|
|
|
|
2011-03-09 00:57:29 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// LiveRangeEdit delegate methods
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
|
|
|
|
// LRE itself will remove from SlotIndexes and parent basic block.
|
|
|
|
VRM->RemoveMachineInstrFromMaps(MI);
|
|
|
|
}
|
|
|
|
|
2011-03-13 01:23:11 +00:00
|
|
|
bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
|
|
|
|
if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
|
|
|
|
unassign(LIS->getInterval(VirtReg), PhysReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
// Unassigned virtreg is probably in the priority queue.
|
|
|
|
// RegAllocBase will erase it after dequeueing.
|
|
|
|
return false;
|
|
|
|
}
|
2011-03-09 00:57:29 +00:00
|
|
|
|
2011-03-16 22:56:16 +00:00
|
|
|
void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
|
|
|
|
unsigned PhysReg = VRM->getPhys(VirtReg);
|
|
|
|
if (!PhysReg)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Register is assigned, put it back on the queue for reassignment.
|
|
|
|
LiveInterval &LI = LIS->getInterval(VirtReg);
|
|
|
|
unassign(LI, PhysReg);
|
|
|
|
enqueue(&LI);
|
|
|
|
}
|
|
|
|
|
2011-03-30 02:52:39 +00:00
|
|
|
void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
|
|
|
|
// LRE may clone a virtual register because dead code elimination causes it to
|
2011-07-26 00:54:56 +00:00
|
|
|
// be split into connected components. The new components are much smaller
|
|
|
|
// than the original, so they should get a new chance at being assigned.
|
2011-03-30 02:52:39 +00:00
|
|
|
// same stage as the parent.
|
2011-07-26 00:54:56 +00:00
|
|
|
ExtraRegInfo[Old].Stage = RS_Assign;
|
2011-07-02 01:37:09 +00:00
|
|
|
ExtraRegInfo.grow(New);
|
|
|
|
ExtraRegInfo[New] = ExtraRegInfo[Old];
|
2011-03-30 02:52:39 +00:00
|
|
|
}
|
|
|
|
|
2010-12-08 03:26:16 +00:00
|
|
|
void RAGreedy::releaseMemory() {
|
|
|
|
SpillerInstance.reset(0);
|
2011-07-02 01:37:09 +00:00
|
|
|
ExtraRegInfo.clear();
|
2011-04-12 21:30:53 +00:00
|
|
|
GlobalCand.clear();
|
2010-12-08 03:26:16 +00:00
|
|
|
RegAllocBase::releaseMemory();
|
|
|
|
}
|
|
|
|
|
2011-02-22 23:01:52 +00:00
|
|
|
void RAGreedy::enqueue(LiveInterval *LI) {
|
|
|
|
// Prioritize live ranges by size, assigning larger ranges first.
|
|
|
|
// The queue holds (size, reg) pairs.
|
2011-02-24 23:21:36 +00:00
|
|
|
const unsigned Size = LI->getSize();
|
|
|
|
const unsigned Reg = LI->reg;
|
2011-02-22 23:01:52 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
|
|
"Can only enqueue virtual registers");
|
2011-02-24 23:21:36 +00:00
|
|
|
unsigned Prio;
|
2010-12-08 22:57:16 +00:00
|
|
|
|
2011-07-02 01:37:09 +00:00
|
|
|
ExtraRegInfo.grow(Reg);
|
|
|
|
if (ExtraRegInfo[Reg].Stage == RS_New)
|
2011-07-25 15:25:41 +00:00
|
|
|
ExtraRegInfo[Reg].Stage = RS_Assign;
|
2011-03-30 02:52:39 +00:00
|
|
|
|
Reverse order of RS_Split live ranges under -compact-regions.
There are two conflicting strategies in play:
- Under high register pressure, we want to assign large live ranges
first. Smaller live ranges are easier to place afterwards.
- Live range splitting is guided by interference, so splitting should be
deferred until interference is as realistic as possible.
With the recent changes to the live range stages, and with compact
regions enabled, it is less traumatic to split a live range too early.
If some of the split products were too big, they can often be split
again.
By reversing the RS_Split order, we get this queue order:
1. Normal live ranges, large to small.
2. RS_Split live ranges, large to small.
The large-to-small order improves RAGreedy's puzzle solving skills under
high register pressure. It may cause a bit more iterated splitting, but
we handle that better now.
With this change, -compact-regions is mostly an improvement on SPEC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28 20:48:23 +00:00
|
|
|
if (ExtraRegInfo[Reg].Stage == RS_Split) {
|
2011-03-27 22:49:21 +00:00
|
|
|
// Unsplit ranges that couldn't be allocated immediately are deferred until
|
|
|
|
// everything else has been allocated. Long ranges are allocated last so
|
|
|
|
// they are split against realistic interference.
|
Reverse order of RS_Split live ranges under -compact-regions.
There are two conflicting strategies in play:
- Under high register pressure, we want to assign large live ranges
first. Smaller live ranges are easier to place afterwards.
- Live range splitting is guided by interference, so splitting should be
deferred until interference is as realistic as possible.
With the recent changes to the live range stages, and with compact
regions enabled, it is less traumatic to split a live range too early.
If some of the split products were too big, they can often be split
again.
By reversing the RS_Split order, we get this queue order:
1. Normal live ranges, large to small.
2. RS_Split live ranges, large to small.
The large-to-small order improves RAGreedy's puzzle solving skills under
high register pressure. It may cause a bit more iterated splitting, but
we handle that better now.
With this change, -compact-regions is mostly an improvement on SPEC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28 20:48:23 +00:00
|
|
|
if (CompactRegions)
|
|
|
|
Prio = Size;
|
|
|
|
else
|
|
|
|
Prio = (1u << 31) - Size;
|
|
|
|
} else {
|
2011-03-27 22:49:21 +00:00
|
|
|
// Everything else is allocated in long->short order. Long ranges that don't
|
|
|
|
// fit should be spilled ASAP so they don't create interference.
|
2011-02-24 23:21:36 +00:00
|
|
|
Prio = (1u << 31) + Size;
|
2011-02-23 00:56:56 +00:00
|
|
|
|
2011-03-27 22:49:21 +00:00
|
|
|
// Boost ranges that have a physical register hint.
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg)))
|
|
|
|
Prio |= (1u << 30);
|
|
|
|
}
|
2011-02-24 23:21:36 +00:00
|
|
|
|
|
|
|
Queue.push(std::make_pair(Prio, Reg));
|
2010-12-08 22:57:16 +00:00
|
|
|
}
|
|
|
|
|
2011-02-22 23:01:52 +00:00
|
|
|
LiveInterval *RAGreedy::dequeue() {
|
|
|
|
if (Queue.empty())
|
|
|
|
return 0;
|
|
|
|
LiveInterval *LI = &LIS->getInterval(Queue.top().second);
|
|
|
|
Queue.pop();
|
|
|
|
return LI;
|
|
|
|
}
|
2010-12-22 22:01:30 +00:00
|
|
|
|
2011-04-20 18:19:48 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Direct Assignment
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// tryAssign - Try to assign VirtReg to an available register.
|
|
|
|
unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
|
|
|
|
AllocationOrder &Order,
|
|
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs) {
|
|
|
|
Order.rewind();
|
|
|
|
unsigned PhysReg;
|
|
|
|
while ((PhysReg = Order.next()))
|
|
|
|
if (!checkPhysRegInterference(VirtReg, PhysReg))
|
|
|
|
break;
|
|
|
|
if (!PhysReg || Order.isHint(PhysReg))
|
|
|
|
return PhysReg;
|
|
|
|
|
2011-07-08 20:46:18 +00:00
|
|
|
// PhysReg is available, but there may be a better choice.
|
|
|
|
|
|
|
|
// If we missed a simple hint, try to cheaply evict interference from the
|
|
|
|
// preferred register.
|
|
|
|
if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
|
|
|
|
if (Order.isHint(Hint)) {
|
|
|
|
DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
|
|
|
|
EvictionCost MaxCost(1);
|
|
|
|
if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
|
|
|
|
evictInterference(VirtReg, Hint, NewVRegs);
|
|
|
|
return Hint;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Try to evict interference from a cheaper alternative.
|
2011-04-20 18:19:48 +00:00
|
|
|
unsigned Cost = TRI->getCostPerUse(PhysReg);
|
|
|
|
|
|
|
|
// Most registers have 0 additional cost.
|
|
|
|
if (!Cost)
|
|
|
|
return PhysReg;
|
|
|
|
|
|
|
|
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
|
|
|
|
<< '\n');
|
|
|
|
unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
|
|
|
|
return CheapReg ? CheapReg : PhysReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-02-23 00:29:52 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Interference eviction
|
|
|
|
//===----------------------------------------------------------------------===//
|
2011-02-09 01:14:03 +00:00
|
|
|
|
2011-07-08 20:46:18 +00:00
|
|
|
/// shouldEvict - determine if A should evict the assigned live range B. The
|
|
|
|
/// eviction policy defined by this function together with the allocation order
|
|
|
|
/// defined by enqueue() decides which registers ultimately end up being split
|
|
|
|
/// and spilled.
|
2011-05-25 23:58:36 +00:00
|
|
|
///
|
2011-07-02 01:37:09 +00:00
|
|
|
/// Cascade numbers are used to prevent infinite loops if this function is a
|
|
|
|
/// cyclic relation.
|
2011-07-08 20:46:18 +00:00
|
|
|
///
|
|
|
|
/// @param A The live range to be assigned.
|
|
|
|
/// @param IsHint True when A is about to be assigned to its preferred
|
|
|
|
/// register.
|
|
|
|
/// @param B The live range to be evicted.
|
|
|
|
/// @param BreaksHint True when B is already assigned to its preferred register.
|
|
|
|
bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
|
|
|
|
LiveInterval &B, bool BreaksHint) {
|
2011-07-25 15:25:43 +00:00
|
|
|
bool CanSplit = getStage(B) < RS_Spill;
|
2011-07-08 20:46:18 +00:00
|
|
|
|
|
|
|
// Be fairly aggressive about following hints as long as the evictee can be
|
|
|
|
// split.
|
|
|
|
if (CanSplit && IsHint && !BreaksHint)
|
|
|
|
return true;
|
|
|
|
|
2011-07-02 01:37:09 +00:00
|
|
|
return A.weight > B.weight;
|
2011-05-25 23:58:36 +00:00
|
|
|
}
|
|
|
|
|
2011-07-08 20:46:18 +00:00
|
|
|
/// canEvictInterference - Return true if all interferences between VirtReg and
|
|
|
|
/// PhysReg can be evicted. When OnlyCheap is set, don't do anything
|
|
|
|
///
|
|
|
|
/// @param VirtReg Live range that is about to be assigned.
|
|
|
|
/// @param PhysReg Desired register for assignment.
|
|
|
|
/// @prarm IsHint True when PhysReg is VirtReg's preferred register.
|
|
|
|
/// @param MaxCost Only look for cheaper candidates and update with new cost
|
|
|
|
/// when returning true.
|
|
|
|
/// @returns True when interference can be evicted cheaper than MaxCost.
|
2011-02-23 00:29:52 +00:00
|
|
|
bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
|
2011-07-08 20:46:18 +00:00
|
|
|
bool IsHint, EvictionCost &MaxCost) {
|
2011-07-02 01:37:09 +00:00
|
|
|
// Find VirtReg's cascade number. This will be unassigned if VirtReg was never
|
|
|
|
// involved in an eviction before. If a cascade number was assigned, deny
|
|
|
|
// evicting anything with the same or a newer cascade number. This prevents
|
|
|
|
// infinite eviction loops.
|
|
|
|
//
|
|
|
|
// This works out so a register without a cascade number is allowed to evict
|
|
|
|
// anything, and it can be evicted by anything.
|
|
|
|
unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
|
|
|
|
if (!Cascade)
|
|
|
|
Cascade = NextCascade;
|
|
|
|
|
2011-07-08 20:46:18 +00:00
|
|
|
EvictionCost Cost;
|
2011-02-23 00:29:52 +00:00
|
|
|
for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
|
|
|
|
LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
|
2011-04-11 21:47:01 +00:00
|
|
|
// If there is 10 or more interferences, chances are one is heavier.
|
2011-07-08 20:46:18 +00:00
|
|
|
if (Q.collectInterferingVRegs(10) >= 10)
|
2011-02-23 00:29:52 +00:00
|
|
|
return false;
|
|
|
|
|
2011-04-11 21:47:01 +00:00
|
|
|
// Check if any interfering live range is heavier than MaxWeight.
|
|
|
|
for (unsigned i = Q.interferingVRegs().size(); i; --i) {
|
|
|
|
LiveInterval *Intf = Q.interferingVRegs()[i - 1];
|
2011-02-23 00:29:52 +00:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
|
|
|
|
return false;
|
2011-07-08 20:46:18 +00:00
|
|
|
// Never evict spill products. They cannot split or spill.
|
2011-07-25 15:25:41 +00:00
|
|
|
if (getStage(*Intf) == RS_Done)
|
2011-07-02 01:37:09 +00:00
|
|
|
return false;
|
2011-07-08 20:46:18 +00:00
|
|
|
// Once a live range becomes small enough, it is urgent that we find a
|
|
|
|
// register for it. This is indicated by an infinite spill weight. These
|
|
|
|
// urgent live ranges get to evict almost anything.
|
|
|
|
bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable();
|
|
|
|
// Only evict older cascades or live ranges without a cascade.
|
|
|
|
unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
|
|
|
|
if (Cascade <= IntfCascade) {
|
|
|
|
if (!Urgent)
|
|
|
|
return false;
|
|
|
|
// We permit breaking cascades for urgent evictions. It should be the
|
|
|
|
// last resort, though, so make it really expensive.
|
|
|
|
Cost.BrokenHints += 10;
|
|
|
|
}
|
|
|
|
// Would this break a satisfied hint?
|
|
|
|
bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
|
|
|
|
// Update eviction cost.
|
|
|
|
Cost.BrokenHints += BreaksHint;
|
|
|
|
Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
|
|
|
|
// Abort if this would be too expensive.
|
|
|
|
if (!(Cost < MaxCost))
|
2011-05-25 23:58:36 +00:00
|
|
|
return false;
|
2011-07-08 20:46:18 +00:00
|
|
|
// Finally, apply the eviction policy for non-urgent evictions.
|
|
|
|
if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
|
2011-06-01 18:45:02 +00:00
|
|
|
return false;
|
2011-02-09 01:14:03 +00:00
|
|
|
}
|
|
|
|
}
|
2011-07-08 20:46:18 +00:00
|
|
|
MaxCost = Cost;
|
2011-02-23 00:29:52 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-07-08 20:46:18 +00:00
|
|
|
/// evictInterference - Evict any interferring registers that prevent VirtReg
|
|
|
|
/// from being assigned to Physreg. This assumes that canEvictInterference
|
|
|
|
/// returned true.
|
|
|
|
void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
|
|
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs) {
|
|
|
|
// Make sure that VirtReg has a cascade number, and assign that cascade
|
|
|
|
// number to every evicted register. These live ranges than then only be
|
|
|
|
// evicted by a newer cascade, preventing infinite loops.
|
|
|
|
unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
|
|
|
|
if (!Cascade)
|
|
|
|
Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
|
|
|
|
|
|
|
|
DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
|
|
|
|
<< " interference: Cascade " << Cascade << '\n');
|
|
|
|
for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
|
|
|
|
LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
|
|
|
|
assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
|
|
|
|
for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
|
|
|
|
LiveInterval *Intf = Q.interferingVRegs()[i];
|
|
|
|
unassign(*Intf, VRM->getPhys(Intf->reg));
|
|
|
|
assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
|
|
|
|
VirtReg.isSpillable() < Intf->isSpillable()) &&
|
|
|
|
"Cannot decrease cascade number, illegal eviction");
|
|
|
|
ExtraRegInfo[Intf->reg].Cascade = Cascade;
|
|
|
|
++NumEvicted;
|
|
|
|
NewVRegs.push_back(Intf);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-02-23 00:29:52 +00:00
|
|
|
/// tryEvict - Try to evict all interferences for a physreg.
|
2011-06-01 18:45:02 +00:00
|
|
|
/// @param VirtReg Currently unassigned virtual register.
|
|
|
|
/// @param Order Physregs to try.
|
|
|
|
/// @return Physreg to assign VirtReg, or 0.
|
2011-02-23 00:29:52 +00:00
|
|
|
unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
|
|
|
|
AllocationOrder &Order,
|
2011-04-20 18:19:48 +00:00
|
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs,
|
|
|
|
unsigned CostPerUseLimit) {
|
2011-02-23 00:29:52 +00:00
|
|
|
NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
|
|
|
|
|
2011-07-08 20:46:18 +00:00
|
|
|
// Keep track of the cheapest interference seen so far.
|
|
|
|
EvictionCost BestCost(~0u);
|
2011-02-23 00:29:52 +00:00
|
|
|
unsigned BestPhys = 0;
|
|
|
|
|
2011-07-08 20:46:18 +00:00
|
|
|
// When we are just looking for a reduced cost per use, don't break any
|
|
|
|
// hints, and only evict smaller spill weights.
|
|
|
|
if (CostPerUseLimit < ~0u) {
|
|
|
|
BestCost.BrokenHints = 0;
|
|
|
|
BestCost.MaxWeight = VirtReg.weight;
|
|
|
|
}
|
|
|
|
|
2011-02-23 00:29:52 +00:00
|
|
|
Order.rewind();
|
|
|
|
while (unsigned PhysReg = Order.next()) {
|
2011-04-20 18:19:48 +00:00
|
|
|
if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
|
|
|
|
continue;
|
2011-07-08 20:46:18 +00:00
|
|
|
// The first use of a callee-saved register in a function has cost 1.
|
|
|
|
// Don't start using a CSR when the CostPerUseLimit is low.
|
|
|
|
if (CostPerUseLimit == 1)
|
|
|
|
if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
|
|
|
|
if (!MRI->isPhysRegUsed(CSR)) {
|
|
|
|
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
|
|
|
|
<< PrintReg(CSR, TRI) << '\n');
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
|
2011-02-23 00:29:52 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Best so far.
|
|
|
|
BestPhys = PhysReg;
|
2011-07-08 20:46:18 +00:00
|
|
|
|
2011-02-25 01:04:22 +00:00
|
|
|
// Stop if the hint can be used.
|
|
|
|
if (Order.isHint(PhysReg))
|
|
|
|
break;
|
2011-02-09 01:14:03 +00:00
|
|
|
}
|
|
|
|
|
2011-02-23 00:29:52 +00:00
|
|
|
if (!BestPhys)
|
|
|
|
return 0;
|
|
|
|
|
2011-07-08 20:46:18 +00:00
|
|
|
evictInterference(VirtReg, BestPhys, NewVRegs);
|
2011-02-23 00:29:52 +00:00
|
|
|
return BestPhys;
|
2010-12-09 18:15:21 +00:00
|
|
|
}
|
|
|
|
|
2010-12-22 22:01:30 +00:00
|
|
|
|
2011-01-18 21:13:27 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Region Splitting
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2011-04-06 21:32:38 +00:00
|
|
|
/// addSplitConstraints - Fill out the SplitConstraints vector based on the
|
|
|
|
/// interference pattern in Physreg and its aliases. Add the constraints to
|
|
|
|
/// SpillPlacement and return the static cost of this split in Cost, assuming
|
|
|
|
/// that all preferences in SplitConstraints are met.
|
2011-04-09 02:59:09 +00:00
|
|
|
/// Return false if there are no bundles with positive bias.
|
|
|
|
bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
|
|
|
|
float &Cost) {
|
2011-04-06 03:57:00 +00:00
|
|
|
ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
|
2011-04-02 06:03:38 +00:00
|
|
|
|
2011-01-18 21:13:27 +00:00
|
|
|
// Reset interference dependent info.
|
2011-04-06 03:57:00 +00:00
|
|
|
SplitConstraints.resize(UseBlocks.size());
|
2011-03-05 01:10:31 +00:00
|
|
|
float StaticCost = 0;
|
2011-04-06 03:57:00 +00:00
|
|
|
for (unsigned i = 0; i != UseBlocks.size(); ++i) {
|
|
|
|
const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
|
2011-03-05 01:10:31 +00:00
|
|
|
SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
|
|
|
|
|
2011-02-09 22:50:26 +00:00
|
|
|
BC.Number = BI.MBB->getNumber();
|
2011-04-02 06:03:38 +00:00
|
|
|
Intf.moveToBlock(BC.Number);
|
2011-04-06 03:57:00 +00:00
|
|
|
BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
|
|
|
|
BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
|
2011-08-02 23:04:06 +00:00
|
|
|
BC.ChangesValue = BI.FirstDef;
|
2011-01-18 21:13:27 +00:00
|
|
|
|
2011-04-02 06:03:38 +00:00
|
|
|
if (!Intf.hasInterference())
|
|
|
|
continue;
|
|
|
|
|
2011-03-05 01:10:31 +00:00
|
|
|
// Number of spill code instructions to insert.
|
|
|
|
unsigned Ins = 0;
|
|
|
|
|
|
|
|
// Interference for the live-in value.
|
2011-04-02 06:03:38 +00:00
|
|
|
if (BI.LiveIn) {
|
2011-04-04 15:32:15 +00:00
|
|
|
if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
|
2011-04-06 03:57:00 +00:00
|
|
|
BC.Entry = SpillPlacement::MustSpill, ++Ins;
|
2011-08-02 22:54:14 +00:00
|
|
|
else if (Intf.first() < BI.FirstInstr)
|
2011-03-05 01:10:31 +00:00
|
|
|
BC.Entry = SpillPlacement::PrefSpill, ++Ins;
|
2011-08-02 22:54:14 +00:00
|
|
|
else if (Intf.first() < BI.LastInstr)
|
2011-03-05 01:10:31 +00:00
|
|
|
++Ins;
|
2011-02-08 23:02:58 +00:00
|
|
|
}
|
2011-01-18 21:13:27 +00:00
|
|
|
|
2011-03-05 01:10:31 +00:00
|
|
|
// Interference for the live-out value.
|
2011-04-02 06:03:38 +00:00
|
|
|
if (BI.LiveOut) {
|
2011-04-05 04:20:29 +00:00
|
|
|
if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
|
2011-04-06 03:57:00 +00:00
|
|
|
BC.Exit = SpillPlacement::MustSpill, ++Ins;
|
2011-08-02 22:54:14 +00:00
|
|
|
else if (Intf.last() > BI.LastInstr)
|
2011-03-05 01:10:31 +00:00
|
|
|
BC.Exit = SpillPlacement::PrefSpill, ++Ins;
|
2011-08-02 22:54:14 +00:00
|
|
|
else if (Intf.last() > BI.FirstInstr)
|
2011-03-05 01:10:31 +00:00
|
|
|
++Ins;
|
2011-01-18 21:13:27 +00:00
|
|
|
}
|
|
|
|
|
2011-03-05 01:10:31 +00:00
|
|
|
// Accumulate the total frequency of inserted spill code.
|
|
|
|
if (Ins)
|
|
|
|
StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
|
2011-01-18 21:13:27 +00:00
|
|
|
}
|
2011-04-09 02:59:09 +00:00
|
|
|
Cost = StaticCost;
|
2011-04-06 03:57:00 +00:00
|
|
|
|
2011-04-06 21:32:38 +00:00
|
|
|
// Add constraints for use-blocks. Note that these are the only constraints
|
|
|
|
// that may add a positive bias, it is downhill from here.
|
|
|
|
SpillPlacer->addConstraints(SplitConstraints);
|
2011-04-09 02:59:09 +00:00
|
|
|
return SpillPlacer->scanActiveBundles();
|
|
|
|
}
|
2011-04-06 03:57:00 +00:00
|
|
|
|
|
|
|
|
2011-04-09 02:59:09 +00:00
|
|
|
/// addThroughConstraints - Add constraints and links to SpillPlacer from the
|
|
|
|
/// live-through blocks in Blocks.
|
|
|
|
void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
|
|
|
|
ArrayRef<unsigned> Blocks) {
|
2011-04-06 21:32:38 +00:00
|
|
|
const unsigned GroupSize = 8;
|
|
|
|
SpillPlacement::BlockConstraint BCS[GroupSize];
|
2011-04-09 02:59:09 +00:00
|
|
|
unsigned TBS[GroupSize];
|
|
|
|
unsigned B = 0, T = 0;
|
2011-04-06 03:57:00 +00:00
|
|
|
|
2011-04-09 02:59:09 +00:00
|
|
|
for (unsigned i = 0; i != Blocks.size(); ++i) {
|
|
|
|
unsigned Number = Blocks[i];
|
2011-04-06 21:32:38 +00:00
|
|
|
Intf.moveToBlock(Number);
|
|
|
|
|
2011-04-07 17:27:46 +00:00
|
|
|
if (!Intf.hasInterference()) {
|
2011-04-09 02:59:09 +00:00
|
|
|
assert(T < GroupSize && "Array overflow");
|
|
|
|
TBS[T] = Number;
|
|
|
|
if (++T == GroupSize) {
|
2011-07-18 12:00:32 +00:00
|
|
|
SpillPlacer->addLinks(makeArrayRef(TBS, T));
|
2011-04-09 02:59:09 +00:00
|
|
|
T = 0;
|
|
|
|
}
|
2011-04-07 17:27:46 +00:00
|
|
|
continue;
|
2011-04-06 21:32:38 +00:00
|
|
|
}
|
|
|
|
|
2011-04-09 02:59:09 +00:00
|
|
|
assert(B < GroupSize && "Array overflow");
|
|
|
|
BCS[B].Number = Number;
|
|
|
|
|
2011-04-07 17:27:46 +00:00
|
|
|
// Interference for the live-in value.
|
|
|
|
if (Intf.first() <= Indexes->getMBBStartIdx(Number))
|
|
|
|
BCS[B].Entry = SpillPlacement::MustSpill;
|
|
|
|
else
|
|
|
|
BCS[B].Entry = SpillPlacement::PrefSpill;
|
|
|
|
|
|
|
|
// Interference for the live-out value.
|
|
|
|
if (Intf.last() >= SA->getLastSplitPoint(Number))
|
|
|
|
BCS[B].Exit = SpillPlacement::MustSpill;
|
|
|
|
else
|
|
|
|
BCS[B].Exit = SpillPlacement::PrefSpill;
|
|
|
|
|
2011-04-06 21:32:38 +00:00
|
|
|
if (++B == GroupSize) {
|
|
|
|
ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
|
|
|
|
SpillPlacer->addConstraints(Array);
|
|
|
|
B = 0;
|
|
|
|
}
|
2011-04-06 03:57:00 +00:00
|
|
|
}
|
|
|
|
|
2011-04-06 21:32:38 +00:00
|
|
|
ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
|
|
|
|
SpillPlacer->addConstraints(Array);
|
2011-07-18 12:00:32 +00:00
|
|
|
SpillPlacer->addLinks(makeArrayRef(TBS, T));
|
2011-01-18 21:13:27 +00:00
|
|
|
}
|
|
|
|
|
2011-07-14 00:17:10 +00:00
|
|
|
void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
|
2011-04-12 21:30:53 +00:00
|
|
|
// Keep track of through blocks that have not been added to SpillPlacer.
|
|
|
|
BitVector Todo = SA->getThroughBlocks();
|
|
|
|
SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
|
|
|
|
unsigned AddedTo = 0;
|
2011-04-09 02:59:09 +00:00
|
|
|
#ifndef NDEBUG
|
|
|
|
unsigned Visited = 0;
|
|
|
|
#endif
|
2011-04-12 21:30:53 +00:00
|
|
|
|
2011-04-09 02:59:09 +00:00
|
|
|
for (;;) {
|
|
|
|
ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
|
|
|
|
// Find new through blocks in the periphery of PrefRegBundles.
|
|
|
|
for (int i = 0, e = NewBundles.size(); i != e; ++i) {
|
|
|
|
unsigned Bundle = NewBundles[i];
|
|
|
|
// Look at all blocks connected to Bundle in the full graph.
|
|
|
|
ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
|
|
|
|
for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
unsigned Block = *I;
|
2011-04-12 21:30:53 +00:00
|
|
|
if (!Todo.test(Block))
|
2011-04-09 02:59:09 +00:00
|
|
|
continue;
|
2011-04-12 21:30:53 +00:00
|
|
|
Todo.reset(Block);
|
2011-04-09 02:59:09 +00:00
|
|
|
// This is a new through block. Add it to SpillPlacer later.
|
2011-04-12 21:30:53 +00:00
|
|
|
ActiveBlocks.push_back(Block);
|
2011-04-09 02:59:09 +00:00
|
|
|
#ifndef NDEBUG
|
|
|
|
++Visited;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Any new blocks to add?
|
2011-07-05 18:46:42 +00:00
|
|
|
if (ActiveBlocks.size() == AddedTo)
|
|
|
|
break;
|
2011-07-23 03:22:33 +00:00
|
|
|
|
|
|
|
// Compute through constraints from the interference, or assume that all
|
|
|
|
// through blocks prefer spilling when forming compact regions.
|
|
|
|
ArrayRef<unsigned> NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
|
|
|
|
if (Cand.PhysReg)
|
|
|
|
addThroughConstraints(Cand.Intf, NewBlocks);
|
|
|
|
else
|
2011-08-03 23:09:38 +00:00
|
|
|
// Provide a strong negative bias on through blocks to prevent unwanted
|
|
|
|
// liveness on loop backedges.
|
|
|
|
SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
|
2011-07-05 18:46:42 +00:00
|
|
|
AddedTo = ActiveBlocks.size();
|
|
|
|
|
2011-04-09 02:59:09 +00:00
|
|
|
// Perhaps iterating can enable more bundles?
|
|
|
|
SpillPlacer->iterate();
|
|
|
|
}
|
|
|
|
DEBUG(dbgs() << ", v=" << Visited);
|
|
|
|
}
|
2011-03-05 01:10:31 +00:00
|
|
|
|
2011-07-23 03:41:57 +00:00
|
|
|
/// calcCompactRegion - Compute the set of edge bundles that should be live
|
|
|
|
/// when splitting the current live range into compact regions. Compact
|
|
|
|
/// regions can be computed without looking at interference. They are the
|
|
|
|
/// regions formed by removing all the live-through blocks from the live range.
|
|
|
|
///
|
|
|
|
/// Returns false if the current live range is already compact, or if the
|
|
|
|
/// compact regions would form single block regions anyway.
|
|
|
|
bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
|
|
|
|
// Without any through blocks, the live range is already compact.
|
|
|
|
if (!SA->getNumThroughBlocks())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Compact regions don't correspond to any physreg.
|
|
|
|
Cand.reset(IntfCache, 0);
|
|
|
|
|
|
|
|
DEBUG(dbgs() << "Compact region bundles");
|
|
|
|
|
|
|
|
// Use the spill placer to determine the live bundles. GrowRegion pretends
|
|
|
|
// that all the through blocks have interference when PhysReg is unset.
|
|
|
|
SpillPlacer->prepare(Cand.LiveBundles);
|
|
|
|
|
|
|
|
// The static split cost will be zero since Cand.Intf reports no interference.
|
|
|
|
float Cost;
|
|
|
|
if (!addSplitConstraints(Cand.Intf, Cost)) {
|
|
|
|
DEBUG(dbgs() << ", none.\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
growRegion(Cand);
|
|
|
|
SpillPlacer->finish();
|
|
|
|
|
|
|
|
if (!Cand.LiveBundles.any()) {
|
|
|
|
DEBUG(dbgs() << ", none.\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
DEBUG({
|
|
|
|
for (int i = Cand.LiveBundles.find_first(); i>=0;
|
|
|
|
i = Cand.LiveBundles.find_next(i))
|
|
|
|
dbgs() << " EB#" << i;
|
|
|
|
dbgs() << ".\n";
|
|
|
|
});
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-04-22 22:47:40 +00:00
|
|
|
/// calcSpillCost - Compute how expensive it would be to split the live range in
|
|
|
|
/// SA around all use blocks instead of forming bundle regions.
|
|
|
|
float RAGreedy::calcSpillCost() {
|
|
|
|
float Cost = 0;
|
|
|
|
ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
|
|
|
|
for (unsigned i = 0; i != UseBlocks.size(); ++i) {
|
|
|
|
const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
|
|
|
|
unsigned Number = BI.MBB->getNumber();
|
|
|
|
// We normally only need one spill instruction - a load or a store.
|
|
|
|
Cost += SpillPlacer->getBlockFrequency(Number);
|
|
|
|
|
|
|
|
// Unless the value is redefined in the block.
|
2011-08-02 23:04:08 +00:00
|
|
|
if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
|
|
|
|
Cost += SpillPlacer->getBlockFrequency(Number);
|
2011-04-22 22:47:40 +00:00
|
|
|
}
|
|
|
|
return Cost;
|
|
|
|
}
|
|
|
|
|
2011-01-18 21:13:27 +00:00
|
|
|
/// calcGlobalSplitCost - Return the global split cost of following the split
|
|
|
|
/// pattern in LiveBundles. This cost should be added to the local cost of the
|
2011-03-05 01:10:31 +00:00
|
|
|
/// interference pattern in SplitConstraints.
|
2011-01-18 21:13:27 +00:00
|
|
|
///
|
2011-07-14 00:17:10 +00:00
|
|
|
float RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
|
2011-01-18 21:13:27 +00:00
|
|
|
float GlobalCost = 0;
|
2011-04-12 21:30:53 +00:00
|
|
|
const BitVector &LiveBundles = Cand.LiveBundles;
|
2011-04-06 03:57:00 +00:00
|
|
|
ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
|
|
|
|
for (unsigned i = 0; i != UseBlocks.size(); ++i) {
|
|
|
|
const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
|
2011-03-05 01:10:31 +00:00
|
|
|
SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
|
2011-03-05 03:28:51 +00:00
|
|
|
bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
|
|
|
|
bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
|
|
|
|
unsigned Ins = 0;
|
|
|
|
|
2011-04-06 03:57:00 +00:00
|
|
|
if (BI.LiveIn)
|
|
|
|
Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
|
|
|
|
if (BI.LiveOut)
|
|
|
|
Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
|
2011-03-05 03:28:51 +00:00
|
|
|
if (Ins)
|
|
|
|
GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
|
2011-01-18 21:13:27 +00:00
|
|
|
}
|
2011-04-06 03:57:00 +00:00
|
|
|
|
2011-04-12 21:30:53 +00:00
|
|
|
for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
|
|
|
|
unsigned Number = Cand.ActiveBlocks[i];
|
2011-04-06 03:57:00 +00:00
|
|
|
bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
|
|
|
|
bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
|
2011-04-06 21:32:41 +00:00
|
|
|
if (!RegIn && !RegOut)
|
|
|
|
continue;
|
|
|
|
if (RegIn && RegOut) {
|
|
|
|
// We need double spill code if this block has interference.
|
2011-07-14 00:17:10 +00:00
|
|
|
Cand.Intf.moveToBlock(Number);
|
|
|
|
if (Cand.Intf.hasInterference())
|
2011-04-06 21:32:41 +00:00
|
|
|
GlobalCost += 2*SpillPlacer->getBlockFrequency(Number);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// live-in / stack-out or stack-in live-out.
|
|
|
|
GlobalCost += SpillPlacer->getBlockFrequency(Number);
|
2011-04-06 03:57:00 +00:00
|
|
|
}
|
2011-01-18 21:13:27 +00:00
|
|
|
return GlobalCost;
|
|
|
|
}
|
|
|
|
|
2011-07-26 23:41:46 +00:00
|
|
|
/// splitAroundRegion - Split the current live range around the regions
|
|
|
|
/// determined by BundleCand and GlobalCand.
|
2011-01-19 22:11:48 +00:00
|
|
|
///
|
2011-07-26 23:41:46 +00:00
|
|
|
/// Before calling this function, GlobalCand and BundleCand must be initialized
|
|
|
|
/// so each bundle is assigned to a valid candidate, or NoCand for the
|
|
|
|
/// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
|
|
|
|
/// objects must be initialized for the current live range, and intervals
|
|
|
|
/// created for the used candidates.
|
2011-01-19 22:11:48 +00:00
|
|
|
///
|
2011-07-26 23:41:46 +00:00
|
|
|
/// @param LREdit The LiveRangeEdit object handling the current split.
|
|
|
|
/// @param UsedCands List of used GlobalCand entries. Every BundleCand value
|
|
|
|
/// must appear in this list.
|
|
|
|
void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
|
|
|
|
ArrayRef<unsigned> UsedCands) {
|
|
|
|
// These are the intervals created for new global ranges. We may create more
|
|
|
|
// intervals for local ranges.
|
|
|
|
const unsigned NumGlobalIntvs = LREdit.size();
|
|
|
|
DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
|
|
|
|
assert(NumGlobalIntvs && "No global intervals configured");
|
2011-01-19 22:11:48 +00:00
|
|
|
|
Reapply r134047 now that the world is ready for it.
This patch will sometimes choose live range split points next to
interference instead of always splitting next to a register point. That
means spill code can now appear almost anywhere, and it was necessary
to fix code that didn't expect that.
The difficult places were:
- Between a CALL returning a value on the x87 stack and the
corresponding FpPOP_RETVAL (was FpGET_ST0). Probably also near x87
inline assembly, but that didn't actually show up in testing.
- Between a CALL popping arguments off the stack and the corresponding
ADJCALLSTACKUP.
Both are fixed now. The only place spill code can't appear is after
terminators, see SplitAnalysis::getLastSplitPoint.
Original commit message:
Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art.
This function has to deal with a lot of special cases, and the old
version got it wrong sometimes. In particular, it would sometimes leave
multiple uses in the stack interval in a single block. That causes bad
code with multiple reloads in the same basic block.
The new version handles block entry and exit in a single pass. It first
eliminates all the easy cases, and then goes on to create a local
interval for the blocks with difficult interference. Previously, we
would only create the local interval for completely isolated blocks.
It can happen that the stack interval becomes completely empty because
we could allocate a register in all edge bundles, and the new local
intervals deal with the interference. The empty stack interval is
harmless, but we need to remove a SplitKit assertion that checks for
empty intervals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 01:30:39 +00:00
|
|
|
// First handle all the blocks with uses.
|
2011-04-06 03:57:00 +00:00
|
|
|
ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
|
|
|
|
for (unsigned i = 0; i != UseBlocks.size(); ++i) {
|
|
|
|
const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
|
2011-07-26 23:41:46 +00:00
|
|
|
unsigned Number = BI.MBB->getNumber();
|
|
|
|
unsigned IntvIn = 0, IntvOut = 0;
|
|
|
|
SlotIndex IntfIn, IntfOut;
|
|
|
|
if (BI.LiveIn) {
|
|
|
|
unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
|
|
|
|
if (CandIn != NoCand) {
|
|
|
|
GlobalSplitCandidate &Cand = GlobalCand[CandIn];
|
|
|
|
IntvIn = Cand.IntvIdx;
|
|
|
|
Cand.Intf.moveToBlock(Number);
|
|
|
|
IntfIn = Cand.Intf.first();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (BI.LiveOut) {
|
|
|
|
unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
|
|
|
|
if (CandOut != NoCand) {
|
|
|
|
GlobalSplitCandidate &Cand = GlobalCand[CandOut];
|
|
|
|
IntvOut = Cand.IntvIdx;
|
|
|
|
Cand.Intf.moveToBlock(Number);
|
|
|
|
IntfOut = Cand.Intf.last();
|
|
|
|
}
|
|
|
|
}
|
2011-01-19 22:11:48 +00:00
|
|
|
|
2011-04-12 19:32:53 +00:00
|
|
|
// Create separate intervals for isolated blocks with multiple uses.
|
2011-07-26 23:41:46 +00:00
|
|
|
if (!IntvIn && !IntvOut) {
|
2011-04-12 19:32:53 +00:00
|
|
|
DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
|
2011-07-26 23:41:46 +00:00
|
|
|
if (!BI.isOneInstr())
|
Reapply r134047 now that the world is ready for it.
This patch will sometimes choose live range split points next to
interference instead of always splitting next to a register point. That
means spill code can now appear almost anywhere, and it was necessary
to fix code that didn't expect that.
The difficult places were:
- Between a CALL returning a value on the x87 stack and the
corresponding FpPOP_RETVAL (was FpGET_ST0). Probably also near x87
inline assembly, but that didn't actually show up in testing.
- Between a CALL popping arguments off the stack and the corresponding
ADJCALLSTACKUP.
Both are fixed now. The only place spill code can't appear is after
terminators, see SplitAnalysis::getLastSplitPoint.
Original commit message:
Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art.
This function has to deal with a lot of special cases, and the old
version got it wrong sometimes. In particular, it would sometimes leave
multiple uses in the stack interval in a single block. That causes bad
code with multiple reloads in the same basic block.
The new version handles block entry and exit in a single pass. It first
eliminates all the easy cases, and then goes on to create a local
interval for the blocks with difficult interference. Previously, we
would only create the local interval for completely isolated blocks.
It can happen that the stack interval becomes completely empty because
we could allocate a register in all edge bundles, and the new local
intervals deal with the interference. The empty stack interval is
harmless, but we need to remove a SplitKit assertion that checks for
empty intervals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 01:30:39 +00:00
|
|
|
SE->splitSingleBlock(BI);
|
2011-04-12 19:32:53 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2011-07-26 23:41:46 +00:00
|
|
|
if (IntvIn && IntvOut)
|
|
|
|
SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
|
|
|
|
else if (IntvIn)
|
|
|
|
SE->splitRegInBlock(BI, IntvIn, IntfIn);
|
2011-07-15 21:47:57 +00:00
|
|
|
else
|
2011-07-26 23:41:46 +00:00
|
|
|
SE->splitRegOutBlock(BI, IntvOut, IntfOut);
|
2011-01-19 22:11:48 +00:00
|
|
|
}
|
|
|
|
|
2011-07-26 23:41:46 +00:00
|
|
|
// Handle live-through blocks. The relevant live-through blocks are stored in
|
|
|
|
// the ActiveBlocks list with each candidate. We need to filter out
|
|
|
|
// duplicates.
|
|
|
|
BitVector Todo = SA->getThroughBlocks();
|
|
|
|
for (unsigned c = 0; c != UsedCands.size(); ++c) {
|
|
|
|
ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
|
|
|
|
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
|
|
|
|
unsigned Number = Blocks[i];
|
|
|
|
if (!Todo.test(Number))
|
|
|
|
continue;
|
|
|
|
Todo.reset(Number);
|
|
|
|
|
|
|
|
unsigned IntvIn = 0, IntvOut = 0;
|
|
|
|
SlotIndex IntfIn, IntfOut;
|
|
|
|
|
|
|
|
unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
|
|
|
|
if (CandIn != NoCand) {
|
|
|
|
GlobalSplitCandidate &Cand = GlobalCand[CandIn];
|
|
|
|
IntvIn = Cand.IntvIdx;
|
|
|
|
Cand.Intf.moveToBlock(Number);
|
|
|
|
IntfIn = Cand.Intf.first();
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
|
|
|
|
if (CandOut != NoCand) {
|
|
|
|
GlobalSplitCandidate &Cand = GlobalCand[CandOut];
|
|
|
|
IntvOut = Cand.IntvIdx;
|
|
|
|
Cand.Intf.moveToBlock(Number);
|
|
|
|
IntfOut = Cand.Intf.last();
|
|
|
|
}
|
|
|
|
if (!IntvIn && !IntvOut)
|
|
|
|
continue;
|
|
|
|
SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
|
|
|
|
}
|
2011-04-06 03:57:00 +00:00
|
|
|
}
|
|
|
|
|
2011-02-17 22:53:48 +00:00
|
|
|
++NumGlobalSplits;
|
2011-01-19 22:11:48 +00:00
|
|
|
|
2011-04-21 18:38:15 +00:00
|
|
|
SmallVector<unsigned, 8> IntvMap;
|
|
|
|
SE->finish(&IntvMap);
|
2011-07-26 23:41:46 +00:00
|
|
|
DebugVars->splitRegister(SA->getParent().reg, LREdit.regs());
|
2011-05-06 18:00:02 +00:00
|
|
|
|
2011-07-02 01:37:09 +00:00
|
|
|
ExtraRegInfo.resize(MRI->getNumVirtRegs());
|
2011-05-28 02:32:57 +00:00
|
|
|
unsigned OrigBlocks = SA->getNumLiveBlocks();
|
2011-04-21 18:38:15 +00:00
|
|
|
|
|
|
|
// Sort out the new intervals created by splitting. We get four kinds:
|
|
|
|
// - Remainder intervals should not be split again.
|
|
|
|
// - Candidate intervals can be assigned to Cand.PhysReg.
|
|
|
|
// - Block-local splits are candidates for local splitting.
|
|
|
|
// - DCE leftovers should go back on the queue.
|
|
|
|
for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
|
2011-07-02 01:37:09 +00:00
|
|
|
LiveInterval &Reg = *LREdit.get(i);
|
2011-04-21 18:38:15 +00:00
|
|
|
|
|
|
|
// Ignore old intervals from DCE.
|
2011-07-02 01:37:09 +00:00
|
|
|
if (getStage(Reg) != RS_New)
|
2011-04-21 18:38:15 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Remainder interval. Don't try splitting again, spill if it doesn't
|
|
|
|
// allocate.
|
|
|
|
if (IntvMap[i] == 0) {
|
2011-07-25 15:25:41 +00:00
|
|
|
setStage(Reg, RS_Spill);
|
2011-04-21 18:38:15 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2011-07-26 23:41:46 +00:00
|
|
|
// Global intervals. Allow repeated splitting as long as the number of live
|
|
|
|
// blocks is strictly decreasing.
|
|
|
|
if (IntvMap[i] < NumGlobalIntvs) {
|
2011-07-02 01:37:09 +00:00
|
|
|
if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
|
2011-04-26 22:33:12 +00:00
|
|
|
DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
|
|
|
|
<< " blocks as original.\n");
|
|
|
|
// Don't allow repeated splitting as a safe guard against looping.
|
2011-07-25 15:25:43 +00:00
|
|
|
setStage(Reg, RS_Split2);
|
2011-04-26 22:33:12 +00:00
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Other intervals are treated as new. This includes local intervals created
|
|
|
|
// for blocks with multiple uses, and anything created by DCE.
|
2011-04-21 18:38:15 +00:00
|
|
|
}
|
|
|
|
|
2011-03-27 22:49:21 +00:00
|
|
|
if (VerifyEnabled)
|
2011-01-19 22:11:48 +00:00
|
|
|
MF->verify(this, "After splitting live range around region");
|
|
|
|
}
|
|
|
|
|
2011-01-18 21:13:27 +00:00
|
|
|
unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
|
|
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs) {
|
2011-07-14 00:17:10 +00:00
|
|
|
unsigned NumCands = 0;
|
2011-07-26 23:41:46 +00:00
|
|
|
unsigned BestCand = NoCand;
|
|
|
|
float BestCost;
|
|
|
|
SmallVector<unsigned, 8> UsedCands;
|
|
|
|
|
|
|
|
// Check if we can split this live range around a compact region.
|
|
|
|
bool HasCompact = CompactRegions && calcCompactRegion(GlobalCand.front());
|
|
|
|
if (HasCompact) {
|
|
|
|
// Yes, keep GlobalCand[0] as the compact region candidate.
|
|
|
|
NumCands = 1;
|
|
|
|
BestCost = HUGE_VALF;
|
|
|
|
} else {
|
|
|
|
// No benefit from the compact region, our fallback will be per-block
|
|
|
|
// splitting. Make sure we find a solution that is cheaper than spilling.
|
|
|
|
BestCost = Hysteresis * calcSpillCost();
|
|
|
|
DEBUG(dbgs() << "Cost of isolating all blocks = " << BestCost << '\n');
|
|
|
|
}
|
2011-03-05 01:10:31 +00:00
|
|
|
|
2011-01-18 21:13:27 +00:00
|
|
|
Order.rewind();
|
2011-07-14 00:17:10 +00:00
|
|
|
while (unsigned PhysReg = Order.next()) {
|
2011-07-14 05:35:11 +00:00
|
|
|
// Discard bad candidates before we run out of interference cache cursors.
|
|
|
|
// This will only affect register classes with a lot of registers (>32).
|
|
|
|
if (NumCands == IntfCache.getMaxCursors()) {
|
|
|
|
unsigned WorstCount = ~0u;
|
|
|
|
unsigned Worst = 0;
|
|
|
|
for (unsigned i = 0; i != NumCands; ++i) {
|
2011-07-26 23:41:46 +00:00
|
|
|
if (i == BestCand || !GlobalCand[i].PhysReg)
|
2011-07-14 05:35:11 +00:00
|
|
|
continue;
|
|
|
|
unsigned Count = GlobalCand[i].LiveBundles.count();
|
|
|
|
if (Count < WorstCount)
|
|
|
|
Worst = i, WorstCount = Count;
|
|
|
|
}
|
|
|
|
--NumCands;
|
|
|
|
GlobalCand[Worst] = GlobalCand[NumCands];
|
|
|
|
}
|
|
|
|
|
2011-07-14 00:17:10 +00:00
|
|
|
if (GlobalCand.size() <= NumCands)
|
|
|
|
GlobalCand.resize(NumCands+1);
|
|
|
|
GlobalSplitCandidate &Cand = GlobalCand[NumCands];
|
|
|
|
Cand.reset(IntfCache, PhysReg);
|
2011-03-05 01:10:31 +00:00
|
|
|
|
2011-07-14 00:17:10 +00:00
|
|
|
SpillPlacer->prepare(Cand.LiveBundles);
|
2011-04-06 21:32:38 +00:00
|
|
|
float Cost;
|
2011-07-14 00:17:10 +00:00
|
|
|
if (!addSplitConstraints(Cand.Intf, Cost)) {
|
2011-04-09 02:59:09 +00:00
|
|
|
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
|
2011-04-06 21:32:38 +00:00
|
|
|
continue;
|
|
|
|
}
|
2011-04-09 02:59:09 +00:00
|
|
|
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
|
2011-04-22 22:47:40 +00:00
|
|
|
if (Cost >= BestCost) {
|
|
|
|
DEBUG({
|
|
|
|
if (BestCand == NoCand)
|
|
|
|
dbgs() << " worse than no bundles\n";
|
|
|
|
else
|
|
|
|
dbgs() << " worse than "
|
|
|
|
<< PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
|
|
|
|
});
|
2011-01-18 21:13:27 +00:00
|
|
|
continue;
|
2011-03-05 03:28:51 +00:00
|
|
|
}
|
2011-07-14 00:17:10 +00:00
|
|
|
growRegion(Cand);
|
2011-01-19 22:11:48 +00:00
|
|
|
|
2011-04-06 19:13:57 +00:00
|
|
|
SpillPlacer->finish();
|
|
|
|
|
2011-01-19 22:11:48 +00:00
|
|
|
// No live bundles, defer to splitSingleBlocks().
|
2011-07-14 00:17:10 +00:00
|
|
|
if (!Cand.LiveBundles.any()) {
|
2011-03-05 03:28:51 +00:00
|
|
|
DEBUG(dbgs() << " no bundles.\n");
|
2011-01-19 22:11:48 +00:00
|
|
|
continue;
|
2011-03-05 03:28:51 +00:00
|
|
|
}
|
2011-01-19 22:11:48 +00:00
|
|
|
|
2011-07-14 00:17:10 +00:00
|
|
|
Cost += calcGlobalSplitCost(Cand);
|
2011-03-05 03:28:51 +00:00
|
|
|
DEBUG({
|
|
|
|
dbgs() << ", total = " << Cost << " with bundles";
|
2011-07-14 00:17:10 +00:00
|
|
|
for (int i = Cand.LiveBundles.find_first(); i>=0;
|
|
|
|
i = Cand.LiveBundles.find_next(i))
|
2011-03-05 03:28:51 +00:00
|
|
|
dbgs() << " EB#" << i;
|
|
|
|
dbgs() << ".\n";
|
|
|
|
});
|
2011-04-22 22:47:40 +00:00
|
|
|
if (Cost < BestCost) {
|
2011-07-14 00:17:10 +00:00
|
|
|
BestCand = NumCands;
|
2011-04-22 22:47:40 +00:00
|
|
|
BestCost = Hysteresis * Cost; // Prevent rounding effects.
|
2011-01-18 21:13:27 +00:00
|
|
|
}
|
2011-07-14 00:17:10 +00:00
|
|
|
++NumCands;
|
2011-01-18 21:13:27 +00:00
|
|
|
}
|
2011-01-19 22:11:48 +00:00
|
|
|
|
2011-07-26 23:41:46 +00:00
|
|
|
// No solutions found, fall back to single block splitting.
|
|
|
|
if (!HasCompact && BestCand == NoCand)
|
2011-01-19 22:11:48 +00:00
|
|
|
return 0;
|
|
|
|
|
2011-07-26 23:41:46 +00:00
|
|
|
// Prepare split editor.
|
|
|
|
LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
|
|
|
|
SE->reset(LREdit);
|
|
|
|
|
|
|
|
// Assign all edge bundles to the preferred candidate, or NoCand.
|
|
|
|
BundleCand.assign(Bundles->getNumBundles(), NoCand);
|
|
|
|
|
|
|
|
// Assign bundles for the best candidate region.
|
|
|
|
if (BestCand != NoCand) {
|
|
|
|
GlobalSplitCandidate &Cand = GlobalCand[BestCand];
|
|
|
|
if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
|
|
|
|
UsedCands.push_back(BestCand);
|
|
|
|
Cand.IntvIdx = SE->openIntv();
|
|
|
|
DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
|
|
|
|
<< B << " bundles, intv " << Cand.IntvIdx << ".\n");
|
2011-08-03 23:07:27 +00:00
|
|
|
(void)B;
|
2011-07-26 23:41:46 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Assign bundles for the compact region.
|
|
|
|
if (HasCompact) {
|
|
|
|
GlobalSplitCandidate &Cand = GlobalCand.front();
|
|
|
|
assert(!Cand.PhysReg && "Compact region has no physreg");
|
|
|
|
if (unsigned B = Cand.getBundles(BundleCand, 0)) {
|
|
|
|
UsedCands.push_back(0);
|
|
|
|
Cand.IntvIdx = SE->openIntv();
|
|
|
|
DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
|
|
|
|
<< Cand.IntvIdx << ".\n");
|
2011-08-03 23:07:27 +00:00
|
|
|
(void)B;
|
2011-07-26 23:41:46 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
splitAroundRegion(LREdit, UsedCands);
|
2011-01-18 21:13:27 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-19 22:11:48 +00:00
|
|
|
|
2011-02-17 19:13:53 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Local Splitting
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
|
|
/// calcGapWeights - Compute the maximum spill weight that needs to be evicted
|
|
|
|
/// in order to use PhysReg between two entries in SA->UseSlots.
|
|
|
|
///
|
|
|
|
/// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
|
|
|
|
///
|
|
|
|
void RAGreedy::calcGapWeights(unsigned PhysReg,
|
|
|
|
SmallVectorImpl<float> &GapWeight) {
|
2011-04-06 03:57:00 +00:00
|
|
|
assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
|
|
|
|
const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
|
2011-02-17 19:13:53 +00:00
|
|
|
const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
|
|
|
|
const unsigned NumGaps = Uses.size()-1;
|
|
|
|
|
|
|
|
// Start and end points for the interference check.
|
2011-08-02 22:54:14 +00:00
|
|
|
SlotIndex StartIdx =
|
|
|
|
BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
|
|
|
|
SlotIndex StopIdx =
|
|
|
|
BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
|
2011-02-17 19:13:53 +00:00
|
|
|
|
|
|
|
GapWeight.assign(NumGaps, 0.0f);
|
|
|
|
|
|
|
|
// Add interference from each overlapping register.
|
|
|
|
for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
|
|
|
|
if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
|
|
|
|
.checkInterference())
|
|
|
|
continue;
|
|
|
|
|
2011-08-02 22:54:14 +00:00
|
|
|
// We know that VirtReg is a continuous interval from FirstInstr to
|
|
|
|
// LastInstr, so we don't need InterferenceQuery.
|
2011-02-17 19:13:53 +00:00
|
|
|
//
|
|
|
|
// Interference that overlaps an instruction is counted in both gaps
|
|
|
|
// surrounding the instruction. The exception is interference before
|
|
|
|
// StartIdx and after StopIdx.
|
|
|
|
//
|
|
|
|
LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
|
|
|
|
for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
|
|
|
|
// Skip the gaps before IntI.
|
|
|
|
while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
|
|
|
|
if (++Gap == NumGaps)
|
|
|
|
break;
|
|
|
|
if (Gap == NumGaps)
|
|
|
|
break;
|
|
|
|
|
|
|
|
// Update the gaps covered by IntI.
|
|
|
|
const float weight = IntI.value()->weight;
|
|
|
|
for (; Gap != NumGaps; ++Gap) {
|
|
|
|
GapWeight[Gap] = std::max(GapWeight[Gap], weight);
|
|
|
|
if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (Gap == NumGaps)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
|
|
|
|
/// basic block.
|
|
|
|
///
|
|
|
|
unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
|
|
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs) {
|
2011-04-06 03:57:00 +00:00
|
|
|
assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
|
|
|
|
const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
|
2011-02-17 19:13:53 +00:00
|
|
|
|
|
|
|
// Note that it is possible to have an interval that is live-in or live-out
|
|
|
|
// while only covering a single block - A phi-def can use undef values from
|
|
|
|
// predecessors, and the block could be a single-block loop.
|
|
|
|
// We don't bother doing anything clever about such a case, we simply assume
|
2011-08-02 22:54:14 +00:00
|
|
|
// that the interval is continuous from FirstInstr to LastInstr. We should
|
|
|
|
// make sure that we don't do anything illegal to such an interval, though.
|
2011-02-17 19:13:53 +00:00
|
|
|
|
|
|
|
const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
|
|
|
|
if (Uses.size() <= 2)
|
|
|
|
return 0;
|
|
|
|
const unsigned NumGaps = Uses.size()-1;
|
|
|
|
|
|
|
|
DEBUG({
|
|
|
|
dbgs() << "tryLocalSplit: ";
|
|
|
|
for (unsigned i = 0, e = Uses.size(); i != e; ++i)
|
|
|
|
dbgs() << ' ' << SA->UseSlots[i];
|
|
|
|
dbgs() << '\n';
|
|
|
|
});
|
|
|
|
|
2011-06-06 23:55:20 +00:00
|
|
|
// Since we allow local split results to be split again, there is a risk of
|
|
|
|
// creating infinite loops. It is tempting to require that the new live
|
|
|
|
// ranges have less instructions than the original. That would guarantee
|
|
|
|
// convergence, but it is too strict. A live range with 3 instructions can be
|
|
|
|
// split 2+3 (including the COPY), and we want to allow that.
|
|
|
|
//
|
|
|
|
// Instead we use these rules:
|
|
|
|
//
|
2011-07-25 15:25:43 +00:00
|
|
|
// 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
|
2011-06-06 23:55:20 +00:00
|
|
|
// noop split, of course).
|
2011-07-25 15:25:43 +00:00
|
|
|
// 2. Require progress be made for ranges with getStage() == RS_Split2. All
|
2011-06-06 23:55:20 +00:00
|
|
|
// the new ranges must have fewer instructions than before the split.
|
2011-07-25 15:25:43 +00:00
|
|
|
// 3. New ranges with the same number of instructions are marked RS_Split2,
|
2011-06-06 23:55:20 +00:00
|
|
|
// smaller ranges are marked RS_New.
|
|
|
|
//
|
|
|
|
// These rules allow a 3 -> 2+3 split once, which we need. They also prevent
|
|
|
|
// excessive splitting and infinite loops.
|
|
|
|
//
|
2011-07-25 15:25:43 +00:00
|
|
|
bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
|
2011-02-17 19:13:53 +00:00
|
|
|
|
2011-06-06 23:55:20 +00:00
|
|
|
// Best split candidate.
|
2011-02-17 19:13:53 +00:00
|
|
|
unsigned BestBefore = NumGaps;
|
|
|
|
unsigned BestAfter = 0;
|
|
|
|
float BestDiff = 0;
|
|
|
|
|
2011-03-04 00:58:40 +00:00
|
|
|
const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
|
2011-02-17 19:13:53 +00:00
|
|
|
SmallVector<float, 8> GapWeight;
|
|
|
|
|
|
|
|
Order.rewind();
|
|
|
|
while (unsigned PhysReg = Order.next()) {
|
|
|
|
// Keep track of the largest spill weight that would need to be evicted in
|
|
|
|
// order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
|
|
|
|
calcGapWeights(PhysReg, GapWeight);
|
|
|
|
|
|
|
|
// Try to find the best sequence of gaps to close.
|
|
|
|
// The new spill weight must be larger than any gap interference.
|
|
|
|
|
|
|
|
// We will split before Uses[SplitBefore] and after Uses[SplitAfter].
|
2011-06-06 23:55:20 +00:00
|
|
|
unsigned SplitBefore = 0, SplitAfter = 1;
|
2011-02-17 19:13:53 +00:00
|
|
|
|
|
|
|
// MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
|
|
|
|
// It is the spill weight that needs to be evicted.
|
|
|
|
float MaxGap = GapWeight[0];
|
|
|
|
|
|
|
|
for (;;) {
|
|
|
|
// Live before/after split?
|
|
|
|
const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
|
|
|
|
const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
|
|
|
|
|
|
|
|
DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
|
|
|
|
<< Uses[SplitBefore] << '-' << Uses[SplitAfter]
|
|
|
|
<< " i=" << MaxGap);
|
|
|
|
|
|
|
|
// Stop before the interval gets so big we wouldn't be making progress.
|
|
|
|
if (!LiveBefore && !LiveAfter) {
|
|
|
|
DEBUG(dbgs() << " all\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Should the interval be extended or shrunk?
|
|
|
|
bool Shrink = true;
|
|
|
|
|
2011-06-06 23:55:20 +00:00
|
|
|
// How many gaps would the new range have?
|
|
|
|
unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
|
|
|
|
|
|
|
|
// Legally, without causing looping?
|
|
|
|
bool Legal = !ProgressRequired || NewGaps < NumGaps;
|
|
|
|
|
|
|
|
if (Legal && MaxGap < HUGE_VALF) {
|
|
|
|
// Estimate the new spill weight. Each instruction reads or writes the
|
|
|
|
// register. Conservatively assume there are no read-modify-write
|
|
|
|
// instructions.
|
2011-02-17 19:13:53 +00:00
|
|
|
//
|
2011-06-06 23:55:20 +00:00
|
|
|
// Try to guess the size of the new interval.
|
|
|
|
const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
|
|
|
|
Uses[SplitBefore].distance(Uses[SplitAfter]) +
|
|
|
|
(LiveBefore + LiveAfter)*SlotIndex::InstrDist);
|
2011-02-17 19:13:53 +00:00
|
|
|
// Would this split be possible to allocate?
|
|
|
|
// Never allocate all gaps, we wouldn't be making progress.
|
2011-04-30 05:07:46 +00:00
|
|
|
DEBUG(dbgs() << " w=" << EstWeight);
|
|
|
|
if (EstWeight * Hysteresis >= MaxGap) {
|
2011-02-17 19:13:53 +00:00
|
|
|
Shrink = false;
|
2011-04-30 05:07:46 +00:00
|
|
|
float Diff = EstWeight - MaxGap;
|
2011-02-17 19:13:53 +00:00
|
|
|
if (Diff > BestDiff) {
|
|
|
|
DEBUG(dbgs() << " (best)");
|
2011-04-30 05:07:46 +00:00
|
|
|
BestDiff = Hysteresis * Diff;
|
2011-02-17 19:13:53 +00:00
|
|
|
BestBefore = SplitBefore;
|
|
|
|
BestAfter = SplitAfter;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Try to shrink.
|
|
|
|
if (Shrink) {
|
2011-06-06 23:55:20 +00:00
|
|
|
if (++SplitBefore < SplitAfter) {
|
2011-02-17 19:13:53 +00:00
|
|
|
DEBUG(dbgs() << " shrink\n");
|
|
|
|
// Recompute the max when necessary.
|
|
|
|
if (GapWeight[SplitBefore - 1] >= MaxGap) {
|
|
|
|
MaxGap = GapWeight[SplitBefore];
|
|
|
|
for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
|
|
|
|
MaxGap = std::max(MaxGap, GapWeight[i]);
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
MaxGap = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Try to extend the interval.
|
|
|
|
if (SplitAfter >= NumGaps) {
|
|
|
|
DEBUG(dbgs() << " end\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
DEBUG(dbgs() << " extend\n");
|
2011-06-06 23:55:20 +00:00
|
|
|
MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
|
2011-02-17 19:13:53 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Didn't find any candidates?
|
|
|
|
if (BestBefore == NumGaps)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
|
|
|
|
<< '-' << Uses[BestAfter] << ", " << BestDiff
|
|
|
|
<< ", " << (BestAfter - BestBefore + 1) << " instrs\n");
|
|
|
|
|
2011-03-09 00:57:29 +00:00
|
|
|
LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
|
2011-03-03 01:29:13 +00:00
|
|
|
SE->reset(LREdit);
|
|
|
|
|
|
|
|
SE->openIntv();
|
|
|
|
SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
|
|
|
|
SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
|
|
|
|
SE->useIntv(SegStart, SegStop);
|
2011-06-06 23:55:20 +00:00
|
|
|
SmallVector<unsigned, 8> IntvMap;
|
|
|
|
SE->finish(&IntvMap);
|
2011-05-06 18:00:02 +00:00
|
|
|
DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
|
2011-06-06 23:55:20 +00:00
|
|
|
|
|
|
|
// If the new range has the same number of instructions as before, mark it as
|
2011-07-25 15:25:43 +00:00
|
|
|
// RS_Split2 so the next split will be forced to make progress. Otherwise,
|
2011-06-06 23:55:20 +00:00
|
|
|
// leave the new intervals as RS_New so they can compete.
|
|
|
|
bool LiveBefore = BestBefore != 0 || BI.LiveIn;
|
|
|
|
bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
|
|
|
|
unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
|
|
|
|
if (NewGaps >= NumGaps) {
|
|
|
|
DEBUG(dbgs() << "Tagging non-progress ranges: ");
|
|
|
|
assert(!ProgressRequired && "Didn't make progress when it was required.");
|
|
|
|
for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
|
|
|
|
if (IntvMap[i] == 1) {
|
2011-07-25 15:25:43 +00:00
|
|
|
setStage(*LREdit.get(i), RS_Split2);
|
2011-06-06 23:55:20 +00:00
|
|
|
DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg));
|
|
|
|
}
|
|
|
|
DEBUG(dbgs() << '\n');
|
|
|
|
}
|
2011-02-17 22:53:48 +00:00
|
|
|
++NumLocalSplits;
|
2011-02-17 19:13:53 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-19 22:11:48 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Live Range Splitting
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// trySplit - Try to split VirtReg or one of its interferences, making it
|
|
|
|
/// assignable.
|
|
|
|
/// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
|
|
|
|
unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
|
|
|
|
SmallVectorImpl<LiveInterval*>&NewVRegs) {
|
2011-02-17 19:13:53 +00:00
|
|
|
// Local intervals are handled separately.
|
2011-02-19 00:38:40 +00:00
|
|
|
if (LIS->intervalIsInOneMBB(VirtReg)) {
|
|
|
|
NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
|
2011-03-01 21:10:07 +00:00
|
|
|
SA->analyze(&VirtReg);
|
2011-02-17 19:13:53 +00:00
|
|
|
return tryLocalSplit(VirtReg, Order, NewVRegs);
|
2011-02-19 00:38:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
|
2011-01-19 22:11:48 +00:00
|
|
|
|
2011-07-25 15:25:43 +00:00
|
|
|
// Ranges must be Split2 or less.
|
2011-07-25 15:25:41 +00:00
|
|
|
if (getStage(VirtReg) >= RS_Spill)
|
2011-03-01 21:10:07 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
SA->analyze(&VirtReg);
|
|
|
|
|
2011-05-03 20:42:13 +00:00
|
|
|
// FIXME: SplitAnalysis may repair broken live ranges coming from the
|
|
|
|
// coalescer. That may cause the range to become allocatable which means that
|
|
|
|
// tryRegionSplit won't be making progress. This check should be replaced with
|
|
|
|
// an assertion when the coalescer is fixed.
|
|
|
|
if (SA->didRepairRange()) {
|
|
|
|
// VirtReg has changed, so all cached queries are invalid.
|
2011-05-10 17:37:41 +00:00
|
|
|
invalidateVirtRegs();
|
2011-05-03 20:42:13 +00:00
|
|
|
if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
|
|
|
|
return PhysReg;
|
|
|
|
}
|
|
|
|
|
2011-07-25 15:25:43 +00:00
|
|
|
// First try to split around a region spanning multiple blocks. RS_Split2
|
|
|
|
// ranges already made dubious progress with region splitting, so they go
|
|
|
|
// straight to single block splitting.
|
|
|
|
if (getStage(VirtReg) < RS_Split2) {
|
|
|
|
unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
|
|
|
|
if (PhysReg || !NewVRegs.empty())
|
|
|
|
return PhysReg;
|
|
|
|
}
|
2011-01-19 22:11:48 +00:00
|
|
|
|
|
|
|
// Then isolate blocks with multiple uses.
|
2011-04-12 19:32:53 +00:00
|
|
|
SplitAnalysis::BlockPtrSet Blocks;
|
|
|
|
if (SA->getMultiUseBlocks(Blocks)) {
|
|
|
|
LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
|
|
|
|
SE->reset(LREdit);
|
|
|
|
SE->splitSingleBlocks(Blocks);
|
2011-07-25 15:25:41 +00:00
|
|
|
setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill);
|
2011-04-12 19:32:53 +00:00
|
|
|
if (VerifyEnabled)
|
|
|
|
MF->verify(this, "After splitting live range around basic blocks");
|
2011-01-19 22:11:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Don't assign any physregs.
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-12-22 22:01:30 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Main Entry Point
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
|
2011-01-19 22:11:48 +00:00
|
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs) {
|
2010-12-22 22:01:30 +00:00
|
|
|
// First try assigning a free register.
|
2011-06-03 20:34:53 +00:00
|
|
|
AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
|
2011-04-20 18:19:48 +00:00
|
|
|
if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
|
|
|
|
return PhysReg;
|
2010-12-09 18:15:21 +00:00
|
|
|
|
2011-05-25 23:58:36 +00:00
|
|
|
LiveRangeStage Stage = getStage(VirtReg);
|
2011-07-02 01:37:09 +00:00
|
|
|
DEBUG(dbgs() << StageName[Stage]
|
|
|
|
<< " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
|
2011-05-25 23:58:36 +00:00
|
|
|
|
2011-06-01 18:45:02 +00:00
|
|
|
// Try to evict a less worthy live range, but only for ranges from the primary
|
2011-07-25 15:25:41 +00:00
|
|
|
// queue. The RS_Split ranges already failed to do this, and they should not
|
2011-06-01 18:45:02 +00:00
|
|
|
// get a second chance until they have been split.
|
2011-07-25 15:25:41 +00:00
|
|
|
if (Stage != RS_Split)
|
2011-06-01 18:45:02 +00:00
|
|
|
if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
|
|
|
|
return PhysReg;
|
2010-12-09 18:15:21 +00:00
|
|
|
|
2011-01-19 22:11:48 +00:00
|
|
|
assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
|
|
|
|
|
2011-02-24 23:21:36 +00:00
|
|
|
// The first time we see a live range, don't try to split or spill.
|
|
|
|
// Wait until the second time, when all smaller ranges have been allocated.
|
|
|
|
// This gives a better picture of the interference to split around.
|
2011-07-25 15:25:41 +00:00
|
|
|
if (Stage < RS_Split) {
|
|
|
|
setStage(VirtReg, RS_Split);
|
2011-03-19 23:02:47 +00:00
|
|
|
DEBUG(dbgs() << "wait for second round\n");
|
2011-02-24 23:21:36 +00:00
|
|
|
NewVRegs.push_back(&VirtReg);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-05-06 21:58:30 +00:00
|
|
|
// If we couldn't allocate a register from spilling, there is probably some
|
|
|
|
// invalid inline assembly. The base class wil report it.
|
2011-07-25 15:25:41 +00:00
|
|
|
if (Stage >= RS_Done || !VirtReg.isSpillable())
|
2011-05-06 21:58:30 +00:00
|
|
|
return ~0u;
|
2011-03-01 21:10:07 +00:00
|
|
|
|
2010-12-14 00:37:49 +00:00
|
|
|
// Try splitting VirtReg or interferences.
|
2011-01-19 22:11:48 +00:00
|
|
|
unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
|
|
|
|
if (PhysReg || !NewVRegs.empty())
|
2010-12-14 00:37:44 +00:00
|
|
|
return PhysReg;
|
|
|
|
|
2010-12-22 22:01:30 +00:00
|
|
|
// Finally spill VirtReg itself.
|
|
|
|
NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
|
2011-03-10 01:51:42 +00:00
|
|
|
LiveRangeEdit LRE(VirtReg, NewVRegs, this);
|
|
|
|
spiller().spill(LRE);
|
2011-07-25 15:25:41 +00:00
|
|
|
setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
|
2010-12-08 03:26:16 +00:00
|
|
|
|
2011-03-16 22:56:08 +00:00
|
|
|
if (VerifyEnabled)
|
|
|
|
MF->verify(this, "After spilling");
|
|
|
|
|
2010-12-08 03:26:16 +00:00
|
|
|
// The live virtual register requesting allocation was spilled, so tell
|
|
|
|
// the caller not to allocate anything during this round.
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
|
|
|
|
DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
|
|
|
|
<< "********** Function: "
|
|
|
|
<< ((Value*)mf.getFunction())->getName() << '\n');
|
|
|
|
|
|
|
|
MF = &mf;
|
2010-12-17 23:16:35 +00:00
|
|
|
if (VerifyEnabled)
|
2010-12-18 00:06:56 +00:00
|
|
|
MF->verify(this, "Before greedy register allocator");
|
2010-12-17 23:16:35 +00:00
|
|
|
|
2010-12-10 23:49:00 +00:00
|
|
|
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
|
2011-01-18 21:13:27 +00:00
|
|
|
Indexes = &getAnalysis<SlotIndexes>();
|
2010-12-17 23:16:32 +00:00
|
|
|
DomTree = &getAnalysis<MachineDominatorTree>();
|
2010-12-10 22:54:44 +00:00
|
|
|
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
|
2010-12-15 23:46:13 +00:00
|
|
|
Loops = &getAnalysis<MachineLoopInfo>();
|
2011-01-18 21:13:27 +00:00
|
|
|
Bundles = &getAnalysis<EdgeBundles>();
|
|
|
|
SpillPlacer = &getAnalysis<SpillPlacement>();
|
2011-05-06 18:00:02 +00:00
|
|
|
DebugVars = &getAnalysis<LiveDebugVariables>();
|
2011-01-18 21:13:27 +00:00
|
|
|
|
2011-02-19 00:53:42 +00:00
|
|
|
SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
|
2011-03-03 01:29:13 +00:00
|
|
|
SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
|
2011-07-02 01:37:09 +00:00
|
|
|
ExtraRegInfo.clear();
|
|
|
|
ExtraRegInfo.resize(MRI->getNumVirtRegs());
|
|
|
|
NextCascade = 1;
|
2011-04-02 06:03:38 +00:00
|
|
|
IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI);
|
2011-07-26 23:41:46 +00:00
|
|
|
GlobalCand.resize(32); // This will grow as needed.
|
2010-12-15 23:46:13 +00:00
|
|
|
|
2010-12-08 03:26:16 +00:00
|
|
|
allocatePhysRegs();
|
|
|
|
addMBBLiveIns(MF);
|
2011-02-08 21:13:03 +00:00
|
|
|
LIS->addKillFlags();
|
2010-12-08 03:26:16 +00:00
|
|
|
|
|
|
|
// Run rewriter
|
2010-12-11 00:19:56 +00:00
|
|
|
{
|
|
|
|
NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
|
2011-02-18 22:03:18 +00:00
|
|
|
VRM->rewrite(Indexes);
|
2010-12-11 00:19:56 +00:00
|
|
|
}
|
2010-12-08 03:26:16 +00:00
|
|
|
|
2011-04-05 21:40:37 +00:00
|
|
|
// Write out new DBG_VALUE instructions.
|
2011-07-31 03:53:42 +00:00
|
|
|
{
|
|
|
|
NamedRegionTimer T("Emit Debug Info", TimerGroupName, TimePassesIsEnabled);
|
|
|
|
DebugVars->emitDebugValues(VRM);
|
|
|
|
}
|
2011-04-05 21:40:37 +00:00
|
|
|
|
2010-12-08 03:26:16 +00:00
|
|
|
// The pass output is in VirtRegMap. Release all the transient data.
|
|
|
|
releaseMemory();
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|