2012-02-18 12:03:15 +00:00
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//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
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2011-04-14 14:33:36 +00:00
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//
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2003-10-21 15:17:13 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2011-04-14 14:33:36 +00:00
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//
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2003-10-21 15:17:13 +00:00
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//===----------------------------------------------------------------------===//
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2003-08-03 15:47:49 +00:00
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//
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2011-10-11 06:44:02 +00:00
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// This is a target description file for the Intel i386 architecture, referred
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// to here as the "X86" architecture.
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2003-08-03 15:47:49 +00:00
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//
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//===----------------------------------------------------------------------===//
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2003-08-04 04:59:56 +00:00
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// Get the target-independent interfaces which we are implementing...
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2003-08-03 15:47:49 +00:00
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//
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2008-11-24 07:34:46 +00:00
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include "llvm/Target/Target.td"
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2003-08-03 15:47:49 +00:00
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2011-07-07 21:06:52 +00:00
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//===----------------------------------------------------------------------===//
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2012-08-16 03:50:04 +00:00
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// X86 Subtarget state
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2011-07-07 21:06:52 +00:00
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//
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def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
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"64-bit mode (x86_64)">;
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2006-10-06 09:17:41 +00:00
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//===----------------------------------------------------------------------===//
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2012-08-16 03:50:04 +00:00
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// X86 Subtarget features
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2007-05-04 20:38:40 +00:00
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//===----------------------------------------------------------------------===//
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2009-09-02 05:53:04 +00:00
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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2010-12-04 20:32:23 +00:00
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def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
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"Support POPCNT instruction">;
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2010-01-11 16:29:42 +00:00
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2007-05-04 20:38:40 +00:00
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def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
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"Enable MMX instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions",
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2009-09-02 05:53:04 +00:00
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// SSE codegen depends on cmovs, and all
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2011-04-14 14:33:36 +00:00
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// SSE1+ processors support them.
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2009-09-02 05:53:04 +00:00
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[FeatureMMX, FeatureCMOV]>;
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2007-05-04 20:38:40 +00:00
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions",
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[FeatureSSE1]>;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions",
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[FeatureSSE2]>;
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def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
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"Enable SSSE3 instructions",
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[FeatureSSE3]>;
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2008-02-03 07:18:54 +00:00
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def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
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"Enable SSE 4.1 instructions",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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2011-12-29 15:51:45 +00:00
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[FeatureSSE41]>;
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2007-05-04 20:38:40 +00:00
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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2011-04-15 00:32:41 +00:00
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"Enable 3DNow! instructions",
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[FeatureMMX]>;
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2007-05-04 20:38:40 +00:00
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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2007-05-06 07:56:19 +00:00
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"Enable 3DNow! Athlon instructions",
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[Feature3DNow]>;
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2009-02-03 00:04:43 +00:00
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// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
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// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
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// without disabling 64-bit mode.
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2007-05-06 07:56:19 +00:00
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def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
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2010-03-14 22:24:34 +00:00
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"Support 64-bit instructions",
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[FeatureCMOV]>;
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2011-08-26 21:21:21 +00:00
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def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
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"64-bit with cmpxchg16b",
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[Feature64Bit]>;
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2009-01-02 05:35:45 +00:00
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def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
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"Bit testing of memory is slow">;
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2010-04-01 05:58:17 +00:00
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def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
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"IsUAMemFast", "true",
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"Fast unaligned memory access">;
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2009-05-26 21:04:35 +00:00
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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2011-12-30 07:16:00 +00:00
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"Support SSE 4a instructions",
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[FeatureSSE3]>;
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2006-10-06 09:17:41 +00:00
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2012-01-09 09:02:13 +00:00
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def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
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"Enable AVX instructions",
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[FeatureSSE42]>;
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def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
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2011-10-30 19:57:21 +00:00
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"Enable AVX2 instructions",
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[FeatureAVX]>;
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2012-05-31 14:34:17 +00:00
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def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
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"Enable packed carry-less multiplication instructions",
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2012-05-01 05:28:32 +00:00
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[FeatureSSE2]>;
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2012-06-03 18:58:46 +00:00
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def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
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2011-12-29 19:46:19 +00:00
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"Enable three-operand fused multiple-add",
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[FeatureAVX]>;
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2009-06-26 22:46:54 +00:00
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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2011-12-30 07:16:00 +00:00
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"Enable four-operand fused multiple-add",
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2012-05-01 06:54:48 +00:00
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[FeatureAVX, FeatureSSE4A]>;
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2011-12-30 07:16:00 +00:00
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def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
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2012-05-01 05:41:41 +00:00
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"Enable XOP instructions",
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2012-08-16 04:04:02 +00:00
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[FeatureFMA4]>;
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2010-01-11 16:29:42 +00:00
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def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
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"HasVectorUAMem", "true",
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"Allow unaligned memory operands on vector/SIMD instructions">;
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2010-04-02 21:54:27 +00:00
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def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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2012-05-01 05:28:32 +00:00
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"Enable AES instructions",
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[FeatureSSE2]>;
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2011-10-03 17:28:23 +00:00
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def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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2011-10-09 07:31:39 +00:00
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions">;
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2011-10-30 19:57:21 +00:00
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def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
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"Support FS/GS Base instructions">;
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2011-10-11 06:44:02 +00:00
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def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
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"Support LZCNT instruction">;
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2011-10-14 03:21:46 +00:00
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def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
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"Support BMI instructions">;
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2011-10-16 07:55:05 +00:00
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def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
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"Support BMI2 instructions">;
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2012-11-08 07:28:54 +00:00
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def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
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"Support RTM instructions">;
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2013-03-26 22:46:02 +00:00
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def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
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"Support HLE">;
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2013-02-14 19:08:21 +00:00
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def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
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"Support ADX instructions">;
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2013-03-26 17:47:11 +00:00
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def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
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"Support PRFCHW instructions">;
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2013-03-28 23:41:26 +00:00
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def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
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"Support RDSEED instruction">;
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2012-02-07 22:50:41 +00:00
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def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
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"Use LEA for adjusting the stack pointer">;
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2012-09-04 18:22:17 +00:00
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def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
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2013-01-08 18:27:24 +00:00
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"HasSlowDivide", "true",
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"Use small divide for positive values less than 256">;
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def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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2013-03-27 19:14:02 +00:00
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def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
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"CallRegIndirect", "true",
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"Call register indirect">;
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2009-06-26 22:46:54 +00:00
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2006-10-06 09:17:41 +00:00
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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2012-02-01 23:20:51 +00:00
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include "X86Schedule.td"
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def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
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"Intel Atom processors">;
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2006-10-06 09:17:41 +00:00
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class Proc<string Name, list<SubtargetFeature> Features>
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2012-07-07 04:00:00 +00:00
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: ProcessorModel<Name, GenericModel, Features>;
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2012-02-01 23:20:51 +00:00
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2006-10-06 09:17:41 +00:00
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def : Proc<"generic", []>;
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def : Proc<"i386", []>;
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def : Proc<"i486", []>;
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2008-10-14 22:06:33 +00:00
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def : Proc<"i586", []>;
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2006-10-06 09:17:41 +00:00
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def : Proc<"pentium", []>;
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def : Proc<"pentium-mmx", [FeatureMMX]>;
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def : Proc<"i686", []>;
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2009-09-02 05:53:04 +00:00
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def : Proc<"pentiumpro", [FeatureCMOV]>;
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def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
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2007-05-22 05:15:37 +00:00
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def : Proc<"pentium3", [FeatureSSE1]>;
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2011-05-03 03:42:50 +00:00
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def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
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2009-01-02 05:35:45 +00:00
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def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
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2007-05-22 05:15:37 +00:00
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def : Proc<"pentium4", [FeatureSSE2]>;
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2011-05-03 03:42:50 +00:00
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def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
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2012-12-15 09:01:13 +00:00
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def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
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FeatureFastUAMem]>;
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2013-03-26 22:19:12 +00:00
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// Intel Core Duo.
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def : ProcessorModel<"yonah", SandyBridgeModel,
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[FeatureSSE3, FeatureSlowBTMem]>;
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// NetBurst.
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def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
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def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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// Intel Core 2 Solo/Duo.
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def : ProcessorModel<"core2", SandyBridgeModel,
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[FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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def : ProcessorModel<"penryn", SandyBridgeModel,
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[FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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// Atom.
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def : ProcessorModel<"atom", AtomModel,
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[ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
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FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
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2013-03-27 19:14:02 +00:00
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FeatureSlowDivide,
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FeatureCallRegIndirect,
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FeaturePadShortFunctions]>;
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2013-03-26 22:19:12 +00:00
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2010-04-02 21:54:27 +00:00
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// "Arrandale" along with corei3 and corei5
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2013-03-26 22:19:12 +00:00
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def : ProcessorModel<"corei7", SandyBridgeModel,
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[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
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FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
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def : ProcessorModel<"nehalem", SandyBridgeModel,
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[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
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FeatureFastUAMem, FeaturePOPCNT]>;
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2010-04-02 21:54:27 +00:00
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// Westmere is a similar machine to nehalem with some additional features.
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// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
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2013-03-26 22:19:12 +00:00
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def : ProcessorModel<"westmere", SandyBridgeModel,
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[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
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FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
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FeaturePCLMUL]>;
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2011-10-10 19:35:07 +00:00
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// Sandy Bridge
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2010-12-10 00:26:57 +00:00
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// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
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// rather than a superset.
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2013-03-26 22:19:12 +00:00
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def : ProcessorModel<"corei7-avx", SandyBridgeModel,
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[FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
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2011-10-10 19:35:07 +00:00
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// Ivy Bridge
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2013-03-26 22:19:12 +00:00
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def : ProcessorModel<"core-avx-i", SandyBridgeModel,
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[FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
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FeatureF16C, FeatureFSGSBase]>;
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2006-10-06 09:17:41 +00:00
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2011-10-14 03:21:46 +00:00
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// Haswell
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2013-03-28 22:34:46 +00:00
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def : ProcessorModel<"core-avx2", HaswellModel,
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2013-03-26 22:19:12 +00:00
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[FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
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FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
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2013-03-26 22:46:02 +00:00
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FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
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FeatureHLE]>;
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2011-10-14 03:21:46 +00:00
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2006-10-06 09:17:41 +00:00
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def : Proc<"k6", [FeatureMMX]>;
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2011-04-15 00:32:41 +00:00
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def : Proc<"k6-2", [Feature3DNow]>;
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def : Proc<"k6-3", [Feature3DNow]>;
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def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
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2009-01-02 05:35:45 +00:00
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def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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2009-02-03 00:04:43 +00:00
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def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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2011-08-26 21:21:21 +00:00
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def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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2009-05-26 21:04:35 +00:00
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FeatureSlowBTMem]>;
|
2011-08-26 21:21:21 +00:00
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def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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2009-05-26 21:04:35 +00:00
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FeatureSlowBTMem]>;
|
2011-08-26 21:21:21 +00:00
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def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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2009-05-26 21:04:35 +00:00
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FeatureSlowBTMem]>;
|
2012-05-01 06:54:48 +00:00
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def : Proc<"amdfam10", [FeatureSSE4A,
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2011-11-30 15:48:16 +00:00
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Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
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2011-12-29 18:47:31 +00:00
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FeaturePOPCNT, FeatureSlowBTMem]>;
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2012-01-10 11:50:02 +00:00
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// Bobcat
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def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
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FeatureLZCNT, FeaturePOPCNT]>;
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// Bulldozer
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2012-05-01 06:54:48 +00:00
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def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
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2012-05-31 14:34:17 +00:00
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FeatureAES, FeaturePCLMUL,
|
2012-05-01 06:54:48 +00:00
|
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FeatureLZCNT, FeaturePOPCNT]>;
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2012-01-10 11:50:02 +00:00
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// Enhanced Bulldozer
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2012-05-01 06:54:48 +00:00
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def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
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2012-05-31 14:34:17 +00:00
|
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FeatureAES, FeaturePCLMUL,
|
2012-05-01 06:54:48 +00:00
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FeatureF16C, FeatureLZCNT,
|
2012-08-16 04:04:02 +00:00
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FeaturePOPCNT, FeatureBMI, FeatureFMA]>;
|
2012-09-12 14:36:02 +00:00
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def : Proc<"geode", [Feature3DNowA]>;
|
2006-10-06 09:17:41 +00:00
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def : Proc<"winchip-c6", [FeatureMMX]>;
|
2011-04-15 00:32:41 +00:00
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|
def : Proc<"winchip2", [Feature3DNow]>;
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def : Proc<"c3", [Feature3DNow]>;
|
2007-05-22 05:15:37 +00:00
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|
def : Proc<"c3-2", [FeatureSSE1]>;
|
2006-10-06 09:17:41 +00:00
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|
2003-08-03 15:47:49 +00:00
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|
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//===----------------------------------------------------------------------===//
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// Register File Description
|
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//===----------------------------------------------------------------------===//
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include "X86RegisterInfo.td"
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|
2003-08-03 18:19:37 +00:00
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//===----------------------------------------------------------------------===//
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|
|
// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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|
2003-08-03 21:54:21 +00:00
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|
|
include "X86InstrInfo.td"
|
|
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|
|
2010-04-05 03:10:20 +00:00
|
|
|
def X86InstrInfo : InstrInfo;
|
2003-08-03 18:19:37 +00:00
|
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|
|
2007-02-26 18:17:14 +00:00
|
|
|
//===----------------------------------------------------------------------===//
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|
|
// Calling Conventions
|
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|
//===----------------------------------------------------------------------===//
|
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|
|
include "X86CallingConv.td"
|
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|
//===----------------------------------------------------------------------===//
|
2010-10-30 13:48:28 +00:00
|
|
|
// Assembly Parser
|
2007-02-26 18:17:14 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2009-07-29 00:02:19 +00:00
|
|
|
def ATTAsmParser : AsmParser {
|
2012-01-12 18:03:40 +00:00
|
|
|
string AsmParserClassName = "AsmParser";
|
2012-01-09 19:13:28 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
def ATTAsmParserVariant : AsmParserVariant {
|
2009-07-29 00:02:19 +00:00
|
|
|
int Variant = 0;
|
2009-08-11 20:59:47 +00:00
|
|
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|
|
// Discard comments in assembly strings.
|
|
|
|
string CommentDelimiter = "#";
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|
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|
|
// Recognize hard coded registers.
|
|
|
|
string RegisterPrefix = "%";
|
2009-07-29 00:02:19 +00:00
|
|
|
}
|
|
|
|
|
2012-01-10 17:51:54 +00:00
|
|
|
def IntelAsmParserVariant : AsmParserVariant {
|
|
|
|
int Variant = 1;
|
|
|
|
|
|
|
|
// Discard comments in assembly strings.
|
|
|
|
string CommentDelimiter = ";";
|
|
|
|
|
|
|
|
// Recognize hard coded registers.
|
|
|
|
string RegisterPrefix = "";
|
|
|
|
}
|
|
|
|
|
2010-10-30 13:48:28 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Assembly Printers
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2004-10-03 20:36:57 +00:00
|
|
|
// The X86 target supports two different syntaxes for emitting machine code.
|
|
|
|
// This is controlled by the -x86-asm-syntax={att|intel}
|
|
|
|
def ATTAsmWriter : AsmWriter {
|
2009-09-13 19:30:11 +00:00
|
|
|
string AsmWriterClassName = "ATTInstPrinter";
|
2004-10-03 20:36:57 +00:00
|
|
|
int Variant = 0;
|
2010-09-30 23:40:25 +00:00
|
|
|
bit isMCAsmWriter = 1;
|
2004-10-03 20:36:57 +00:00
|
|
|
}
|
|
|
|
def IntelAsmWriter : AsmWriter {
|
2009-09-20 07:47:59 +00:00
|
|
|
string AsmWriterClassName = "IntelInstPrinter";
|
2004-10-03 20:36:57 +00:00
|
|
|
int Variant = 1;
|
2010-09-30 23:40:25 +00:00
|
|
|
bit isMCAsmWriter = 1;
|
2004-10-03 20:36:57 +00:00
|
|
|
}
|
|
|
|
|
2003-08-03 18:19:37 +00:00
|
|
|
def X86 : Target {
|
|
|
|
// Information about the instructions...
|
2003-08-04 04:59:56 +00:00
|
|
|
let InstructionSet = X86InstrInfo;
|
2009-07-29 00:02:19 +00:00
|
|
|
let AssemblyParsers = [ATTAsmParser];
|
2012-01-10 17:51:54 +00:00
|
|
|
let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
|
2004-10-03 20:36:57 +00:00
|
|
|
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
|
2003-08-03 18:19:37 +00:00
|
|
|
}
|