2004-07-23 17:56:30 +00:00
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//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
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2003-11-20 03:32:25 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2003-11-20 03:32:25 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass which is used
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// by the Linear Scan Register allocator. This pass linearizes the
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// basic blocks of the function in DFS order and uses the
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// LiveVariables pass to conservatively compute live intervals for
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// each virtual and physical register.
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//
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//===----------------------------------------------------------------------===//
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2012-01-07 07:39:47 +00:00
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#define DEBUG_TYPE "regalloc"
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2005-09-21 04:19:09 +00:00
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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2004-05-01 21:24:39 +00:00
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#include "llvm/Value.h"
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2008-07-25 00:02:30 +00:00
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#include "llvm/Analysis/AliasAnalysis.h"
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2003-11-20 03:32:25 +00:00
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2003-11-20 03:32:25 +00:00
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#include "llvm/CodeGen/Passes.h"
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2008-02-10 18:45:23 +00:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2003-11-20 03:32:25 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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2004-09-01 22:55:40 +00:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2009-07-11 13:10:19 +00:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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2012-02-13 20:44:42 +00:00
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#include "llvm/ADT/DenseSet.h"
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2004-09-01 22:55:40 +00:00
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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2004-09-03 18:19:51 +00:00
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#include <algorithm>
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2009-06-02 16:53:25 +00:00
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#include <limits>
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2006-12-02 02:22:01 +00:00
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#include <cmath>
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2003-11-20 03:32:25 +00:00
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using namespace llvm;
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2008-05-13 00:00:25 +00:00
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// Hidden options for help debugging.
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2010-08-12 20:01:23 +00:00
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static cl::opt<bool> DisableReMat("disable-rematerialization",
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2008-05-13 00:00:25 +00:00
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cl::init(false), cl::Hidden);
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2009-09-14 21:33:42 +00:00
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STATISTIC(numIntervals , "Number of original intervals");
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2006-12-19 22:41:21 +00:00
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2007-05-03 01:11:54 +00:00
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char LiveIntervals::ID = 0;
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2010-10-12 19:48:12 +00:00
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INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
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"Live Interval Analysis", false, false)
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2012-02-10 04:10:36 +00:00
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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2010-10-12 19:48:12 +00:00
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INITIALIZE_PASS_DEPENDENCY(LiveVariables)
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2012-02-10 04:10:36 +00:00
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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2010-10-12 19:48:12 +00:00
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
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2010-10-07 22:25:06 +00:00
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"Live Interval Analysis", false, false)
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2003-11-20 03:32:25 +00:00
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2006-08-24 22:43:55 +00:00
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void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
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2009-07-31 23:37:33 +00:00
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AU.setPreservesCFG();
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2008-07-25 00:02:30 +00:00
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<AliasAnalysis>();
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2004-08-04 09:46:26 +00:00
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AU.addRequired<LiveVariables>();
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2010-08-17 21:00:37 +00:00
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AU.addPreserved<LiveVariables>();
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2012-02-13 20:44:42 +00:00
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AU.addPreservedID(MachineLoopInfoID);
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2008-01-04 20:54:55 +00:00
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AU.addPreservedID(MachineDominatorsID);
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2009-11-03 23:52:08 +00:00
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AU.addPreserved<SlotIndexes>();
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AU.addRequiredTransitive<SlotIndexes>();
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2004-08-04 09:46:26 +00:00
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MachineFunctionPass::getAnalysisUsage(AU);
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2003-11-20 03:32:25 +00:00
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}
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2006-08-24 22:43:55 +00:00
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void LiveIntervals::releaseMemory() {
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2008-08-13 21:49:13 +00:00
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// Free the live intervals themselves.
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2008-08-13 22:08:30 +00:00
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for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
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2010-03-24 20:25:25 +00:00
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E = r2iMap_.end(); I != E; ++I)
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2008-08-13 21:49:13 +00:00
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delete I->second;
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2010-08-12 20:01:23 +00:00
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2004-08-04 09:46:26 +00:00
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r2iMap_.clear();
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2012-02-08 17:33:45 +00:00
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RegMaskSlots.clear();
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RegMaskBits.clear();
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2012-02-10 01:26:29 +00:00
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RegMaskBlocks.clear();
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2009-07-09 03:57:02 +00:00
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2010-06-26 11:30:59 +00:00
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// Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
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VNInfoAllocator.Reset();
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2006-05-11 07:29:24 +00:00
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}
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2008-05-28 20:54:50 +00:00
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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mri_ = &mf_->getRegInfo();
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tm_ = &fn.getTarget();
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tri_ = tm_->getRegisterInfo();
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tii_ = tm_->getInstrInfo();
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2008-07-25 00:02:30 +00:00
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aa_ = &getAnalysis<AliasAnalysis>();
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2008-05-28 20:54:50 +00:00
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lv_ = &getAnalysis<LiveVariables>();
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2009-11-03 23:52:08 +00:00
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indexes_ = &getAnalysis<SlotIndexes>();
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2008-05-28 20:54:50 +00:00
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allocatableRegs_ = tri_->getAllocatableSet(fn);
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2012-02-14 18:51:53 +00:00
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reservedRegs_ = tri_->getReservedRegs(fn);
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2003-11-20 03:32:25 +00:00
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2004-08-04 09:46:26 +00:00
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computeIntervals();
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2003-11-20 03:32:25 +00:00
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2004-08-04 09:46:26 +00:00
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numIntervals += getNumIntervals();
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2004-02-15 10:24:21 +00:00
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2004-09-30 15:59:17 +00:00
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DEBUG(dump());
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2004-08-04 09:46:26 +00:00
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return true;
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2003-11-20 03:32:25 +00:00
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}
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2004-09-30 15:59:17 +00:00
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/// print - Implement the dump method.
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2009-08-23 06:03:38 +00:00
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void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
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2009-08-23 03:41:05 +00:00
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OS << "********** INTERVALS **********\n";
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2005-07-27 23:03:38 +00:00
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for (const_iterator I = begin(), E = end(); I != E; ++I) {
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2009-08-23 03:41:05 +00:00
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I->second->print(OS, tri_);
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OS << "\n";
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2005-07-27 23:03:38 +00:00
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}
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2004-09-30 15:59:17 +00:00
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2009-09-14 21:33:42 +00:00
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printInstrs(OS);
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}
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void LiveIntervals::printInstrs(raw_ostream &OS) const {
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2009-08-23 03:41:05 +00:00
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OS << "********** MACHINEINSTRS **********\n";
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2010-10-26 20:21:46 +00:00
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mf_->print(OS, indexes_);
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2004-09-30 15:59:17 +00:00
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}
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2009-09-14 21:33:42 +00:00
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void LiveIntervals::dumpInstrs() const {
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2010-01-04 22:49:02 +00:00
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printInstrs(dbgs());
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2009-09-14 21:33:42 +00:00
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}
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2010-05-04 20:26:52 +00:00
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static
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2010-05-05 18:27:40 +00:00
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bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
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2010-05-04 20:26:52 +00:00
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unsigned Reg = MI.getOperand(MOIdx).getReg();
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for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg())
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continue;
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if (MO.getReg() == Reg && MO.isDef()) {
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assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
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MI.getOperand(MOIdx).getSubReg() &&
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2010-07-06 23:26:25 +00:00
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(MO.getSubReg() || MO.isImplicit()));
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2010-05-04 20:26:52 +00:00
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return true;
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}
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}
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return false;
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}
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2010-05-05 18:27:40 +00:00
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/// isPartialRedef - Return true if the specified def at the specific index is
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/// partially re-defining the specified live interval. A common case of this is
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2010-08-12 20:01:23 +00:00
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/// a definition of the sub-register.
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2010-05-05 18:27:40 +00:00
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bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
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LiveInterval &interval) {
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if (!MO.getSubReg() || MO.isEarlyClobber())
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return false;
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2011-11-13 20:45:27 +00:00
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SlotIndex RedefIndex = MIIdx.getRegSlot();
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2010-05-05 18:27:40 +00:00
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const LiveRange *OldLR =
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2011-11-13 20:45:27 +00:00
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interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
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2010-09-25 12:04:16 +00:00
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MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
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if (DefMI != 0) {
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2010-05-05 18:27:40 +00:00
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return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
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}
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return false;
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}
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2006-08-22 18:19:46 +00:00
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void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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2003-11-20 03:32:25 +00:00
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MachineBasicBlock::iterator mi,
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2009-11-03 23:52:08 +00:00
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SlotIndex MIIdx,
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2009-09-04 20:41:11 +00:00
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MachineOperand& MO,
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2008-07-10 07:35:43 +00:00
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unsigned MOIdx,
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2006-08-22 18:19:46 +00:00
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LiveInterval &interval) {
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2011-01-09 03:05:53 +00:00
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DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
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2008-04-03 16:39:43 +00:00
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2004-08-04 09:46:56 +00:00
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// Virtual registers may be defined multiple times (due to phi
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// elimination and 2-addr elimination). Much of what we do only has to be
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// done once for the vreg. We use an empty interval to detect the first
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2004-08-04 09:46:26 +00:00
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// time we see a vreg.
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2009-07-17 19:43:40 +00:00
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LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
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2004-08-04 09:46:26 +00:00
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if (interval.empty()) {
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// Get the Idx of the defining instructions.
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2011-11-13 22:05:42 +00:00
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SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
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2010-05-21 16:32:16 +00:00
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// Make sure the first definition is not a partial redefinition. Add an
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// <imp-def> of the full register.
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2011-10-05 16:51:21 +00:00
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// FIXME: LiveIntervals shouldn't modify the code like this. Whoever
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// created the machine instruction should annotate it with <undef> flags
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// as needed. Then we can simply assert here. The REG_SEQUENCE lowering
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// is the main suspect.
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2011-10-04 21:49:33 +00:00
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if (MO.getSubReg()) {
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2010-05-21 16:32:16 +00:00
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mi->addRegisterDefined(interval.reg);
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2011-10-04 21:49:33 +00:00
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// Mark all defs of interval.reg on this instruction as reading <undef>.
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for (unsigned i = MOIdx, e = mi->getNumOperands(); i != e; ++i) {
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MachineOperand &MO2 = mi->getOperand(i);
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if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg())
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MO2.setIsUndef();
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}
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}
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2010-05-21 16:32:16 +00:00
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2012-02-04 05:20:49 +00:00
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VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
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2007-08-29 20:45:00 +00:00
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assert(ValNo->id == 0 && "First value in interval is not 0?");
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2004-08-04 09:46:26 +00:00
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// Loop over all of the blocks that the vreg is defined in. There are
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// two cases we have to handle here. The most common case is a vreg
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// whose lifetime is contained within a basic block. In this case there
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// will be a single kill, in MBB, which comes after the definition.
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if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
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// FIXME: what about dead vars?
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2009-11-03 23:52:08 +00:00
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SlotIndex killIdx;
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2004-08-04 09:46:26 +00:00
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if (vi.Kills[0] != mi)
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2011-11-13 20:45:27 +00:00
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killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
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2004-08-04 09:46:26 +00:00
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else
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2011-11-13 20:45:27 +00:00
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killIdx = defIndex.getDeadSlot();
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2004-08-04 09:46:26 +00:00
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// If the kill happens after the definition, we have an intra-block
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// live range.
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if (killIdx > defIndex) {
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2009-05-26 18:27:15 +00:00
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assert(vi.AliveBlocks.empty() &&
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2004-08-04 09:46:26 +00:00
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"Shouldn't be alive across any blocks!");
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2007-08-29 20:45:00 +00:00
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LiveRange LR(defIndex, killIdx, ValNo);
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2004-08-04 09:46:26 +00:00
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interval.addRange(LR);
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2010-01-04 22:49:02 +00:00
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DEBUG(dbgs() << " +" << LR << "\n");
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2004-08-04 09:46:26 +00:00
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return;
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}
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}
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2004-07-19 02:15:56 +00:00
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2004-08-04 09:46:26 +00:00
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// The other case we handle is when a virtual register lives to the end
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// of the defining block, potentially live across some blocks, then is
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// live into some number of blocks, but gets killed. Start by adding a
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// range that goes from this definition to the end of the defining block.
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2009-12-22 00:11:50 +00:00
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LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
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2010-01-04 22:49:02 +00:00
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DEBUG(dbgs() << " +" << NewLR);
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2004-08-04 09:46:26 +00:00
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interval.addRange(NewLR);
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2010-02-23 22:43:58 +00:00
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bool PHIJoin = lv_->isPHIJoin(interval.reg);
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if (PHIJoin) {
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// A phi join register is killed at the end of the MBB and revived as a new
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// valno in the killing blocks.
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assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
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DEBUG(dbgs() << " phi-join");
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ValNo->setHasPHIKill(true);
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} else {
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// Iterate over all of the blocks that the variable is completely
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// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
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// live interval.
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for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
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E = vi.AliveBlocks.end(); I != E; ++I) {
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MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
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LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
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interval.addRange(LR);
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DEBUG(dbgs() << " +" << LR);
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}
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2004-08-04 09:46:26 +00:00
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}
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// Finally, this virtual register is live from the start of any killing
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// block to the 'use' slot of the killing instruction.
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for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
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MachineInstr *Kill = vi.Kills[i];
|
2010-02-23 22:43:58 +00:00
|
|
|
SlotIndex Start = getMBBStartIdx(Kill->getParent());
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
|
2010-02-23 22:43:58 +00:00
|
|
|
|
|
|
|
// Create interval with one of a NEW value number. Note that this value
|
|
|
|
// number isn't actually defined by an instruction, weird huh? :)
|
|
|
|
if (PHIJoin) {
|
2010-09-25 12:04:16 +00:00
|
|
|
assert(getInstructionFromIndex(Start) == 0 &&
|
|
|
|
"PHI def index points at actual instruction.");
|
2012-02-04 05:20:49 +00:00
|
|
|
ValNo = interval.getNextValue(Start, VNInfoAllocator);
|
2010-02-23 22:43:58 +00:00
|
|
|
ValNo->setIsPHIDef(true);
|
|
|
|
}
|
|
|
|
LiveRange LR(Start, killIdx, ValNo);
|
2004-08-04 09:46:26 +00:00
|
|
|
interval.addRange(LR);
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << " +" << LR);
|
2004-08-04 09:46:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
} else {
|
2010-05-05 18:27:40 +00:00
|
|
|
if (MultipleDefsBySameMI(*mi, MOIdx))
|
2010-05-20 03:30:09 +00:00
|
|
|
// Multiple defs of the same virtual register by the same instruction.
|
|
|
|
// e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
|
2010-05-04 20:26:52 +00:00
|
|
|
// This is likely due to elimination of REG_SEQUENCE instructions. Return
|
|
|
|
// here since there is nothing to do.
|
|
|
|
return;
|
|
|
|
|
2004-08-04 09:46:26 +00:00
|
|
|
// If this is the second time we see a virtual register definition, it
|
|
|
|
// must be due to phi elimination or two addr elimination. If this is
|
2006-11-03 03:04:46 +00:00
|
|
|
// the result of two address elimination, then the vreg is one of the
|
|
|
|
// def-and-use register operand.
|
2010-05-05 18:27:40 +00:00
|
|
|
|
|
|
|
// It may also be partial redef like this:
|
2010-08-12 20:01:23 +00:00
|
|
|
// 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
|
|
|
|
// 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
|
2010-05-05 18:27:40 +00:00
|
|
|
bool PartReDef = isPartialRedef(MIIdx, MO, interval);
|
|
|
|
if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
|
2004-08-04 09:46:26 +00:00
|
|
|
// If this is a two-address definition, then we have already processed
|
|
|
|
// the live range. The only problem is that we didn't realize there
|
|
|
|
// are actually two values in the live interval. Because of this we
|
|
|
|
// need to take the LiveRegion that defines this register and split it
|
|
|
|
// into two values.
|
2011-11-13 22:05:42 +00:00
|
|
|
SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
|
2004-08-04 09:46:26 +00:00
|
|
|
|
2009-09-12 03:34:03 +00:00
|
|
|
const LiveRange *OldLR =
|
2011-11-13 20:45:27 +00:00
|
|
|
interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
|
2007-08-29 20:45:00 +00:00
|
|
|
VNInfo *OldValNo = OldLR->valno;
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex DefIndex = OldValNo->def.getRegSlot();
|
2007-08-11 00:59:19 +00:00
|
|
|
|
Allow a register to be redefined multiple times in a basic block.
LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.
Here is an example of chained INSERT_SUBREGs that we can handle now:
68 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
register: %reg1040 +[70,134:0)
76 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0) 0@78-(134) 1@70-(78)
84 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0) 0@86-(134) 1@70-(78) 2@78-(86)
92 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0) 0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)
rdar://problem/8096390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 21:29:40 +00:00
|
|
|
// Delete the previous value, which should be short and continuous,
|
2006-08-22 18:19:46 +00:00
|
|
|
// because the 2-addr copy must be in the same MBB as the redef.
|
2004-08-04 09:46:26 +00:00
|
|
|
interval.removeRange(DefIndex, RedefIndex);
|
2004-08-04 09:46:56 +00:00
|
|
|
|
2006-08-31 05:54:43 +00:00
|
|
|
// The new value number (#1) is defined by the instruction we claimed
|
|
|
|
// defined value #0.
|
2010-09-25 12:04:16 +00:00
|
|
|
VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
|
2009-06-17 21:01:20 +00:00
|
|
|
|
2006-08-31 05:54:43 +00:00
|
|
|
// Value#0 is now defined by the 2-addr instruction.
|
2012-02-04 05:20:49 +00:00
|
|
|
OldValNo->def = RedefIndex;
|
2010-08-12 20:01:23 +00:00
|
|
|
|
2006-08-22 18:19:46 +00:00
|
|
|
// Add the new live interval which replaces the range for the input copy.
|
|
|
|
LiveRange LR(DefIndex, RedefIndex, ValNo);
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << " replace range with " << LR);
|
2004-08-04 09:46:26 +00:00
|
|
|
interval.addRange(LR);
|
|
|
|
|
|
|
|
// If this redefinition is dead, we need to add a dummy unit live
|
|
|
|
// range covering the def slot.
|
2008-06-25 23:39:39 +00:00
|
|
|
if (MO.isDead())
|
2011-11-13 20:45:27 +00:00
|
|
|
interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
|
2009-11-03 23:52:08 +00:00
|
|
|
OldValNo));
|
2004-08-04 09:46:26 +00:00
|
|
|
|
2009-08-22 20:18:03 +00:00
|
|
|
DEBUG({
|
2010-01-04 22:49:02 +00:00
|
|
|
dbgs() << " RESULT: ";
|
|
|
|
interval.print(dbgs(), tri_);
|
2009-08-22 20:18:03 +00:00
|
|
|
});
|
2010-05-05 18:27:40 +00:00
|
|
|
} else if (lv_->isPHIJoin(interval.reg)) {
|
2004-08-04 09:46:26 +00:00
|
|
|
// In the case of PHI elimination, each variable definition is only
|
|
|
|
// live until the end of the block. We've already taken care of the
|
|
|
|
// rest of the live range.
|
2010-02-23 22:43:58 +00:00
|
|
|
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex defIndex = MIIdx.getRegSlot();
|
2009-03-23 08:01:15 +00:00
|
|
|
if (MO.isEarlyClobber())
|
2011-11-13 20:45:27 +00:00
|
|
|
defIndex = MIIdx.getRegSlot(true);
|
2009-09-14 21:33:42 +00:00
|
|
|
|
2012-02-04 05:20:49 +00:00
|
|
|
VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
|
2010-08-12 20:01:23 +00:00
|
|
|
|
2009-12-22 00:11:50 +00:00
|
|
|
SlotIndex killIndex = getMBBEndIdx(mbb);
|
2007-08-29 20:45:00 +00:00
|
|
|
LiveRange LR(defIndex, killIndex, ValNo);
|
2004-08-04 09:46:26 +00:00
|
|
|
interval.addRange(LR);
|
2009-06-17 21:01:20 +00:00
|
|
|
ValNo->setHasPHIKill(true);
|
2010-02-23 22:43:58 +00:00
|
|
|
DEBUG(dbgs() << " phi-join +" << LR);
|
2010-05-05 18:27:40 +00:00
|
|
|
} else {
|
|
|
|
llvm_unreachable("Multiply defined register");
|
2003-12-18 08:48:48 +00:00
|
|
|
}
|
2004-08-04 09:46:26 +00:00
|
|
|
}
|
2003-11-20 03:32:25 +00:00
|
|
|
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << '\n');
|
2003-11-20 03:32:25 +00:00
|
|
|
}
|
|
|
|
|
2012-02-14 18:51:53 +00:00
|
|
|
#ifndef NDEBUG
|
|
|
|
static bool isRegLiveOutOf(const MachineBasicBlock *MBB, unsigned Reg) {
|
|
|
|
for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
|
|
|
|
SE = MBB->succ_end();
|
|
|
|
SI != SE; ++SI) {
|
|
|
|
const MachineBasicBlock* succ = *SI;
|
|
|
|
if (succ->isLiveIn(Reg))
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2004-07-23 21:24:19 +00:00
|
|
|
void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
|
2003-11-20 03:32:25 +00:00
|
|
|
MachineBasicBlock::iterator mi,
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex MIIdx,
|
2008-06-25 23:39:39 +00:00
|
|
|
MachineOperand& MO,
|
2012-02-04 05:20:49 +00:00
|
|
|
LiveInterval &interval) {
|
2011-01-09 03:05:53 +00:00
|
|
|
DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
|
2004-08-04 09:46:26 +00:00
|
|
|
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex baseIndex = MIIdx;
|
2011-11-13 22:05:42 +00:00
|
|
|
SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex end = start;
|
2004-08-04 09:46:26 +00:00
|
|
|
|
|
|
|
// If it is not used after definition, it is considered dead at
|
|
|
|
// the instruction defining it. Hence its interval is:
|
|
|
|
// [defSlot(def), defSlot(def)+1)
|
2009-09-20 00:36:41 +00:00
|
|
|
// For earlyclobbers, the defSlot was pushed back one; the extra
|
|
|
|
// advance below compensates.
|
2008-06-25 23:39:39 +00:00
|
|
|
if (MO.isDead()) {
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << " dead");
|
2011-11-13 20:45:27 +00:00
|
|
|
end = start.getDeadSlot();
|
2005-08-23 22:51:41 +00:00
|
|
|
goto exit;
|
2004-08-04 09:46:26 +00:00
|
|
|
}
|
2003-11-20 03:32:25 +00:00
|
|
|
|
2004-08-04 09:46:26 +00:00
|
|
|
// If it is not dead on definition, it must be killed by a
|
|
|
|
// subsequent instruction. Hence its interval is:
|
|
|
|
// [defSlot(def), useSlot(kill)+1)
|
2009-11-03 23:52:08 +00:00
|
|
|
baseIndex = baseIndex.getNextIndex();
|
2005-09-02 00:20:32 +00:00
|
|
|
while (++mi != MBB->end()) {
|
2009-11-03 23:52:08 +00:00
|
|
|
|
2010-02-10 00:55:42 +00:00
|
|
|
if (mi->isDebugValue())
|
|
|
|
continue;
|
2009-11-03 23:52:08 +00:00
|
|
|
if (getInstructionFromIndex(baseIndex) == 0)
|
|
|
|
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
|
|
|
|
|
2008-03-05 00:59:57 +00:00
|
|
|
if (mi->killsRegister(interval.reg, tri_)) {
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << " killed");
|
2011-11-13 20:45:27 +00:00
|
|
|
end = baseIndex.getRegSlot();
|
2005-08-23 22:51:41 +00:00
|
|
|
goto exit;
|
2009-04-27 20:42:46 +00:00
|
|
|
} else {
|
2010-05-21 20:53:24 +00:00
|
|
|
int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
|
2009-04-27 20:42:46 +00:00
|
|
|
if (DefIdx != -1) {
|
|
|
|
if (mi->isRegTiedToUseOperand(DefIdx)) {
|
|
|
|
// Two-address instruction.
|
2012-02-04 05:41:20 +00:00
|
|
|
end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
|
2009-04-27 20:42:46 +00:00
|
|
|
} else {
|
|
|
|
// Another instruction redefines the register before it is ever read.
|
2010-02-10 00:55:42 +00:00
|
|
|
// Then the register is essentially dead at the instruction that
|
|
|
|
// defines it. Hence its interval is:
|
2009-04-27 20:42:46 +00:00
|
|
|
// [defSlot(def), defSlot(def)+1)
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << " dead");
|
2011-11-13 20:45:27 +00:00
|
|
|
end = start.getDeadSlot();
|
2009-04-27 20:42:46 +00:00
|
|
|
}
|
|
|
|
goto exit;
|
|
|
|
}
|
2004-07-23 21:24:19 +00:00
|
|
|
}
|
2010-08-12 20:01:23 +00:00
|
|
|
|
2009-11-03 23:52:08 +00:00
|
|
|
baseIndex = baseIndex.getNextIndex();
|
2004-08-04 09:46:26 +00:00
|
|
|
}
|
2010-08-12 20:01:23 +00:00
|
|
|
|
2012-02-14 18:51:53 +00:00
|
|
|
// If we get here the register *should* be live out.
|
|
|
|
assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
|
2004-01-31 23:13:30 +00:00
|
|
|
|
2012-02-14 18:51:53 +00:00
|
|
|
// FIXME: We need saner rules for reserved regs.
|
|
|
|
if (isReserved(interval.reg)) {
|
|
|
|
assert(!isRegLiveOutOf(MBB, interval.reg) && "Reserved reg live-out?");
|
|
|
|
end = start.getDeadSlot();
|
|
|
|
} else {
|
|
|
|
// Unreserved, unallocable registers like EFLAGS can be live across basic
|
|
|
|
// block boundaries.
|
|
|
|
assert(isRegLiveOutOf(MBB, interval.reg) && "Unreserved reg not live-out?");
|
|
|
|
end = getMBBEndIdx(MBB);
|
|
|
|
}
|
2003-11-20 03:32:25 +00:00
|
|
|
exit:
|
2004-08-04 09:46:26 +00:00
|
|
|
assert(start < end && "did not find end of interval?");
|
Allow the live interval analysis pass to be a bit more aggressive about
numbering values in live ranges for physical registers.
The alpha backend currently generates code that looks like this:
vreg = preg
...
preg = vreg
use preg
...
preg = vreg
use preg
etc. Because vreg contains the value of preg coming in, each of the
copies back into preg contain that initial value as well.
In the case of the Alpha, this allows this testcase:
void "foo"(int %blah) {
store int 5, int *%MyVar
store int 12, int* %MyVar2
ret void
}
to compile to:
foo:
ldgp $29, 0($27)
ldiq $0,5
stl $0,MyVar
ldiq $0,12
stl $0,MyVar2
ret $31,($26),1
instead of:
foo:
ldgp $29, 0($27)
bis $29,$29,$0
ldiq $1,5
bis $0,$0,$29
stl $1,MyVar
ldiq $1,12
bis $0,$0,$29
stl $1,MyVar2
ret $31,($26),1
This does not seem to have any noticable effect on X86 code.
This fixes PR535.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20536 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-09 23:05:19 +00:00
|
|
|
|
2007-04-25 07:30:23 +00:00
|
|
|
// Already exists? Extend old live interval.
|
2010-10-11 21:45:03 +00:00
|
|
|
VNInfo *ValNo = interval.getVNInfoAt(start);
|
|
|
|
bool Extend = ValNo != 0;
|
|
|
|
if (!Extend)
|
2012-02-04 05:20:49 +00:00
|
|
|
ValNo = interval.getNextValue(start, VNInfoAllocator);
|
2007-08-29 20:45:00 +00:00
|
|
|
LiveRange LR(start, end, ValNo);
|
2004-08-04 09:46:26 +00:00
|
|
|
interval.addRange(LR);
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << " +" << LR << '\n');
|
2003-11-20 03:32:25 +00:00
|
|
|
}
|
|
|
|
|
2004-07-23 21:24:19 +00:00
|
|
|
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex MIIdx,
|
2008-07-10 07:35:43 +00:00
|
|
|
MachineOperand& MO,
|
|
|
|
unsigned MOIdx) {
|
2008-06-25 23:39:39 +00:00
|
|
|
if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
2008-07-10 07:35:43 +00:00
|
|
|
handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
|
2008-06-25 23:39:39 +00:00
|
|
|
getOrCreateInterval(MO.getReg()));
|
2012-02-04 05:20:49 +00:00
|
|
|
else
|
2009-04-27 20:42:46 +00:00
|
|
|
handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
|
2012-02-04 05:20:49 +00:00
|
|
|
getOrCreateInterval(MO.getReg()));
|
2004-01-31 14:37:41 +00:00
|
|
|
}
|
|
|
|
|
2007-02-19 21:49:54 +00:00
|
|
|
void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex MIIdx,
|
2012-02-10 03:19:36 +00:00
|
|
|
LiveInterval &interval) {
|
2012-02-14 18:51:53 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
|
|
|
|
"Only physical registers can be live in.");
|
|
|
|
assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
|
|
|
|
MBB->isLandingPad()) &&
|
|
|
|
"Allocatable live-ins only valid for entry blocks and landing pads.");
|
|
|
|
|
2011-01-09 03:05:53 +00:00
|
|
|
DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
|
2007-02-19 21:49:54 +00:00
|
|
|
|
|
|
|
// Look for kills, if it reaches a def before it's killed, then it shouldn't
|
|
|
|
// be considered a livein.
|
|
|
|
MachineBasicBlock::iterator mi = MBB->begin();
|
2010-03-16 21:51:27 +00:00
|
|
|
MachineBasicBlock::iterator E = MBB->end();
|
|
|
|
// Skip over DBG_VALUE at the start of the MBB.
|
|
|
|
if (mi != E && mi->isDebugValue()) {
|
|
|
|
while (++mi != E && mi->isDebugValue())
|
|
|
|
;
|
|
|
|
if (mi == E)
|
|
|
|
// MBB is empty except for DBG_VALUE's.
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex baseIndex = MIIdx;
|
|
|
|
SlotIndex start = baseIndex;
|
|
|
|
if (getInstructionFromIndex(baseIndex) == 0)
|
|
|
|
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
|
|
|
|
|
|
|
|
SlotIndex end = baseIndex;
|
2009-03-05 03:34:26 +00:00
|
|
|
bool SeenDefUse = false;
|
2007-02-19 21:49:54 +00:00
|
|
|
|
2010-02-10 00:55:42 +00:00
|
|
|
while (mi != E) {
|
2010-02-10 01:31:26 +00:00
|
|
|
if (mi->killsRegister(interval.reg, tri_)) {
|
|
|
|
DEBUG(dbgs() << " killed");
|
2011-11-13 20:45:27 +00:00
|
|
|
end = baseIndex.getRegSlot();
|
2010-02-10 01:31:26 +00:00
|
|
|
SeenDefUse = true;
|
|
|
|
break;
|
2010-05-21 20:53:24 +00:00
|
|
|
} else if (mi->definesRegister(interval.reg, tri_)) {
|
2010-02-10 01:31:26 +00:00
|
|
|
// Another instruction redefines the register before it is ever read.
|
|
|
|
// Then the register is essentially dead at the instruction that defines
|
|
|
|
// it. Hence its interval is:
|
|
|
|
// [defSlot(def), defSlot(def)+1)
|
|
|
|
DEBUG(dbgs() << " dead");
|
2011-11-13 20:45:27 +00:00
|
|
|
end = start.getDeadSlot();
|
2010-02-10 01:31:26 +00:00
|
|
|
SeenDefUse = true;
|
|
|
|
break;
|
2010-02-10 00:55:42 +00:00
|
|
|
}
|
2010-02-10 01:31:26 +00:00
|
|
|
|
2010-03-16 21:51:27 +00:00
|
|
|
while (++mi != E && mi->isDebugValue())
|
|
|
|
// Skip over DBG_VALUE.
|
|
|
|
;
|
|
|
|
if (mi != E)
|
2009-11-03 23:52:08 +00:00
|
|
|
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
|
2007-02-19 21:49:54 +00:00
|
|
|
}
|
|
|
|
|
2007-06-27 01:16:36 +00:00
|
|
|
// Live-in register might not be used at all.
|
2009-03-05 03:34:26 +00:00
|
|
|
if (!SeenDefUse) {
|
2012-02-14 18:51:53 +00:00
|
|
|
if (isAllocatable(interval.reg) || isReserved(interval.reg)) {
|
|
|
|
// This must be an entry block or landing pad - we asserted so on entry
|
|
|
|
// to the function. For these blocks the interval is dead on entry.
|
|
|
|
DEBUG(dbgs() << " dead");
|
|
|
|
end = start.getDeadSlot();
|
|
|
|
} else {
|
|
|
|
assert(isRegLiveOutOf(MBB, interval.reg) &&
|
|
|
|
"Live in reg untouched in block should be be live through.");
|
|
|
|
DEBUG(dbgs() << " live through");
|
|
|
|
end = getMBBEndIdx(MBB);
|
|
|
|
}
|
2007-04-25 07:30:23 +00:00
|
|
|
}
|
|
|
|
|
2010-09-25 12:04:16 +00:00
|
|
|
SlotIndex defIdx = getMBBStartIdx(MBB);
|
|
|
|
assert(getInstructionFromIndex(defIdx) == 0 &&
|
|
|
|
"PHI def index points at actual instruction.");
|
2012-02-04 05:20:49 +00:00
|
|
|
VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
|
2009-06-18 22:01:47 +00:00
|
|
|
vni->setIsPHIDef(true);
|
|
|
|
LiveRange LR(start, end, vni);
|
2009-11-07 01:58:40 +00:00
|
|
|
|
2007-02-21 22:41:17 +00:00
|
|
|
interval.addRange(LR);
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << " +" << LR << '\n');
|
2007-02-19 21:49:54 +00:00
|
|
|
}
|
|
|
|
|
2003-11-20 03:32:25 +00:00
|
|
|
/// computeIntervals - computes the live intervals for virtual
|
2004-01-31 14:37:41 +00:00
|
|
|
/// registers. for some ordering of the machine instructions [1,N] a
|
2004-01-31 19:59:32 +00:00
|
|
|
/// live interval is an interval [i, j) where 1 <= i <= j < N for
|
2003-11-20 03:32:25 +00:00
|
|
|
/// which a variable is live
|
2010-08-12 20:01:23 +00:00
|
|
|
void LiveIntervals::computeIntervals() {
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
|
2009-08-22 20:18:03 +00:00
|
|
|
<< "********** Function: "
|
|
|
|
<< ((Value*)mf_->getFunction())->getName() << '\n');
|
2009-07-17 19:43:40 +00:00
|
|
|
|
2012-02-10 01:26:29 +00:00
|
|
|
RegMaskBlocks.resize(mf_->getNumBlockIDs());
|
|
|
|
|
2009-07-17 19:43:40 +00:00
|
|
|
SmallVector<unsigned, 8> UndefUses;
|
2006-09-15 03:57:23 +00:00
|
|
|
for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
|
|
|
|
MBBI != E; ++MBBI) {
|
|
|
|
MachineBasicBlock *MBB = MBBI;
|
2012-02-10 01:26:29 +00:00
|
|
|
RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
|
|
|
|
|
2010-02-06 09:07:11 +00:00
|
|
|
if (MBB->empty())
|
|
|
|
continue;
|
|
|
|
|
2008-09-21 20:43:24 +00:00
|
|
|
// Track the index of the current machine instr.
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex MIIndex = getMBBStartIdx(MBB);
|
2010-05-03 21:38:11 +00:00
|
|
|
DEBUG(dbgs() << "BB#" << MBB->getNumber()
|
|
|
|
<< ":\t\t# derived from " << MBB->getName() << "\n");
|
2004-08-04 09:46:26 +00:00
|
|
|
|
2007-10-03 19:26:29 +00:00
|
|
|
// Create intervals for live-ins to this BB first.
|
2010-04-13 16:57:55 +00:00
|
|
|
for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
|
2007-10-03 19:26:29 +00:00
|
|
|
LE = MBB->livein_end(); LI != LE; ++LI) {
|
|
|
|
handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
|
2006-09-04 18:27:40 +00:00
|
|
|
}
|
2010-08-12 20:01:23 +00:00
|
|
|
|
2008-09-15 22:00:38 +00:00
|
|
|
// Skip over empty initial indices.
|
2009-11-03 23:52:08 +00:00
|
|
|
if (getInstructionFromIndex(MIIndex) == 0)
|
|
|
|
MIIndex = indexes_->getNextNonNullIndex(MIIndex);
|
2010-08-12 20:01:23 +00:00
|
|
|
|
2010-01-22 22:38:21 +00:00
|
|
|
for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
|
|
|
|
MI != miEnd; ++MI) {
|
2010-01-04 22:49:02 +00:00
|
|
|
DEBUG(dbgs() << MIIndex << "\t" << *MI);
|
2010-02-09 19:54:29 +00:00
|
|
|
if (MI->isDebugValue())
|
2010-01-22 22:38:21 +00:00
|
|
|
continue;
|
2012-02-08 17:33:45 +00:00
|
|
|
assert(indexes_->getInstructionFromIndex(MIIndex) == MI &&
|
|
|
|
"Lost SlotIndex synchronization");
|
2004-08-04 09:46:26 +00:00
|
|
|
|
2006-11-10 08:43:01 +00:00
|
|
|
// Handle defs.
|
2006-09-15 03:57:23 +00:00
|
|
|
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2012-02-08 17:33:45 +00:00
|
|
|
|
|
|
|
// Collect register masks.
|
|
|
|
if (MO.isRegMask()) {
|
|
|
|
RegMaskSlots.push_back(MIIndex.getRegSlot());
|
|
|
|
RegMaskBits.push_back(MO.getRegMask());
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2009-07-17 19:43:40 +00:00
|
|
|
if (!MO.isReg() || !MO.getReg())
|
|
|
|
continue;
|
|
|
|
|
2004-08-04 09:46:26 +00:00
|
|
|
// handle register defs - build intervals
|
2009-07-17 19:43:40 +00:00
|
|
|
if (MO.isDef())
|
2008-07-10 07:35:43 +00:00
|
|
|
handleRegisterDef(MBB, MI, MIIndex, MO, i);
|
2009-07-17 19:43:40 +00:00
|
|
|
else if (MO.isUndef())
|
|
|
|
UndefUses.push_back(MO.getReg());
|
2004-08-04 09:46:26 +00:00
|
|
|
}
|
2010-08-12 20:01:23 +00:00
|
|
|
|
2009-11-03 23:52:08 +00:00
|
|
|
// Move to the next instr slot.
|
|
|
|
MIIndex = indexes_->getNextNonNullIndex(MIIndex);
|
2003-11-20 03:32:25 +00:00
|
|
|
}
|
2012-02-10 01:26:29 +00:00
|
|
|
|
|
|
|
// Compute the number of register mask instructions in this block.
|
|
|
|
std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
|
|
|
|
RMB.second = RegMaskSlots.size() - RMB.first;;
|
2004-08-04 09:46:26 +00:00
|
|
|
}
|
2009-07-17 19:43:40 +00:00
|
|
|
|
|
|
|
// Create empty intervals for registers defined by implicit_def's (except
|
|
|
|
// for those implicit_def that define values which are liveout of their
|
|
|
|
// blocks.
|
|
|
|
for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
|
|
|
|
unsigned UndefReg = UndefUses[i];
|
|
|
|
(void)getOrCreateInterval(UndefReg);
|
|
|
|
}
|
2003-11-20 03:32:25 +00:00
|
|
|
}
|
2003-12-05 10:38:28 +00:00
|
|
|
|
2008-08-13 21:49:13 +00:00
|
|
|
LiveInterval* LiveIntervals::createInterval(unsigned reg) {
|
2009-02-08 11:04:35 +00:00
|
|
|
float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
|
2008-08-13 21:49:13 +00:00
|
|
|
return new LiveInterval(reg, Weight);
|
2004-04-09 18:07:57 +00:00
|
|
|
}
|
2007-11-12 06:35:08 +00:00
|
|
|
|
2009-02-08 11:04:35 +00:00
|
|
|
/// dupInterval - Duplicate a live interval. The caller is responsible for
|
|
|
|
/// managing the allocated memory.
|
|
|
|
LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
|
|
|
|
LiveInterval *NewLI = createInterval(li->reg);
|
2009-06-14 20:22:55 +00:00
|
|
|
NewLI->Copy(*li, mri_, getVNInfoAllocator());
|
2009-02-08 11:04:35 +00:00
|
|
|
return NewLI;
|
|
|
|
}
|
|
|
|
|
2011-02-08 00:03:05 +00:00
|
|
|
/// shrinkToUses - After removing some uses of a register, shrink its live
|
|
|
|
/// range to just the remaining uses. This method does not compute reaching
|
|
|
|
/// defs for new uses, and it doesn't remove dead defs.
|
2011-03-17 20:37:07 +00:00
|
|
|
bool LiveIntervals::shrinkToUses(LiveInterval *li,
|
2011-03-07 23:29:10 +00:00
|
|
|
SmallVectorImpl<MachineInstr*> *dead) {
|
2011-02-08 00:03:05 +00:00
|
|
|
DEBUG(dbgs() << "Shrink: " << *li << '\n');
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(li->reg)
|
2012-01-03 20:05:57 +00:00
|
|
|
&& "Can only shrink virtual registers");
|
2011-02-08 00:03:05 +00:00
|
|
|
// Find all the values used, including PHI kills.
|
|
|
|
SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
|
|
|
|
|
2011-09-15 15:24:16 +00:00
|
|
|
// Blocks that have already been added to WorkList as live-out.
|
|
|
|
SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
|
|
|
|
|
2011-02-08 00:03:05 +00:00
|
|
|
// Visit all instructions reading li->reg.
|
|
|
|
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
|
|
|
|
MachineInstr *UseMI = I.skipInstruction();) {
|
|
|
|
if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
|
|
|
|
continue;
|
2011-11-13 23:53:25 +00:00
|
|
|
SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
|
2011-11-14 18:45:38 +00:00
|
|
|
// Note: This intentionally picks up the wrong VNI in case of an EC redef.
|
|
|
|
// See below.
|
|
|
|
VNInfo *VNI = li->getVNInfoBefore(Idx);
|
2011-03-18 03:06:04 +00:00
|
|
|
if (!VNI) {
|
|
|
|
// This shouldn't happen: readsVirtualRegister returns true, but there is
|
|
|
|
// no live value. It is likely caused by a target getting <undef> flags
|
|
|
|
// wrong.
|
|
|
|
DEBUG(dbgs() << Idx << '\t' << *UseMI
|
|
|
|
<< "Warning: Instr claims to read non-existent value in "
|
|
|
|
<< *li << '\n');
|
|
|
|
continue;
|
|
|
|
}
|
2011-11-14 18:45:38 +00:00
|
|
|
// Special case: An early-clobber tied operand reads and writes the
|
|
|
|
// register one slot early. The getVNInfoBefore call above would have
|
|
|
|
// picked up the value defined by UseMI. Adjust the kill slot and value.
|
|
|
|
if (SlotIndex::isSameInstr(VNI->def, Idx)) {
|
|
|
|
Idx = VNI->def;
|
2011-11-13 23:53:25 +00:00
|
|
|
VNI = li->getVNInfoBefore(Idx);
|
2011-02-08 00:03:05 +00:00
|
|
|
assert(VNI && "Early-clobber tied value not available");
|
|
|
|
}
|
|
|
|
WorkList.push_back(std::make_pair(Idx, VNI));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a new live interval with only minimal live segments per def.
|
|
|
|
LiveInterval NewLI(li->reg, 0);
|
|
|
|
for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
|
|
|
|
I != E; ++I) {
|
|
|
|
VNInfo *VNI = *I;
|
|
|
|
if (VNI->isUnused())
|
|
|
|
continue;
|
2011-11-13 22:42:13 +00:00
|
|
|
NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
|
2011-02-08 00:03:05 +00:00
|
|
|
}
|
|
|
|
|
2011-03-02 00:33:03 +00:00
|
|
|
// Keep track of the PHIs that are in use.
|
|
|
|
SmallPtrSet<VNInfo*, 8> UsedPHIs;
|
|
|
|
|
2011-02-08 00:03:05 +00:00
|
|
|
// Extend intervals to reach all uses in WorkList.
|
|
|
|
while (!WorkList.empty()) {
|
|
|
|
SlotIndex Idx = WorkList.back().first;
|
|
|
|
VNInfo *VNI = WorkList.back().second;
|
|
|
|
WorkList.pop_back();
|
2011-11-13 23:53:25 +00:00
|
|
|
const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
|
2011-02-08 00:03:05 +00:00
|
|
|
SlotIndex BlockStart = getMBBStartIdx(MBB);
|
2011-03-02 00:33:03 +00:00
|
|
|
|
|
|
|
// Extend the live range for VNI to be live at Idx.
|
2011-11-13 23:53:25 +00:00
|
|
|
if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
|
2011-03-02 01:43:30 +00:00
|
|
|
(void)ExtVNI;
|
2011-03-02 00:33:03 +00:00
|
|
|
assert(ExtVNI == VNI && "Unexpected existing value number");
|
|
|
|
// Is this a PHIDef we haven't seen before?
|
2011-03-03 00:20:51 +00:00
|
|
|
if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
|
2011-03-02 00:33:03 +00:00
|
|
|
continue;
|
|
|
|
// The PHI is live, make sure the predecessors are live-out.
|
|
|
|
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
|
|
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
2011-09-15 15:24:16 +00:00
|
|
|
if (!LiveOut.insert(*PI))
|
|
|
|
continue;
|
2011-11-13 23:53:25 +00:00
|
|
|
SlotIndex Stop = getMBBEndIdx(*PI);
|
2011-03-02 00:33:03 +00:00
|
|
|
// A predecessor is not required to have a live-out value for a PHI.
|
2011-11-13 23:53:25 +00:00
|
|
|
if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
|
2011-03-02 00:33:03 +00:00
|
|
|
WorkList.push_back(std::make_pair(Stop, PVNI));
|
2011-02-08 00:03:05 +00:00
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// VNI is live-in to MBB.
|
|
|
|
DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
|
2011-11-13 23:53:25 +00:00
|
|
|
NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
|
2011-02-08 00:03:05 +00:00
|
|
|
|
|
|
|
// Make sure VNI is live-out from the predecessors.
|
|
|
|
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
|
|
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
2011-09-15 15:24:16 +00:00
|
|
|
if (!LiveOut.insert(*PI))
|
|
|
|
continue;
|
2011-11-13 23:53:25 +00:00
|
|
|
SlotIndex Stop = getMBBEndIdx(*PI);
|
|
|
|
assert(li->getVNInfoBefore(Stop) == VNI &&
|
|
|
|
"Wrong value out of predecessor");
|
2011-02-08 00:03:05 +00:00
|
|
|
WorkList.push_back(std::make_pair(Stop, VNI));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handle dead values.
|
2011-03-17 20:37:07 +00:00
|
|
|
bool CanSeparate = false;
|
2011-02-08 00:03:05 +00:00
|
|
|
for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
|
|
|
|
I != E; ++I) {
|
|
|
|
VNInfo *VNI = *I;
|
|
|
|
if (VNI->isUnused())
|
|
|
|
continue;
|
|
|
|
LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
|
|
|
|
assert(LII != NewLI.end() && "Missing live range for PHI");
|
2011-11-13 22:42:13 +00:00
|
|
|
if (LII->end != VNI->def.getDeadSlot())
|
2011-02-08 00:03:05 +00:00
|
|
|
continue;
|
2011-03-02 00:33:01 +00:00
|
|
|
if (VNI->isPHIDef()) {
|
2011-02-08 00:03:05 +00:00
|
|
|
// This is a dead PHI. Remove it.
|
|
|
|
VNI->setIsUnused(true);
|
|
|
|
NewLI.removeRange(*LII);
|
2011-03-17 20:37:07 +00:00
|
|
|
DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
|
|
|
|
CanSeparate = true;
|
2011-02-08 00:03:05 +00:00
|
|
|
} else {
|
|
|
|
// This is a dead def. Make sure the instruction knows.
|
|
|
|
MachineInstr *MI = getInstructionFromIndex(VNI->def);
|
|
|
|
assert(MI && "No instruction defining live value");
|
|
|
|
MI->addRegisterDead(li->reg, tri_);
|
2011-03-07 23:29:10 +00:00
|
|
|
if (dead && MI->allDefsAreDead()) {
|
2011-03-16 22:56:08 +00:00
|
|
|
DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
|
2011-03-07 23:29:10 +00:00
|
|
|
dead->push_back(MI);
|
|
|
|
}
|
2011-02-08 00:03:05 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Move the trimmed ranges back.
|
|
|
|
li->ranges.swap(NewLI.ranges);
|
2011-03-16 22:56:08 +00:00
|
|
|
DEBUG(dbgs() << "Shrunk: " << *li << '\n');
|
2011-03-17 20:37:07 +00:00
|
|
|
return CanSeparate;
|
2011-02-08 00:03:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-11-12 06:35:08 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Register allocator hooks.
|
|
|
|
//
|
|
|
|
|
2011-02-08 21:13:03 +00:00
|
|
|
void LiveIntervals::addKillFlags() {
|
|
|
|
for (iterator I = begin(), E = end(); I != E; ++I) {
|
|
|
|
unsigned Reg = I->first;
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
|
|
continue;
|
|
|
|
if (mri_->reg_nodbg_empty(Reg))
|
|
|
|
continue;
|
|
|
|
LiveInterval *LI = I->second;
|
|
|
|
|
|
|
|
// Every instruction that kills Reg corresponds to a live range end point.
|
|
|
|
for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
|
|
|
|
++RI) {
|
2011-11-13 20:45:27 +00:00
|
|
|
// A block index indicates an MBB edge.
|
|
|
|
if (RI->end.isBlock())
|
2011-02-08 21:13:03 +00:00
|
|
|
continue;
|
|
|
|
MachineInstr *MI = getInstructionFromIndex(RI->end);
|
|
|
|
if (!MI)
|
|
|
|
continue;
|
|
|
|
MI->addRegisterKilled(Reg, NULL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-01-30 19:26:20 +00:00
|
|
|
#ifndef NDEBUG
|
2012-01-27 22:36:19 +00:00
|
|
|
static bool intervalRangesSane(const LiveInterval& li) {
|
|
|
|
if (li.empty()) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
SlotIndex lastEnd = li.begin()->start;
|
|
|
|
for (LiveInterval::const_iterator lrItr = li.begin(), lrEnd = li.end();
|
|
|
|
lrItr != lrEnd; ++lrItr) {
|
|
|
|
const LiveRange& lr = *lrItr;
|
|
|
|
if (lastEnd > lr.start || lr.start >= lr.end)
|
|
|
|
return false;
|
|
|
|
lastEnd = lr.end;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2012-01-30 19:26:20 +00:00
|
|
|
#endif
|
2012-01-27 22:36:19 +00:00
|
|
|
|
|
|
|
template <typename DefSetT>
|
|
|
|
static void handleMoveDefs(LiveIntervals& lis, SlotIndex origIdx,
|
|
|
|
SlotIndex miIdx, const DefSetT& defs) {
|
|
|
|
for (typename DefSetT::const_iterator defItr = defs.begin(),
|
|
|
|
defEnd = defs.end();
|
|
|
|
defItr != defEnd; ++defItr) {
|
|
|
|
unsigned def = *defItr;
|
|
|
|
LiveInterval& li = lis.getInterval(def);
|
|
|
|
LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot());
|
|
|
|
assert(lr != 0 && "No range for def?");
|
|
|
|
lr->start = miIdx.getRegSlot();
|
|
|
|
lr->valno->def = miIdx.getRegSlot();
|
|
|
|
assert(intervalRangesSane(li) && "Broke live interval moving def.");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template <typename DeadDefSetT>
|
|
|
|
static void handleMoveDeadDefs(LiveIntervals& lis, SlotIndex origIdx,
|
|
|
|
SlotIndex miIdx, const DeadDefSetT& deadDefs) {
|
|
|
|
for (typename DeadDefSetT::const_iterator deadDefItr = deadDefs.begin(),
|
|
|
|
deadDefEnd = deadDefs.end();
|
|
|
|
deadDefItr != deadDefEnd; ++deadDefItr) {
|
|
|
|
unsigned deadDef = *deadDefItr;
|
|
|
|
LiveInterval& li = lis.getInterval(deadDef);
|
|
|
|
LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot());
|
|
|
|
assert(lr != 0 && "No range for dead def?");
|
|
|
|
assert(lr->start == origIdx.getRegSlot() && "Bad dead range start?");
|
|
|
|
assert(lr->end == origIdx.getDeadSlot() && "Bad dead range end?");
|
|
|
|
assert(lr->valno->def == origIdx.getRegSlot() && "Bad dead valno def.");
|
|
|
|
LiveRange t(*lr);
|
|
|
|
t.start = miIdx.getRegSlot();
|
|
|
|
t.valno->def = miIdx.getRegSlot();
|
|
|
|
t.end = miIdx.getDeadSlot();
|
|
|
|
li.removeRange(*lr);
|
|
|
|
li.addRange(t);
|
|
|
|
assert(intervalRangesSane(li) && "Broke live interval moving dead def.");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template <typename ECSetT>
|
|
|
|
static void handleMoveECs(LiveIntervals& lis, SlotIndex origIdx,
|
|
|
|
SlotIndex miIdx, const ECSetT& ecs) {
|
|
|
|
for (typename ECSetT::const_iterator ecItr = ecs.begin(), ecEnd = ecs.end();
|
|
|
|
ecItr != ecEnd; ++ecItr) {
|
|
|
|
unsigned ec = *ecItr;
|
|
|
|
LiveInterval& li = lis.getInterval(ec);
|
|
|
|
LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot(true));
|
|
|
|
assert(lr != 0 && "No range for early clobber?");
|
|
|
|
assert(lr->start == origIdx.getRegSlot(true) && "Bad EC range start?");
|
|
|
|
assert(lr->end == origIdx.getRegSlot() && "Bad EC range end.");
|
|
|
|
assert(lr->valno->def == origIdx.getRegSlot(true) && "Bad EC valno def.");
|
|
|
|
LiveRange t(*lr);
|
|
|
|
t.start = miIdx.getRegSlot(true);
|
|
|
|
t.valno->def = miIdx.getRegSlot(true);
|
|
|
|
t.end = miIdx.getRegSlot();
|
|
|
|
li.removeRange(*lr);
|
|
|
|
li.addRange(t);
|
|
|
|
assert(intervalRangesSane(li) && "Broke live interval moving EC.");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-02-09 04:45:38 +00:00
|
|
|
static void moveKillFlags(unsigned reg, SlotIndex oldIdx, SlotIndex newIdx,
|
|
|
|
LiveIntervals& lis,
|
|
|
|
const TargetRegisterInfo& tri) {
|
|
|
|
MachineInstr* oldKillMI = lis.getInstructionFromIndex(oldIdx);
|
|
|
|
MachineInstr* newKillMI = lis.getInstructionFromIndex(newIdx);
|
|
|
|
assert(oldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
|
|
|
|
assert(!newKillMI->killsRegister(reg) && "New kill instr is already a kill.");
|
|
|
|
oldKillMI->clearRegisterKills(reg, &tri);
|
|
|
|
newKillMI->addRegisterKilled(reg, &tri);
|
|
|
|
}
|
|
|
|
|
2012-01-27 22:36:19 +00:00
|
|
|
template <typename UseSetT>
|
|
|
|
static void handleMoveUses(const MachineBasicBlock *mbb,
|
|
|
|
const MachineRegisterInfo& mri,
|
2012-02-09 04:45:38 +00:00
|
|
|
const TargetRegisterInfo& tri,
|
2012-01-27 22:36:19 +00:00
|
|
|
const BitVector& reservedRegs, LiveIntervals &lis,
|
|
|
|
SlotIndex origIdx, SlotIndex miIdx,
|
|
|
|
const UseSetT &uses) {
|
|
|
|
bool movingUp = miIdx < origIdx;
|
|
|
|
for (typename UseSetT::const_iterator usesItr = uses.begin(),
|
|
|
|
usesEnd = uses.end();
|
|
|
|
usesItr != usesEnd; ++usesItr) {
|
|
|
|
unsigned use = *usesItr;
|
|
|
|
if (!lis.hasInterval(use))
|
|
|
|
continue;
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(use) && reservedRegs.test(use))
|
|
|
|
continue;
|
|
|
|
LiveInterval& li = lis.getInterval(use);
|
|
|
|
LiveRange* lr = li.getLiveRangeBefore(origIdx.getRegSlot());
|
|
|
|
assert(lr != 0 && "No range for use?");
|
|
|
|
bool liveThrough = lr->end > origIdx.getRegSlot();
|
|
|
|
|
|
|
|
if (movingUp) {
|
|
|
|
// If moving up and liveThrough - nothing to do.
|
|
|
|
// If not live through we need to extend the range to the last use
|
|
|
|
// between the old location and the new one.
|
|
|
|
if (!liveThrough) {
|
|
|
|
SlotIndex lastUseInRange = miIdx.getRegSlot();
|
|
|
|
for (MachineRegisterInfo::use_iterator useI = mri.use_begin(use),
|
|
|
|
useE = mri.use_end();
|
|
|
|
useI != useE; ++useI) {
|
|
|
|
const MachineInstr* mopI = &*useI;
|
|
|
|
const MachineOperand& mop = useI.getOperand();
|
|
|
|
SlotIndex instSlot = lis.getSlotIndexes()->getInstructionIndex(mopI);
|
|
|
|
SlotIndex opSlot = instSlot.getRegSlot(mop.isEarlyClobber());
|
2012-02-09 04:45:38 +00:00
|
|
|
if (opSlot > lastUseInRange && opSlot < origIdx)
|
2012-01-27 22:36:19 +00:00
|
|
|
lastUseInRange = opSlot;
|
|
|
|
}
|
2012-02-09 04:45:38 +00:00
|
|
|
|
|
|
|
// If we found a new instr endpoint update the kill flags.
|
|
|
|
if (lastUseInRange != miIdx.getRegSlot())
|
|
|
|
moveKillFlags(use, miIdx, lastUseInRange, lis, tri);
|
|
|
|
|
|
|
|
// Fix up the range end.
|
2012-01-27 22:36:19 +00:00
|
|
|
lr->end = lastUseInRange;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// Moving down is easy - the existing live range end tells us where
|
|
|
|
// the last kill is.
|
|
|
|
if (!liveThrough) {
|
|
|
|
// Easy fix - just update the range endpoint.
|
|
|
|
lr->end = miIdx.getRegSlot();
|
|
|
|
} else {
|
|
|
|
bool liveOut = lr->end >= lis.getSlotIndexes()->getMBBEndIdx(mbb);
|
|
|
|
if (!liveOut && miIdx.getRegSlot() > lr->end) {
|
2012-02-09 04:45:38 +00:00
|
|
|
moveKillFlags(use, lr->end, miIdx, lis, tri);
|
2012-01-27 22:36:19 +00:00
|
|
|
lr->end = miIdx.getRegSlot();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
assert(intervalRangesSane(li) && "Broke live interval moving use.");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void LiveIntervals::moveInstr(MachineBasicBlock::iterator insertPt,
|
|
|
|
MachineInstr *mi) {
|
|
|
|
MachineBasicBlock* mbb = mi->getParent();
|
2012-01-27 23:52:25 +00:00
|
|
|
assert((insertPt == mbb->end() || insertPt->getParent() == mbb) &&
|
2012-01-27 22:36:19 +00:00
|
|
|
"Cannot handle moves across basic block boundaries.");
|
|
|
|
assert(&*insertPt != mi && "No-op move requested?");
|
2012-02-08 02:17:25 +00:00
|
|
|
assert(!mi->isBundled() && "Can't handle bundled instructions yet.");
|
2012-01-27 22:36:19 +00:00
|
|
|
|
|
|
|
// Grab the original instruction index.
|
|
|
|
SlotIndex origIdx = indexes_->getInstructionIndex(mi);
|
|
|
|
|
|
|
|
// Move the machine instr and obtain its new index.
|
|
|
|
indexes_->removeMachineInstrFromMaps(mi);
|
2012-02-09 04:45:38 +00:00
|
|
|
mbb->splice(insertPt, mbb, mi);
|
2012-01-27 22:36:19 +00:00
|
|
|
SlotIndex miIdx = indexes_->insertMachineInstrInMaps(mi);
|
|
|
|
|
|
|
|
// Pick the direction.
|
|
|
|
bool movingUp = miIdx < origIdx;
|
|
|
|
|
|
|
|
// Collect the operands.
|
|
|
|
DenseSet<unsigned> uses, defs, deadDefs, ecs;
|
|
|
|
for (MachineInstr::mop_iterator mopItr = mi->operands_begin(),
|
|
|
|
mopEnd = mi->operands_end();
|
|
|
|
mopItr != mopEnd; ++mopItr) {
|
|
|
|
const MachineOperand& mop = *mopItr;
|
|
|
|
|
|
|
|
if (!mop.isReg() || mop.getReg() == 0)
|
|
|
|
continue;
|
|
|
|
unsigned reg = mop.getReg();
|
|
|
|
|
|
|
|
if (mop.readsReg() && !ecs.count(reg)) {
|
|
|
|
uses.insert(reg);
|
|
|
|
}
|
|
|
|
if (mop.isDef()) {
|
|
|
|
if (mop.isDead()) {
|
|
|
|
assert(!defs.count(reg) && "Can't mix defs with dead-defs.");
|
|
|
|
deadDefs.insert(reg);
|
|
|
|
} else if (mop.isEarlyClobber()) {
|
|
|
|
uses.erase(reg);
|
|
|
|
ecs.insert(reg);
|
|
|
|
} else {
|
|
|
|
assert(!deadDefs.count(reg) && "Can't mix defs with dead-defs.");
|
|
|
|
defs.insert(reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (movingUp) {
|
2012-02-14 23:06:12 +00:00
|
|
|
handleMoveUses(mbb, *mri_, *tri_, reservedRegs_, *this, origIdx, miIdx, uses);
|
2012-01-27 22:36:19 +00:00
|
|
|
handleMoveECs(*this, origIdx, miIdx, ecs);
|
|
|
|
handleMoveDeadDefs(*this, origIdx, miIdx, deadDefs);
|
|
|
|
handleMoveDefs(*this, origIdx, miIdx, defs);
|
|
|
|
} else {
|
|
|
|
handleMoveDefs(*this, origIdx, miIdx, defs);
|
|
|
|
handleMoveDeadDefs(*this, origIdx, miIdx, deadDefs);
|
|
|
|
handleMoveECs(*this, origIdx, miIdx, ecs);
|
2012-02-14 23:06:12 +00:00
|
|
|
handleMoveUses(mbb, *mri_, *tri_, reservedRegs_, *this, origIdx, miIdx, uses);
|
2012-01-27 22:36:19 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-02-22 09:24:50 +00:00
|
|
|
/// getReMatImplicitUse - If the remat definition MI has one (for now, we only
|
|
|
|
/// allow one) virtual register operand, then its uses are implicitly using
|
|
|
|
/// the register. Returns the virtual register.
|
|
|
|
unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
|
|
|
|
MachineInstr *MI) const {
|
|
|
|
unsigned RegOp = 0;
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2008-10-03 15:45:36 +00:00
|
|
|
if (!MO.isReg() || !MO.isUse())
|
2008-02-22 09:24:50 +00:00
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (Reg == 0 || Reg == li.reg)
|
|
|
|
continue;
|
2010-08-12 20:01:23 +00:00
|
|
|
|
2012-02-14 03:04:29 +00:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isAllocatable(Reg))
|
2009-06-27 04:06:41 +00:00
|
|
|
continue;
|
2008-02-22 09:24:50 +00:00
|
|
|
RegOp = MO.getReg();
|
2012-01-25 21:53:23 +00:00
|
|
|
break; // Found vreg operand - leave the loop.
|
2008-02-22 09:24:50 +00:00
|
|
|
}
|
|
|
|
return RegOp;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isValNoAvailableAt - Return true if the val# of the specified interval
|
|
|
|
/// which reaches the given instruction also reaches the specified use index.
|
|
|
|
bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex UseIdx) const {
|
2010-10-11 21:45:03 +00:00
|
|
|
VNInfo *UValNo = li.getVNInfoAt(UseIdx);
|
|
|
|
return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI));
|
2008-02-22 09:24:50 +00:00
|
|
|
}
|
|
|
|
|
2007-11-12 06:35:08 +00:00
|
|
|
/// isReMaterializable - Returns true if the definition MI of the specified
|
|
|
|
/// val# of the specified interval is re-materializable.
|
2010-11-10 19:18:47 +00:00
|
|
|
bool
|
|
|
|
LiveIntervals::isReMaterializable(const LiveInterval &li,
|
|
|
|
const VNInfo *ValNo, MachineInstr *MI,
|
2011-03-10 01:21:58 +00:00
|
|
|
const SmallVectorImpl<LiveInterval*> *SpillIs,
|
2010-11-10 19:18:47 +00:00
|
|
|
bool &isLoad) {
|
2007-11-12 06:35:08 +00:00
|
|
|
if (DisableReMat)
|
|
|
|
return false;
|
|
|
|
|
2009-10-09 23:27:56 +00:00
|
|
|
if (!tii_->isTriviallyReMaterializable(MI, aa_))
|
|
|
|
return false;
|
2007-11-12 06:35:08 +00:00
|
|
|
|
2009-10-09 23:27:56 +00:00
|
|
|
// Target-specific code can mark an instruction as being rematerializable
|
|
|
|
// if it has one virtual reg use, though it had better be something like
|
|
|
|
// a PIC base register which is likely to be live everywhere.
|
2008-07-25 00:02:30 +00:00
|
|
|
unsigned ImpUse = getReMatImplicitUse(li, MI);
|
|
|
|
if (ImpUse) {
|
|
|
|
const LiveInterval &ImpLi = getInterval(ImpUse);
|
2010-03-30 05:49:07 +00:00
|
|
|
for (MachineRegisterInfo::use_nodbg_iterator
|
|
|
|
ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
|
|
|
|
ri != re; ++ri) {
|
2008-07-25 00:02:30 +00:00
|
|
|
MachineInstr *UseMI = &*ri;
|
2009-11-03 23:52:08 +00:00
|
|
|
SlotIndex UseIdx = getInstructionIndex(UseMI);
|
2010-10-11 21:45:03 +00:00
|
|
|
if (li.getVNInfoAt(UseIdx) != ValNo)
|
2008-07-25 00:02:30 +00:00
|
|
|
continue;
|
|
|
|
if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
|
|
|
|
return false;
|
|
|
|
}
|
2008-09-30 15:44:16 +00:00
|
|
|
|
|
|
|
// If a register operand of the re-materialized instruction is going to
|
|
|
|
// be spilled next, then it's not legal to re-materialize this instruction.
|
2011-03-10 01:21:58 +00:00
|
|
|
if (SpillIs)
|
|
|
|
for (unsigned i = 0, e = SpillIs->size(); i != e; ++i)
|
|
|
|
if (ImpUse == (*SpillIs)[i]->reg)
|
|
|
|
return false;
|
2008-07-25 00:02:30 +00:00
|
|
|
}
|
|
|
|
return true;
|
2007-12-06 00:01:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// isReMaterializable - Returns true if every definition of MI of every
|
|
|
|
/// val# of the specified interval is re-materializable.
|
2010-11-10 19:18:47 +00:00
|
|
|
bool
|
|
|
|
LiveIntervals::isReMaterializable(const LiveInterval &li,
|
2011-03-10 01:21:58 +00:00
|
|
|
const SmallVectorImpl<LiveInterval*> *SpillIs,
|
2010-11-10 19:18:47 +00:00
|
|
|
bool &isLoad) {
|
2007-12-06 00:01:56 +00:00
|
|
|
isLoad = false;
|
|
|
|
for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
|
|
|
|
i != e; ++i) {
|
|
|
|
const VNInfo *VNI = *i;
|
2009-06-17 21:01:20 +00:00
|
|
|
if (VNI->isUnused())
|
2007-12-06 00:01:56 +00:00
|
|
|
continue; // Dead val#.
|
|
|
|
// Is the def for the val# rematerializable?
|
2009-06-17 21:01:20 +00:00
|
|
|
MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
|
2010-09-25 12:04:16 +00:00
|
|
|
if (!ReMatDefMI)
|
|
|
|
return false;
|
2007-12-06 00:01:56 +00:00
|
|
|
bool DefIsLoad = false;
|
2008-02-22 09:24:50 +00:00
|
|
|
if (!ReMatDefMI ||
|
2008-09-30 15:44:16 +00:00
|
|
|
!isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
|
2007-11-12 06:35:08 +00:00
|
|
|
return false;
|
2007-12-06 00:01:56 +00:00
|
|
|
isLoad |= DefIsLoad;
|
2007-11-12 06:35:08 +00:00
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-02-10 01:23:55 +00:00
|
|
|
MachineBasicBlock*
|
|
|
|
LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
|
|
|
|
// A local live range must be fully contained inside the block, meaning it is
|
|
|
|
// defined and killed at instructions, not at block boundaries. It is not
|
|
|
|
// live in or or out of any block.
|
|
|
|
//
|
|
|
|
// It is technically possible to have a PHI-defined live range identical to a
|
|
|
|
// single block, but we are going to return false in that case.
|
|
|
|
|
|
|
|
SlotIndex Start = LI.beginIndex();
|
|
|
|
if (Start.isBlock())
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
SlotIndex Stop = LI.endIndex();
|
|
|
|
if (Stop.isBlock())
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
// getMBBFromIndex doesn't need to search the MBB table when both indexes
|
|
|
|
// belong to proper instructions.
|
|
|
|
MachineBasicBlock *MBB1 = indexes_->getMBBFromIndex(Start);
|
|
|
|
MachineBasicBlock *MBB2 = indexes_->getMBBFromIndex(Stop);
|
|
|
|
return MBB1 == MBB2 ? MBB1 : NULL;
|
Live interval splitting:
When a live interval is being spilled, rather than creating short, non-spillable
intervals for every def / use, split the interval at BB boundaries. That is, for
every BB where the live interval is defined or used, create a new interval that
covers all the defs and uses in the BB.
This is designed to eliminate one common problem: multiple reloads of the same
value in a single basic block. Note, it does *not* decrease the number of spills
since no copies are inserted so the split intervals are *connected* through
spill and reloads (or rematerialization). The newly created intervals can be
spilled again, in that case, since it does not span multiple basic blocks, it's
spilled in the usual manner. However, it can reuse the same stack slot as the
previously split interval.
This is currently controlled by -split-intervals-at-bb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44198 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-17 00:40:40 +00:00
|
|
|
}
|
|
|
|
|
2010-03-01 20:59:38 +00:00
|
|
|
float
|
|
|
|
LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
|
|
|
|
// Limit the loop depth ridiculousness.
|
|
|
|
if (loopDepth > 200)
|
|
|
|
loopDepth = 200;
|
|
|
|
|
|
|
|
// The loop depth is used to roughly estimate the number of times the
|
|
|
|
// instruction is executed. Something like 10^d is simple, but will quickly
|
|
|
|
// overflow a float. This expression behaves like 10^d for small d, but is
|
|
|
|
// more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
|
|
|
|
// headroom before overflow.
|
2011-03-31 12:11:33 +00:00
|
|
|
// By the way, powf() might be unavailable here. For consistency,
|
|
|
|
// We may take pow(double,double).
|
|
|
|
float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
|
2010-03-01 20:59:38 +00:00
|
|
|
|
|
|
|
return (isDef + isUse) * lc;
|
|
|
|
}
|
|
|
|
|
2008-06-05 17:15:43 +00:00
|
|
|
LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
|
2009-07-09 03:57:02 +00:00
|
|
|
MachineInstr* startInst) {
|
2008-06-05 17:15:43 +00:00
|
|
|
LiveInterval& Interval = getOrCreateInterval(reg);
|
|
|
|
VNInfo* VN = Interval.getNextValue(
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex(getInstructionIndex(startInst).getRegSlot()),
|
2012-02-04 05:20:49 +00:00
|
|
|
getVNInfoAllocator());
|
2009-06-17 21:01:20 +00:00
|
|
|
VN->setHasPHIKill(true);
|
2009-09-04 20:41:11 +00:00
|
|
|
LiveRange LR(
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex(getInstructionIndex(startInst).getRegSlot()),
|
2009-12-22 00:11:50 +00:00
|
|
|
getMBBEndIdx(startInst->getParent()), VN);
|
2008-06-05 17:15:43 +00:00
|
|
|
Interval.addRange(LR);
|
2010-08-12 20:01:23 +00:00
|
|
|
|
2008-06-05 17:15:43 +00:00
|
|
|
return LR;
|
|
|
|
}
|
2012-02-08 17:33:45 +00:00
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Register mask functions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
|
|
|
|
BitVector &UsableRegs) {
|
|
|
|
if (LI.empty())
|
|
|
|
return false;
|
2012-02-10 01:31:31 +00:00
|
|
|
LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
|
|
|
|
|
|
|
|
// Use a smaller arrays for local live ranges.
|
|
|
|
ArrayRef<SlotIndex> Slots;
|
|
|
|
ArrayRef<const uint32_t*> Bits;
|
|
|
|
if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
|
|
|
|
Slots = getRegMaskSlotsInBlock(MBB->getNumber());
|
|
|
|
Bits = getRegMaskBitsInBlock(MBB->getNumber());
|
|
|
|
} else {
|
|
|
|
Slots = getRegMaskSlots();
|
|
|
|
Bits = getRegMaskBits();
|
|
|
|
}
|
2012-02-08 17:33:45 +00:00
|
|
|
|
|
|
|
// We are going to enumerate all the register mask slots contained in LI.
|
|
|
|
// Start with a binary search of RegMaskSlots to find a starting point.
|
|
|
|
ArrayRef<SlotIndex>::iterator SlotI =
|
|
|
|
std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
|
|
|
|
ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
|
|
|
|
|
|
|
|
// No slots in range, LI begins after the last call.
|
|
|
|
if (SlotI == SlotE)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
bool Found = false;
|
|
|
|
for (;;) {
|
|
|
|
assert(*SlotI >= LiveI->start);
|
|
|
|
// Loop over all slots overlapping this segment.
|
|
|
|
while (*SlotI < LiveI->end) {
|
|
|
|
// *SlotI overlaps LI. Collect mask bits.
|
|
|
|
if (!Found) {
|
|
|
|
// This is the first overlap. Initialize UsableRegs to all ones.
|
|
|
|
UsableRegs.clear();
|
|
|
|
UsableRegs.resize(tri_->getNumRegs(), true);
|
|
|
|
Found = true;
|
|
|
|
}
|
|
|
|
// Remove usable registers clobbered by this mask.
|
2012-02-10 01:31:31 +00:00
|
|
|
UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
|
2012-02-08 17:33:45 +00:00
|
|
|
if (++SlotI == SlotE)
|
|
|
|
return Found;
|
|
|
|
}
|
|
|
|
// *SlotI is beyond the current LI segment.
|
|
|
|
LiveI = LI.advanceTo(LiveI, *SlotI);
|
|
|
|
if (LiveI == LiveE)
|
|
|
|
return Found;
|
|
|
|
// Advance SlotI until it overlaps.
|
|
|
|
while (*SlotI < LiveI->start)
|
|
|
|
if (++SlotI == SlotE)
|
|
|
|
return Found;
|
|
|
|
}
|
|
|
|
}
|