2005-10-16 05:39:50 +00:00
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//===- PPCRegisterInfo.h - PowerPC Register Information Impl -----*- C++ -*-==//
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPC32_REGISTERINFO_H
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#define POWERPC32_REGISTERINFO_H
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2005-10-14 23:51:18 +00:00
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#include "PPC.h"
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2005-10-14 23:37:35 +00:00
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#include "PPCGenRegisterInfo.h.inc"
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2004-08-17 04:55:41 +00:00
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#include <map>
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namespace llvm {
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2006-07-11 00:48:23 +00:00
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class PPCSubtarget;
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2006-11-27 23:37:22 +00:00
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class TargetInstrInfo;
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class Type;
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2005-10-16 05:39:50 +00:00
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class PPCRegisterInfo : public PPCGenRegisterInfo {
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std::map<unsigned, unsigned> ImmToIdxMap;
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const PPCSubtarget &Subtarget;
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2006-11-13 23:36:35 +00:00
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const TargetInstrInfo &TII;
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public:
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PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
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2006-04-17 21:07:20 +00:00
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// PPC::F14, return the number that it corresponds to (e.g. 14).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// Code Generation virtual methods...
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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2004-08-17 04:55:41 +00:00
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2007-10-05 01:32:41 +00:00
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void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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2007-10-18 22:40:57 +00:00
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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2007-10-18 21:29:24 +00:00
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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2007-10-05 01:32:41 +00:00
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2004-08-17 04:55:41 +00:00
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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2007-10-05 01:32:41 +00:00
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void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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2007-10-18 21:29:24 +00:00
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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2004-08-17 04:55:41 +00:00
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void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned DestReg, unsigned SrcReg,
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2007-09-26 06:25:56 +00:00
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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2007-03-20 08:09:38 +00:00
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, const MachineInstr *Orig) const;
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2005-09-09 21:46:49 +00:00
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/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
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/// copy instructions, turning them into load/store instructions.
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virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
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int FrameIndex) const;
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2007-08-30 05:52:20 +00:00
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virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
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MachineInstr* LoadMI) const {
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return 0;
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}
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2007-07-14 14:06:15 +00:00
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const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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2006-05-18 00:12:58 +00:00
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
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2006-05-18 00:12:58 +00:00
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2007-02-19 21:49:54 +00:00
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BitVector getReservedRegs(const MachineFunction &MF) const;
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2007-01-25 22:25:04 +00:00
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/// targetHandlesStackFrameRounding - Returns true if the target is
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/// responsible for rounding up the stack frame (probably at emitPrologue
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/// time).
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bool targetHandlesStackFrameRounding() const { return true; }
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2007-01-23 00:57:47 +00:00
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bool hasFP(const MachineFunction &MF) const;
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2004-08-17 04:55:41 +00:00
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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2006-12-06 17:42:06 +00:00
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/// usesLR - Returns if the link registers (LR) has been used in the function.
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///
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bool usesLR(MachineFunction &MF) const;
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2006-11-16 22:43:37 +00:00
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void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
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2007-02-28 00:21:17 +00:00
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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2007-05-01 09:13:03 +00:00
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int SPAdj, RegScavenger *RS = NULL) const;
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2006-11-16 22:43:37 +00:00
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/// determineFrameLayout - Determine the size of the frame and maximum call
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/// frame size.
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void determineFrameLayout(MachineFunction &MF) const;
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2007-03-06 10:05:14 +00:00
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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2004-08-17 04:55:41 +00:00
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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2006-03-23 18:12:57 +00:00
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2006-03-28 13:48:33 +00:00
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// Debug information queries.
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2006-04-07 16:34:46 +00:00
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unsigned getRARegister() const;
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2006-03-28 13:48:33 +00:00
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unsigned getFrameRegister(MachineFunction &MF) const;
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2007-01-24 18:45:13 +00:00
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void getInitialFrameState(std::vector<MachineMove> &Moves) const;
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2007-02-21 22:54:50 +00:00
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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2004-08-17 04:55:41 +00:00
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};
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} // end namespace llvm
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#endif
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