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llvm-6502/test/MC/Disassembler/X86/x86-32.txt

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Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-16 02:41:28 +00:00
# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 | FileCheck %s
# Coverage
# CHECK: pushl
0xff 0x34 0x24
# CHECK: popl
0x58
# CHECK: calll
0xff 0xd0
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 01:54:29 +00:00
# CHECK: jecxz -127
0xe3 0x81
# CHECK: jcxz -127
0x67 0xe3 0x81
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-16 02:41:28 +00:00
# CHECK: incl
0x40
# CHECK: leave
0xc9
# PR8873: some instructions not recognized in 32-bit mode
# CHECK: fld
0xdd 0x04 0x24
# CHECK: pshufb
0x0f 0x38 0x00 0xc0
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 22:06:28 +00:00
# CHECK: crc32b %al, %eax
0xf2 0x0f 0x38 0xf0 0xc0
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:03:03 +00:00
# CHECK: crc32w %ax, %eax
0x66 0xf2 0x0f 0x38 0xf1 0xc0
Fix VEX decoding in i386 mode. Fixes PR11008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 19:54:56 +00:00
# CHECK: crc32l %eax, %eax
0xf2 0x0f 0x38 0xf1 0xc0
Fix VEX decoding in i386 mode. Fixes PR11008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
# CHECK: int $33
0xCD 0x21
# CHECK: int $33
0xCD 0x21
# CHECK: addb %al, (%eax)
0 0
# CHECK: calll -1234
0xe8 0x2e 0xfb 0xff 0xff
# CHECK: lfence
0x0f 0xae 0xe8
# CHECK: mfence
0x0f 0xae 0xf0
# CHECK: monitor
0x0f 0x01 0xc8
# CHECK: mwait
0x0f 0x01 0xc9
# CHECK: vmcall
0x0f 0x01 0xc1
Add vmfunc instruction to X86 assembler and disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 01:39:49 +00:00
# CHECK: vmfunc
0x0f 0x01 0xd4
Fix VEX decoding in i386 mode. Fixes PR11008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
# CHECK: vmlaunch
0x0f 0x01 0xc2
# CHECK: vmresume
0x0f 0x01 0xc3
# CHECK: vmxoff
0x0f 0x01 0xc4
# CHECK: swapgs
0x0f 0x01 0xf8
# CHECK: rdtscp
0x0f 0x01 0xf9
# CHECK: vmxon
0xf3 0x0f 0xc7 0x30
# CHECK: vmptrld
0x0f 0xc7 0x30
# CHECK: vmptrst
0x0f 0xc7 0x38
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 08:19:49 +00:00
# CHECK: vmrun
0x0f 0x01 0xd8
# CHECK: vmmcall
0x0f 0x01 0xd9
# CHECK: vmload
0x0f 0x01 0xda
# CHECK: vmsave
0x0f 0x01 0xdb
# CHECK: stgi
0x0f 0x01 0xdc
# CHECK: clgi
0x0f 0x01 0xdd
# CHECK: skinit
0x0f 0x01 0xde
# CHECK: invlpga
0x0f 0x01 0xdf
Fix VEX decoding in i386 mode. Fixes PR11008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
# CHECK: movl $0, -4(%ebp)
0xc7 0x45 0xfc 0x00 0x00 0x00 0x00
# CHECK: movl %cr0, %ecx
0x0f 0x20 0xc1
# CHECK: leal 4(%esp), %ecx
0x8d 0x4c 0x24 0x04
# CHECK: enter $1, $2
0xc8 0x01 0x00 0x02
# CHECK: movw $47416, -66(%ebp)
0x66 0xc7 0x45 0xbe 0x38 0xb9
Test updates that were supposed to go with r140993. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 07:53:59 +00:00
# CHECK: vaddpd %ymm5, %ymm1, %ymm0
Fix VEX decoding in i386 mode. Fixes PR11008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
0xc4 0xc1 0x75 0x58 0xc5
# CHECK: vaddps %ymm3, %ymm1, %ymm0
0xc5 0xf4 0x58 0xc3
Test updates that were supposed to go with r140993. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 07:53:59 +00:00
# CHECK: vandpd %ymm5, %ymm1, %ymm0
Fix VEX decoding in i386 mode. Fixes PR11008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
0xc4 0xc1 0x75 0x54 0xc5
# CHECK: vandps %ymm3, %ymm1, %ymm0
0xc5 0xf4 0x54 0xc3
# CHECK: vzeroall
0xc5 0xfc 0x77
# CHECK: vcvtps2pd %xmm0, %ymm0
0xc5 0xfc 0x5a 0xc0
# CHECK: vandps (%edx), %xmm1, %xmm7
0xc5 0xf0 0x54 0x3a
# CHECK: vcvtss2sil %xmm0, %eax
0xc5 0xfa 0x2d 0xc0
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26 07:48:28 +00:00
# CHECK: vcvtsd2sil %xmm0, %eax
Fix VEX decoding in i386 mode. Fixes PR11008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
0xc5 0xfb 0x2d 0xc0
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26 07:48:28 +00:00
# CHECK: vcvtsd2sil %xmm0, %eax
Test updates that were supposed to go with r140993. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 07:53:59 +00:00
0xc4 0xe1 0x7b 0x2d 0xc0
Fix VEX decoding in i386 mode. Fixes PR11008. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 05:12:43 +00:00
# CHECK: vmaskmovpd %xmm0, %xmm1, (%eax)
0xc4 0xe2 0x71 0x2f 0x00
# CHECK: vmovapd %xmm0, %xmm2
0xc5 0xf9 0x28 0xd0
# Check these special case instructions that the immediate is not sign-extend.
# CHECK: blendps $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x0c 0xca 0x81
# CHECK: blendpd $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x0d 0xca 0x81
# CHECK: pblendw $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x0e 0xca 0x81
# CHECK: mpsadbw $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x42 0xca 0x81
# CHECK: dpps $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x40 0xca 0x81
# CHECK: dppd $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x41 0xca 0x81
# CHECK: insertps $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x21 0xca 0x81
# CHECK: vblendps $129, %ymm2, %ymm5, %ymm1
0xc4 0xe3 0x55 0x0c 0xca 0x81
# CHECK: vblendps $129, (%eax), %ymm5, %ymm1
0xc4 0xe3 0x55 0x0c 0x08 0x81
# CHECK: vblendpd $129, %ymm2, %ymm5, %ymm1
0xc4 0xe3 0x55 0x0d 0xca 0x81
# CHECK: vblendpd $129, (%eax), %ymm5, %ymm1
0xc4 0xe3 0x55 0x0d 0x08 0x81
# CHECK: vpblendw $129, %xmm2, %xmm5, %xmm1
0xc4 0xe3 0x51 0x0e 0xca 0x81
# CHECK: vmpsadbw $129, %xmm2, %xmm5, %xmm1
0xc4 0xe3 0x51 0x42 0xca 0x81
# CHECK: vdpps $129, %ymm2, %ymm5, %ymm1
0xc4 0xe3 0x55 0x40 0xca 0x81
# CHECK: vdpps $129, (%eax), %ymm5, %ymm1
0xc4 0xe3 0x55 0x40 0x08 0x81
# CHECK: vdppd $129, %xmm2, %xmm5, %xmm1
0xc4 0xe3 0x51 0x41 0xca 0x81
# CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1
0xc4 0xe3 0x69 0x21 0xcb 0x81
# CHECK: pause
0xf3 0x90
# CHECK: addl %eax, %edi
0x01 0xc7
# CHECK: addl %edi, %eax
0x03 0xc7
# CHECK: movl %eax, %edi
0x89 0xc7
# CHECK: movl %edi, %eax
0x8b 0xc7
# CHECK: movups %xmm1, %xmm0
0x0f 0x10 0xc1
# CHECK: movups %xmm0, %xmm1
0x0f 0x11 0xc1
# CHECK: movaps %xmm1, %xmm0
0x0f 0x28 0xc1
# CHECK: movaps %xmm0, %xmm1
0x0f 0x29 0xc1
# CHECK: movupd %xmm1, %xmm0
0x66 0x0f 0x10 0xc1
# CHECK: movupd %xmm0, %xmm1
0x66 0x0f 0x11 0xc1
# CHECK: movapd %xmm1, %xmm0
0x66 0x0f 0x28 0xc1
# CHECK: movapd %xmm0, %xmm1
0x66 0x0f 0x29 0xc1
# CHECK: vmovups %xmm1, %xmm0
0xc5 0xf8 0x10 0xc1
# CHECK: vmovups %xmm0, %xmm1
0xc5 0xf8 0x11 0xc1
# CHECK: vmovaps %xmm1, %xmm0
0xc5 0xf8 0x28 0xc1
# CHECK: vmovaps %xmm0, %xmm1
0xc5 0xf8 0x29 0xc1
# CHECK: vmovupd %xmm1, %xmm0
0xc5 0xf9 0x10 0xc1
# CHECK: vmovupd %xmm0, %xmm1
0xc5 0xf9 0x11 0xc1
# CHECK: vmovapd %xmm1, %xmm0
0xc5 0xf9 0x28 0xc1
# CHECK: vmovapd %xmm0, %xmm1
0xc5 0xf9 0x29 0xc1
# CHECK: vmovups %ymm1, %ymm0
0xc5 0xfc 0x10 0xc1
# CHECK: vmovups %ymm0, %ymm1
0xc5 0xfc 0x11 0xc1
# CHECK: vmovaps %ymm1, %ymm0
0xc5 0xfc 0x28 0xc1
# CHECK: vmovaps %ymm0, %ymm1
0xc5 0xfc 0x29 0xc1
# CHECK: movdqa %xmm1, %xmm0
0x66 0x0f 0x6f 0xc1
# CHECK: movdqa %xmm0, %xmm1
0x66 0x0f 0x7f 0xc1
# CHECK: movdqu %xmm1, %xmm0
0xf3 0x0f 0x6f 0xc1
# CHECK: movdqu %xmm0, %xmm1
0xf3 0x0f 0x7f 0xc1
# CHECK: vmovdqa %xmm1, %xmm0
0xc5 0xf9 0x6f 0xc1
# CHECK: vmovdqa %xmm0, %xmm1
0xc5 0xf9 0x7f 0xc1
# CHECK: vmovdqa %ymm1, %ymm0
0xc5 0xfd 0x6f 0xc1
# CHECK: vmovdqa %ymm0, %ymm1
0xc5 0xfd 0x7f 0xc1
# CHECK: vmovdqu %xmm1, %xmm0
0xc5 0xfa 0x6f 0xc1
# CHECK: vmovdqu %xmm0, %xmm1
0xc5 0xfa 0x7f 0xc1
# CHECK: vmovdqu %ymm1, %ymm0
0xc5 0xfe 0x6f 0xc1
# CHECK: vmovdqu %ymm0, %ymm1
0xc5 0xfe 0x7f 0xc1
# CHECK: vblendvps %xmm4, %xmm1, %xmm2, %xmm3
0xc4 0xe3 0x69 0x4a 0xd9 0x41
# CHECK: vroundpd $0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x09 0xc0 0x00
# CHECK: vroundps $0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x08 0xc0 0x00
# CHECK: vroundpd $0, %ymm0, %ymm0
0xc4 0xe3 0x7d 0x09 0xc0 0x00
# CHECK: vroundps $0, %ymm0, %ymm0
0xc4 0xe3 0x7d 0x08 0xc0 0x00
# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x0a 0xc0 0x00
# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x0b 0xc0 0x00
Fix disassembling of INVEPT and INVVPID to take operands git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01 21:20:14 +00:00
# CHECK: invept (%eax), %eax
0x66 0x0f 0x38 0x80 0x00
# CHECK: invvpid (%eax), %eax
0x66 0x0f 0x38 0x81 0x00
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 21:08:12 +00:00
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:05:40 +00:00
# CHECK: invpcid (%eax), %eax
0x66 0x0f 0x38 0x82 0x00
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02 21:08:12 +00:00
# CHECK: nop
0x90
# CHECK: addb $0, %al
0x04 0x00
# CHECK: addw $0, %ax
0x66 0x05 0x00 0x00
# CHECK: addl $0, %eax
0x05 0x00 0x00 0x00 0x00
# CHECK: adcb $0, %al
0x14 0x00
# CHECK: adcw $0, %ax
0x66 0x15 0x00 0x00
# CHECK: adcl $0, %eax
0x15 0x00 0x00 0x00 0x00
# CHECK: cmpb $0, %al
0x3c 0x00
# CHECK: cmpw $0, %ax
0x66 0x3d 0x00 0x00
# CHECK: cmpl $0, %eax
0x3d 0x00 0x00 0x00 0x00
# CHECK: testb $0, %al
0xa8 0x00
# CHECK: testw $0, %ax
0x66 0xa9 0x00 0x00
# CHECK: testl $0, %eax
0xa9 0x00 0x00 0x00 0x00
# CHECK: movb 0, %al
0xa0 0x00 0x00 0x00 0x00
# CHECK: movw 0, %ax
0x66 0xa1 0x00 0x00 0x00 0x00
# CHECK: movl 0, %eax
0xa1 0x00 0x00 0x00 0x00
# CHECK: movb %al, 0
0xa2 0x00 0x00 0x00 0x00
# CHECK: movw %ax, 0
0x66 0xa3 0x00 0x00 0x00 0x00
# CHECK: movl %eax, 0
0xa3 0x00 0x00 0x00 0x00
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 08:14:29 +00:00
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03 05:20:24 +00:00
# CHECK: cmpordpd %xmm7, %xmm0
0x66 0x0f 0xc2 0xc7 0x07
# CHECK: cmpordps %xmm7, %xmm0
0x0f 0xc2 0xc7 0x07
# CHECK: cmpordsd %xmm7, %xmm0
0xf2 0x0f 0xc2 0xc7 0x07
# CHECK: cmpordss %xmm7, %xmm0
0xf3 0x0f 0xc2 0xc7 0x07
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 08:14:29 +00:00
# CHECK: vaddps %xmm3, %xmm7, %xmm0
0xc4 0xe1 0x00 0x58 0xc3
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 17:28:23 +00:00
# CHECK: movbel (%eax), %eax
0x0f 0x38 0xf0 0x00
# CHECK: movbel %eax, (%eax)
0x0f 0x38 0xf1 0x00
# CHECK: movbew (%eax), %ax
0x66 0x0f 0x38 0xf0 0x00
# CHECK: movbew %ax, (%eax)
0x66 0x0f 0x38 0xf1 0x00
# CHECK: rdrandw %ax
0x66 0x0f 0xc7 0xf0
# CHECK: rdrandl %eax
0x0f 0xc7 0xf0
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 06:30:42 +00:00
# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0
0xc4 0xe3 0x7d 0x0a 0xc0 0x00
# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0
0xc4 0xe3 0x7d 0x0b 0xc0 0x00
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26 07:48:28 +00:00
# CHECK: vcvtsd2sil %xmm0, %eax
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 06:30:42 +00:00
0xc4 0xe1 0x7f 0x2d 0xc0
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26 07:48:28 +00:00
# CHECK: vcvtsd2sil %xmm0, %eax
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 06:30:42 +00:00
0xc4 0xe1 0xff 0x2d 0xc0
# CHECK: vucomisd %xmm1, %xmm0
0xc5 0xfd 0x2e 0xc1
# CHECK: vucomiss %xmm1, %xmm0
0xc5 0xfc 0x2e 0xc1
# CHECK: vcomisd %xmm1, %xmm0
0xc5 0xfd 0x2f 0xc1
# CHECK: vcomiss %xmm1, %xmm0
0xc5 0xfc 0x2f 0xc1
# CHECK: vaddss %xmm1, %xmm0, %xmm0
0xc5 0xfe 0x58 0xc1
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:53:50 +00:00
# CHECK: xsave (%eax)
0x0f 0xae 0x20
# CHECK: xrstor (%eax)
0x0f 0xae 0x28
# CHECK: xsaveopt (%eax)
0x0f 0xae 0x30
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
# CHECK: vcvtph2ps %xmm0, %xmm0
0xc4 0xe2 0x79 0x13 0xc0
# CHECK: vcvtph2ps (%eax), %xmm0
0xc4 0xe2 0x79 0x13 0x00
# CHECK: vcvtph2ps %xmm0, %ymm0
0xc4 0xe2 0x7d 0x13 0xc0
# CHECK: vcvtph2ps (%eax), %ymm0
0xc4 0xe2 0x7d 0x13 0x00
# CHECK: vcvtps2ph $0, %xmm0, %xmm0
0xc4 0xe3 0x79 0x1d 0xc0 0x00
# CHECK: vcvtps2ph $0, %xmm0, (%eax)
0xc4 0xe3 0x79 0x1d 0x00 0x00
# CHECK: vcvtps2ph $0, %ymm0, %xmm0
0xc4 0xe3 0x7d 0x1d 0xc0 0x00
# CHECK: vcvtps2ph $0, %ymm0, (%eax)
0xc4 0xe3 0x7d 0x1d 0x00 0x00
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 04:34:23 +00:00
# CHECK: popcntl %eax, %eax
0xf3 0x0f 0xb8 0xc0
# CHECK: popcntw %ax, %ax
0x66 0xf3 0x0f 0xb8 0xc0
Add X86 LZCNT instruction. Including instruction selection support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 06:44:02 +00:00
# CHECK: lzcntl %eax, %eax
0xf3 0x0f 0xbd 0xc0
# CHECK: lzcntw %ax, %ax
0x66 0xf3 0x0f 0xbd 0xc0
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 03:21:46 +00:00
# CHECK: tzcntl %eax, %eax
0xf3 0x0f 0xbc 0xc0
# CHECK: tzcntw %ax, %ax
0x66 0xf3 0x0f 0xbc 0xc0
Add X86 ANDN instruction. Including instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 07:06:56 +00:00
# CHECK: andnl %ecx, %edi, %eax
0xc4 0xe2 0x00 0xf2 0xc1
# CHECK: andnl (%eax), %edi, %eax
0xc4 0xe2 0x00 0xf2 0x00
# CHECK: andnl %ecx, %edi, %eax
0xc4 0xe2 0x80 0xf2 0xc1
# CHECK: andnl (%eax), %edi, %eax
0xc4 0xe2 0x80 0xf2 0x00
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15 20:46:47 +00:00
# CHECK: blsrl (%eax), %edi
0xc4 0xe2 0x40 0xf3 0x08
# CHECK: blsmskl (%eax), %edi
0xc4 0xe2 0x40 0xf3 0x10
# CHECK: blsil (%eax), %edi
0xc4 0xe2 0x40 0xf3 0x18
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 03:51:13 +00:00
# CHECK: bextrl %esi, (%eax), %edx
0xc4 0xe2 0x08 0xf7 0x10
# CHECK: bextrl %esi, %ebx, %edx
0xc4 0xe2 0x08 0xf7 0xd3
Add X86 BZHI instruction as well as BMI2 feature detection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 07:55:05 +00:00
# CHECK: bzhil %esi, (%eax), %edx
0xc4 0xe2 0x08 0xf5 0x10
# CHECK: bzhil %esi, %ebx, %edx
0xc4 0xe2 0x08 0xf5 0xd3
Add X86 PEXTR and PDEP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
# CHECK: pextl %esp, %ecx, %edx
Add X86 PEXTR and PDEP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
0xc4 0xe2 0x72 0xf5 0xd4
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
# CHECK: pextl (%eax), %ecx, %edx
Add X86 PEXTR and PDEP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16 16:50:08 +00:00
0xc4 0xe2 0x72 0xf5 0x10
# CHECK: pdepl %esp, %ecx, %edx
0xc4 0xe2 0x73 0xf5 0xd4
# CHECK: pdepl (%eax), %ecx, %edx
0xc4 0xe2 0x73 0xf5 0x10
Add X86 MULX instruction for disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 00:33:32 +00:00
# CHECK: mulxl %esp, %ecx, %edx
0xc4 0xe2 0x73 0xf6 0xd4
# CHECK: mulxl (%eax), %ecx, %edx
0xc4 0xe2 0x73 0xf6 0x10
# CHECK: mulxl %esp, %ecx, %edx
0xc4 0xe2 0xf3 0xf6 0xd4
# CHECK: mulxl (%eax), %ecx, %edx
0xc4 0xe2 0xf3 0xf6 0x10
Add X86 RORX instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 07:34:00 +00:00
# CHECK: rorxl $1, %esp, %edx
0xc4 0xe3 0x7b 0xf0 0xd4 0x01
# CHECK: rorxl $31, (%eax), %edx
0xc4 0xe3 0x7b 0xf0 0x10 0x1f
Add X86 SARX, SHRX, and SHLX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 22:18:24 +00:00
# CHECK: shlxl %esi, (%eax), %edx
0xc4 0xe2 0x09 0xf7 0x10
# CHECK: shlxl %esi, %ebx, %edx
0xc4 0xe2 0x09 0xf7 0xd3
# CHECK: sarxl %esi, (%eax), %edx
0xc4 0xe2 0x0a 0xf7 0x10
# CHECK: sarxl %esi, %ebx, %edx
0xc4 0xe2 0x0a 0xf7 0xd3
# CHECK: shrxl %esi, (%eax), %edx
0xc4 0xe2 0x0b 0xf7 0x10
# CHECK: shrxl %esi, %ebx, %edx
0xc4 0xe2 0x0b 0xf7 0xd3
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29 19:05:25 +00:00
# CHECK: extrq $2, $3, %xmm0
0x66 0x0f 0x78 0xc0 0x03 0x02
# CHECK: extrq %xmm1, %xmm0
0x66 0x0f 0x79 0xc1
# CHECK: insertq $6, $5, %xmm1, %xmm0
0xf2 0x0f 0x78 0xc1 0x05 0x06
# CHECK: insertq %xmm1, %xmm0
0xf2 0x0f 0x79 0xc1
# CHECK: movntsd %xmm0, (%edi)
0xf2 0x0f 0x2b 0x07
# CHECK: movntss %xmm0, (%edi)
0xf3 0x0f 0x2b 0x07
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