2003-12-18 13:06:04 +00:00
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//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2003-12-18 13:06:04 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2004-01-04 23:09:24 +00:00
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// This file implements the TwoAddress instruction pass which is used
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// by most register allocators. Two-Address instructions are rewritten
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// from:
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//
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// A = B op C
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//
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// to:
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//
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// A = B
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2004-02-04 22:17:40 +00:00
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// A op= C
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2003-12-18 13:06:04 +00:00
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//
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2004-02-04 22:17:40 +00:00
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// Note that if a register allocator chooses to use this pass, that it
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// has to be capable of handling the non-SSA nature of these rewritten
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// virtual registers.
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//
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// It is also worth noting that the duplicate operand of the two
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// address instruction is removed.
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2004-01-31 21:07:15 +00:00
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//
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2003-12-18 13:06:04 +00:00
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "twoaddrinstr"
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2004-01-31 21:07:15 +00:00
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#include "llvm/CodeGen/Passes.h"
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2004-07-21 23:17:57 +00:00
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#include "llvm/Function.h"
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2003-12-18 13:06:04 +00:00
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-02-10 18:45:23 +00:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2003-12-18 13:06:04 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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2008-10-07 20:22:28 +00:00
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#include "llvm/Target/TargetOptions.h"
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2006-08-27 12:54:02 +00:00
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#include "llvm/Support/Compiler.h"
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2008-03-13 06:37:55 +00:00
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#include "llvm/Support/Debug.h"
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2008-06-18 07:49:14 +00:00
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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2009-01-05 17:59:02 +00:00
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#include "llvm/ADT/SmallSet.h"
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2004-09-01 22:55:40 +00:00
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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2003-12-18 13:06:04 +00:00
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using namespace llvm;
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2006-12-19 22:41:21 +00:00
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STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
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STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
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Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
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STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
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2006-12-19 22:41:21 +00:00
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STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
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2008-03-13 06:37:55 +00:00
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STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
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2008-06-18 07:49:14 +00:00
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STATISTIC(NumReMats, "Number of instructions re-materialized");
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2009-02-21 03:14:25 +00:00
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STATISTIC(NumDeletes, "Number of dead instructions deleted");
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2008-03-13 06:37:55 +00:00
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2006-12-19 22:41:21 +00:00
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namespace {
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2008-05-10 00:12:52 +00:00
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class VISIBILITY_HIDDEN TwoAddressInstructionPass
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: public MachineFunctionPass {
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2008-03-13 06:37:55 +00:00
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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LiveVariables *LV;
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2009-03-01 02:03:43 +00:00
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// DistanceMap - Keep track the distance of a MI from the start of the
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// current basic block.
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DenseMap<MachineInstr*, unsigned> DistanceMap;
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// SrcRegMap - A map from virtual registers to physical registers which
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// are likely targets to be coalesced to due to copies from physical
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// registers to virtual registers. e.g. v1024 = move r0.
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DenseMap<unsigned, unsigned> SrcRegMap;
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// DstRegMap - A map from virtual registers to physical registers which
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// are likely targets to be coalesced to due to copies to physical
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// registers from virtual registers. e.g. r1 = move v1024.
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DenseMap<unsigned, unsigned> DstRegMap;
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2008-05-10 00:12:52 +00:00
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bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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2008-06-18 07:49:14 +00:00
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bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
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2008-06-25 01:16:38 +00:00
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MachineInstr *MI, MachineInstr *DefMI,
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2009-03-01 02:03:43 +00:00
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MachineBasicBlock *MBB, unsigned Loc);
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2009-01-23 23:27:33 +00:00
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Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
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bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
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unsigned &LastDef);
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2009-04-28 02:12:36 +00:00
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MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
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unsigned Dist);
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Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
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bool isProfitableToCommute(unsigned regB, unsigned regC,
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MachineInstr *MI, MachineBasicBlock *MBB,
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2009-03-01 02:03:43 +00:00
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unsigned Dist);
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Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
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2009-01-23 23:27:33 +00:00
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bool CommuteInstruction(MachineBasicBlock::iterator &mi,
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MachineFunction::iterator &mbbi,
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2009-03-01 02:03:43 +00:00
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unsigned RegB, unsigned RegC, unsigned Dist);
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2009-03-30 21:34:07 +00:00
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bool isProfitableToConv3Addr(unsigned RegA);
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bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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MachineFunction::iterator &mbbi,
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unsigned RegB, unsigned Dist);
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2009-03-01 02:03:43 +00:00
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void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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2009-08-07 00:28:58 +00:00
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2008-03-13 06:37:55 +00:00
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public:
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2007-05-06 13:37:16 +00:00
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static char ID; // Pass identification, replacement for typeid
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2008-09-04 17:05:41 +00:00
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TwoAddressInstructionPass() : MachineFunctionPass(&ID) {}
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2007-05-01 21:15:47 +00:00
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2008-05-10 00:12:52 +00:00
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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2009-07-31 23:37:33 +00:00
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AU.setPreservesCFG();
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2008-05-10 00:12:52 +00:00
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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2008-10-07 20:22:28 +00:00
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if (StrongPHIElim)
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AU.addPreservedID(StrongPHIEliminationID);
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else
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AU.addPreservedID(PHIEliminationID);
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2008-05-10 00:12:52 +00:00
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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2003-12-18 22:40:24 +00:00
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2008-05-10 00:12:52 +00:00
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/// runOnMachineFunction - Pass entry point.
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2004-07-22 15:26:23 +00:00
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bool runOnMachineFunction(MachineFunction&);
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};
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2006-05-24 17:04:05 +00:00
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}
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2003-12-18 13:06:04 +00:00
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2008-05-13 00:00:25 +00:00
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char TwoAddressInstructionPass::ID = 0;
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static RegisterPass<TwoAddressInstructionPass>
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X("twoaddressinstruction", "Two-Address instruction pass");
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2008-05-13 02:05:11 +00:00
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const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
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2003-12-18 22:40:24 +00:00
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2008-03-13 06:37:55 +00:00
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/// Sink3AddrInstruction - A two-address instruction has been converted to a
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/// three-address instruction to avoid clobbering a register. Try to sink it
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2008-05-10 00:12:52 +00:00
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/// past the instruction that would kill the above mentioned register to reduce
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/// register pressure.
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2008-03-13 06:37:55 +00:00
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bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
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MachineInstr *MI, unsigned SavedReg,
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MachineBasicBlock::iterator OldPos) {
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// Check if it's safe to move this instruction.
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bool SeenStore = true; // Be conservative.
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if (!MI->isSafeToMove(TII, SeenStore))
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return false;
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unsigned DefReg = 0;
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SmallSet<unsigned, 4> UseRegs;
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2008-05-10 00:12:52 +00:00
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2008-03-13 06:37:55 +00:00
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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2008-10-03 15:45:36 +00:00
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if (!MO.isReg())
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2008-03-13 06:37:55 +00:00
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (MO.isUse() && MOReg != SavedReg)
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UseRegs.insert(MO.getReg());
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if (!MO.isDef())
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continue;
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if (MO.isImplicit())
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// Don't try to move it if it implicitly defines a register.
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return false;
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if (DefReg)
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// For now, don't move any instructions that define multiple registers.
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return false;
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DefReg = MO.getReg();
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}
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// Find the instruction that kills SavedReg.
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MachineInstr *KillMI = NULL;
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
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UE = MRI->use_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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if (!UseMO.isKill())
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continue;
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KillMI = UseMO.getParent();
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break;
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}
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2008-05-10 00:12:52 +00:00
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Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 00:15:30 +00:00
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if (!KillMI || KillMI->getParent() != MBB || KillMI == MI)
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2008-03-13 06:37:55 +00:00
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return false;
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2008-05-10 00:12:52 +00:00
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// If any of the definitions are used by another instruction between the
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// position and the kill use, then it's not safe to sink it.
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//
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// FIXME: This can be sped up if there is an easy way to query whether an
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2008-06-18 07:49:14 +00:00
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// instruction is before or after another instruction. Then we can use
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2008-05-10 00:12:52 +00:00
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// MachineRegisterInfo def / use instead.
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2008-03-13 06:37:55 +00:00
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MachineOperand *KillMO = NULL;
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MachineBasicBlock::iterator KillPos = KillMI;
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++KillPos;
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2008-05-10 00:12:52 +00:00
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2008-06-18 07:49:14 +00:00
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unsigned NumVisited = 0;
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2008-03-13 06:37:55 +00:00
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for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) {
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MachineInstr *OtherMI = I;
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2008-06-18 07:49:14 +00:00
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if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
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return false;
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++NumVisited;
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2008-03-13 06:37:55 +00:00
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for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = OtherMI->getOperand(i);
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2008-10-03 15:45:36 +00:00
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if (!MO.isReg())
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2008-03-13 06:37:55 +00:00
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continue;
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|
unsigned MOReg = MO.getReg();
|
|
|
|
if (!MOReg)
|
|
|
|
continue;
|
|
|
|
if (DefReg == MOReg)
|
|
|
|
return false;
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2008-03-13 06:37:55 +00:00
|
|
|
if (MO.isKill()) {
|
|
|
|
if (OtherMI == KillMI && MOReg == SavedReg)
|
2008-06-18 07:49:14 +00:00
|
|
|
// Save the operand that kills the register. We want to unset the kill
|
|
|
|
// marker if we can sink MI past it.
|
2008-03-13 06:37:55 +00:00
|
|
|
KillMO = &MO;
|
|
|
|
else if (UseRegs.count(MOReg))
|
|
|
|
// One of the uses is killed before the destination.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update kill and LV information.
|
|
|
|
KillMO->setIsKill(false);
|
|
|
|
KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
|
|
|
|
KillMO->setIsKill(true);
|
2008-07-02 21:28:58 +00:00
|
|
|
|
2008-07-03 09:09:37 +00:00
|
|
|
if (LV)
|
|
|
|
LV->replaceKillInstruction(SavedReg, KillMI, MI);
|
2008-03-13 06:37:55 +00:00
|
|
|
|
|
|
|
// Move instruction to its destination.
|
|
|
|
MBB->remove(MI);
|
|
|
|
MBB->insert(KillPos, MI);
|
|
|
|
|
|
|
|
++Num3AddrSunk;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2008-06-18 07:49:14 +00:00
|
|
|
/// isTwoAddrUse - Return true if the specified MI is using the specified
|
|
|
|
/// register as a two-address operand.
|
|
|
|
static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
|
|
|
|
const TargetInstrDesc &TID = UseMI->getDesc();
|
|
|
|
for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = UseMI->getOperand(i);
|
2008-10-03 15:45:36 +00:00
|
|
|
if (MO.isReg() && MO.getReg() == Reg &&
|
2009-03-19 20:30:06 +00:00
|
|
|
(MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
|
2008-06-18 07:49:14 +00:00
|
|
|
// Earlier use is a two-address one.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isProfitableToReMat - Return true if the heuristics determines it is likely
|
|
|
|
/// to be profitable to re-materialize the definition of Reg rather than copy
|
|
|
|
/// the register.
|
|
|
|
bool
|
|
|
|
TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
|
2009-03-01 02:03:43 +00:00
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
MachineInstr *MI, MachineInstr *DefMI,
|
|
|
|
MachineBasicBlock *MBB, unsigned Loc) {
|
2008-06-18 07:49:14 +00:00
|
|
|
bool OtherUse = false;
|
|
|
|
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
|
|
|
|
UE = MRI->use_end(); UI != UE; ++UI) {
|
|
|
|
MachineOperand &UseMO = UI.getOperand();
|
|
|
|
MachineInstr *UseMI = UseMO.getParent();
|
2008-06-25 01:16:38 +00:00
|
|
|
MachineBasicBlock *UseMBB = UseMI->getParent();
|
|
|
|
if (UseMBB == MBB) {
|
|
|
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
|
|
|
|
if (DI != DistanceMap.end() && DI->second == Loc)
|
|
|
|
continue; // Current use.
|
|
|
|
OtherUse = true;
|
|
|
|
// There is at least one other use in the MBB that will clobber the
|
|
|
|
// register.
|
|
|
|
if (isTwoAddrUse(UseMI, Reg))
|
|
|
|
return true;
|
|
|
|
}
|
2008-06-18 07:49:14 +00:00
|
|
|
}
|
2008-06-25 01:16:38 +00:00
|
|
|
|
|
|
|
// If other uses in MBB are not two-address uses, then don't remat.
|
|
|
|
if (OtherUse)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// No other uses in the same block, remat if it's defined in the same
|
|
|
|
// block so it does not unnecessarily extend the live range.
|
|
|
|
return MBB == DefMI->getParent();
|
2008-06-18 07:49:14 +00:00
|
|
|
}
|
|
|
|
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
/// NoUseAfterLastDef - Return true if there are no intervening uses between the
|
|
|
|
/// last instruction in the MBB that defines the specified register and the
|
|
|
|
/// two-address instruction which is being processed. It also returns the last
|
|
|
|
/// def location by reference
|
|
|
|
bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
|
2009-03-01 02:03:43 +00:00
|
|
|
MachineBasicBlock *MBB, unsigned Dist,
|
|
|
|
unsigned &LastDef) {
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
LastDef = 0;
|
|
|
|
unsigned LastUse = Dist;
|
|
|
|
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
|
|
|
|
E = MRI->reg_end(); I != E; ++I) {
|
|
|
|
MachineOperand &MO = I.getOperand();
|
|
|
|
MachineInstr *MI = MO.getParent();
|
|
|
|
if (MI->getParent() != MBB)
|
|
|
|
continue;
|
|
|
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
|
|
|
|
if (DI == DistanceMap.end())
|
|
|
|
continue;
|
|
|
|
if (MO.isUse() && DI->second < LastUse)
|
|
|
|
LastUse = DI->second;
|
|
|
|
if (MO.isDef() && DI->second > LastDef)
|
|
|
|
LastDef = DI->second;
|
|
|
|
}
|
|
|
|
|
|
|
|
return !(LastUse > LastDef && LastUse < Dist);
|
|
|
|
}
|
|
|
|
|
2009-04-28 02:12:36 +00:00
|
|
|
MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
|
|
|
|
MachineBasicBlock *MBB,
|
|
|
|
unsigned Dist) {
|
2009-05-14 04:26:30 +00:00
|
|
|
unsigned LastUseDist = 0;
|
2009-04-28 02:12:36 +00:00
|
|
|
MachineInstr *LastUse = 0;
|
|
|
|
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
|
|
|
|
E = MRI->reg_end(); I != E; ++I) {
|
|
|
|
MachineOperand &MO = I.getOperand();
|
|
|
|
MachineInstr *MI = MO.getParent();
|
|
|
|
if (MI->getParent() != MBB)
|
|
|
|
continue;
|
|
|
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
|
|
|
|
if (DI == DistanceMap.end())
|
|
|
|
continue;
|
2009-05-14 04:26:30 +00:00
|
|
|
if (DI->second >= Dist)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (MO.isUse() && DI->second > LastUseDist) {
|
2009-04-28 02:12:36 +00:00
|
|
|
LastUse = DI->first;
|
|
|
|
LastUseDist = DI->second;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return LastUse;
|
|
|
|
}
|
|
|
|
|
2009-03-01 02:03:43 +00:00
|
|
|
/// isCopyToReg - Return true if the specified MI is a copy instruction or
|
|
|
|
/// a extract_subreg instruction. It also returns the source and destination
|
|
|
|
/// registers and whether they are physical registers by reference.
|
|
|
|
static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
|
|
|
|
unsigned &SrcReg, unsigned &DstReg,
|
|
|
|
bool &IsSrcPhys, bool &IsDstPhys) {
|
|
|
|
SrcReg = 0;
|
|
|
|
DstReg = 0;
|
|
|
|
unsigned SrcSubIdx, DstSubIdx;
|
|
|
|
if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
|
|
|
|
if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
|
|
|
|
DstReg = MI.getOperand(0).getReg();
|
|
|
|
SrcReg = MI.getOperand(1).getReg();
|
|
|
|
} else if (MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
|
|
|
|
DstReg = MI.getOperand(0).getReg();
|
|
|
|
SrcReg = MI.getOperand(2).getReg();
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 00:15:30 +00:00
|
|
|
} else if (MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
|
|
|
|
DstReg = MI.getOperand(0).getReg();
|
|
|
|
SrcReg = MI.getOperand(2).getReg();
|
2009-03-01 02:03:43 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (DstReg) {
|
|
|
|
IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
|
|
|
|
IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 00:15:30 +00:00
|
|
|
/// isKilled - Test if the given register value, which is used by the given
|
|
|
|
/// instruction, is killed by the given instruction. This looks through
|
|
|
|
/// coalescable copies to see if the original value is potentially not killed.
|
|
|
|
///
|
|
|
|
/// For example, in this code:
|
|
|
|
///
|
|
|
|
/// %reg1034 = copy %reg1024
|
|
|
|
/// %reg1035 = copy %reg1025<kill>
|
|
|
|
/// %reg1036 = add %reg1034<kill>, %reg1035<kill>
|
|
|
|
///
|
|
|
|
/// %reg1034 is not considered to be killed, since it is copied from a
|
|
|
|
/// register which is not killed. Treating it as not killed lets the
|
|
|
|
/// normal heuristics commute the (two-address) add, which lets
|
|
|
|
/// coalescing eliminate the extra copy.
|
|
|
|
///
|
|
|
|
static bool isKilled(MachineInstr &MI, unsigned Reg,
|
|
|
|
const MachineRegisterInfo *MRI,
|
|
|
|
const TargetInstrInfo *TII) {
|
|
|
|
MachineInstr *DefMI = &MI;
|
|
|
|
for (;;) {
|
|
|
|
if (!DefMI->killsRegister(Reg))
|
|
|
|
return false;
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
|
|
return true;
|
|
|
|
MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
|
|
|
|
// If there are multiple defs, we can't do a simple analysis, so just
|
|
|
|
// go with what the kill flag says.
|
|
|
|
if (next(Begin) != MRI->def_end())
|
|
|
|
return true;
|
|
|
|
DefMI = &*Begin;
|
|
|
|
bool IsSrcPhys, IsDstPhys;
|
|
|
|
unsigned SrcReg, DstReg;
|
|
|
|
// If the def is something other than a copy, then it isn't going to
|
|
|
|
// be coalesced, so follow the kill flag.
|
|
|
|
if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
|
|
|
|
return true;
|
|
|
|
Reg = SrcReg;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-03-01 02:03:43 +00:00
|
|
|
/// isTwoAddrUse - Return true if the specified MI uses the specified register
|
|
|
|
/// as a two-address use. If so, return the destination register by reference.
|
|
|
|
static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
|
|
|
|
const TargetInstrDesc &TID = MI.getDesc();
|
2009-03-30 21:34:07 +00:00
|
|
|
unsigned NumOps = (MI.getOpcode() == TargetInstrInfo::INLINEASM)
|
|
|
|
? MI.getNumOperands() : TID.getNumOperands();
|
|
|
|
for (unsigned i = 0; i != NumOps; ++i) {
|
2009-03-01 02:03:43 +00:00
|
|
|
const MachineOperand &MO = MI.getOperand(i);
|
|
|
|
if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
|
|
|
|
continue;
|
2009-03-19 20:30:06 +00:00
|
|
|
unsigned ti;
|
|
|
|
if (MI.isRegTiedToDefOperand(i, &ti)) {
|
2009-03-01 02:03:43 +00:00
|
|
|
DstReg = MI.getOperand(ti).getReg();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// findOnlyInterestingUse - Given a register, if has a single in-basic block
|
|
|
|
/// use, return the use instruction if it's a copy or a two-address use.
|
|
|
|
static
|
|
|
|
MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
|
|
|
|
MachineRegisterInfo *MRI,
|
|
|
|
const TargetInstrInfo *TII,
|
2009-04-14 00:32:25 +00:00
|
|
|
bool &IsCopy,
|
2009-03-01 02:03:43 +00:00
|
|
|
unsigned &DstReg, bool &IsDstPhys) {
|
|
|
|
MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg);
|
|
|
|
if (UI == MRI->use_end())
|
|
|
|
return 0;
|
|
|
|
MachineInstr &UseMI = *UI;
|
|
|
|
if (++UI != MRI->use_end())
|
|
|
|
// More than one use.
|
|
|
|
return 0;
|
|
|
|
if (UseMI.getParent() != MBB)
|
|
|
|
return 0;
|
|
|
|
unsigned SrcReg;
|
|
|
|
bool IsSrcPhys;
|
2009-04-14 00:32:25 +00:00
|
|
|
if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
|
|
|
|
IsCopy = true;
|
2009-03-01 02:03:43 +00:00
|
|
|
return &UseMI;
|
2009-04-14 00:32:25 +00:00
|
|
|
}
|
2009-03-01 02:03:43 +00:00
|
|
|
IsDstPhys = false;
|
2009-04-14 00:32:25 +00:00
|
|
|
if (isTwoAddrUse(UseMI, Reg, DstReg)) {
|
|
|
|
IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
|
2009-03-01 02:03:43 +00:00
|
|
|
return &UseMI;
|
2009-04-14 00:32:25 +00:00
|
|
|
}
|
2009-03-01 02:03:43 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// getMappedReg - Return the physical register the specified virtual register
|
|
|
|
/// might be mapped to.
|
|
|
|
static unsigned
|
|
|
|
getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
|
|
|
|
while (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
|
|
DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
|
|
|
|
if (SI == RegMap.end())
|
|
|
|
return 0;
|
|
|
|
Reg = SI->second;
|
|
|
|
}
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
|
|
return Reg;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// regsAreCompatible - Return true if the two registers are equal or aliased.
|
|
|
|
///
|
|
|
|
static bool
|
|
|
|
regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
|
|
|
|
if (RegA == RegB)
|
|
|
|
return true;
|
|
|
|
if (!RegA || !RegB)
|
|
|
|
return false;
|
|
|
|
return TRI->regsOverlap(RegA, RegB);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
/// isProfitableToReMat - Return true if it's potentially profitable to commute
|
|
|
|
/// the two-address instruction that's being processed.
|
|
|
|
bool
|
|
|
|
TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
|
2009-03-01 02:03:43 +00:00
|
|
|
MachineInstr *MI, MachineBasicBlock *MBB,
|
|
|
|
unsigned Dist) {
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
// Determine if it's profitable to commute this two address instruction. In
|
|
|
|
// general, we want no uses between this instruction and the definition of
|
|
|
|
// the two-address register.
|
|
|
|
// e.g.
|
|
|
|
// %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
|
|
|
|
// %reg1029<def> = MOV8rr %reg1028
|
|
|
|
// %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
|
|
|
|
// insert => %reg1030<def> = MOV8rr %reg1028
|
|
|
|
// %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
|
|
|
|
// In this case, it might not be possible to coalesce the second MOV8rr
|
|
|
|
// instruction if the first one is coalesced. So it would be profitable to
|
|
|
|
// commute it:
|
|
|
|
// %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
|
|
|
|
// %reg1029<def> = MOV8rr %reg1028
|
|
|
|
// %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
|
|
|
|
// insert => %reg1030<def> = MOV8rr %reg1029
|
|
|
|
// %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
|
|
|
|
|
|
|
|
if (!MI->killsRegister(regC))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Ok, we have something like:
|
|
|
|
// %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
|
|
|
|
// let's see if it's worth commuting it.
|
|
|
|
|
2009-03-01 02:03:43 +00:00
|
|
|
// Look for situations like this:
|
|
|
|
// %reg1024<def> = MOV r1
|
|
|
|
// %reg1025<def> = MOV r0
|
|
|
|
// %reg1026<def> = ADD %reg1024, %reg1025
|
|
|
|
// r0 = MOV %reg1026
|
|
|
|
// Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
|
|
|
|
unsigned FromRegB = getMappedReg(regB, SrcRegMap);
|
|
|
|
unsigned FromRegC = getMappedReg(regC, SrcRegMap);
|
|
|
|
unsigned ToRegB = getMappedReg(regB, DstRegMap);
|
|
|
|
unsigned ToRegC = getMappedReg(regC, DstRegMap);
|
|
|
|
if (!regsAreCompatible(FromRegB, ToRegB, TRI) &&
|
|
|
|
(regsAreCompatible(FromRegB, ToRegC, TRI) ||
|
|
|
|
regsAreCompatible(FromRegC, ToRegB, TRI)))
|
|
|
|
return true;
|
|
|
|
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
// If there is a use of regC between its last def (could be livein) and this
|
|
|
|
// instruction, then bail.
|
|
|
|
unsigned LastDefC = 0;
|
2009-03-01 02:03:43 +00:00
|
|
|
if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// If there is a use of regB between its last def (could be livein) and this
|
|
|
|
// instruction, then go ahead and make this transformation.
|
|
|
|
unsigned LastDefB = 0;
|
2009-03-01 02:03:43 +00:00
|
|
|
if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
return true;
|
|
|
|
|
|
|
|
// Since there are no intervening uses for both registers, then commute
|
|
|
|
// if the def of regC is closer. Its live interval is shorter.
|
|
|
|
return LastDefB && LastDefC && LastDefC > LastDefB;
|
|
|
|
}
|
|
|
|
|
2009-01-23 23:27:33 +00:00
|
|
|
/// CommuteInstruction - Commute a two-address instruction and update the basic
|
|
|
|
/// block, distance map, and live variables if needed. Return true if it is
|
|
|
|
/// successful.
|
|
|
|
bool
|
|
|
|
TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
|
2009-03-01 02:03:43 +00:00
|
|
|
MachineFunction::iterator &mbbi,
|
|
|
|
unsigned RegB, unsigned RegC, unsigned Dist) {
|
2009-01-23 23:27:33 +00:00
|
|
|
MachineInstr *MI = mi;
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << "2addr: COMMUTING : " << *MI);
|
2009-01-23 23:27:33 +00:00
|
|
|
MachineInstr *NewMI = TII->commuteInstruction(MI);
|
|
|
|
|
|
|
|
if (NewMI == 0) {
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << "2addr: COMMUTING FAILED!\n");
|
2009-01-23 23:27:33 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << "2addr: COMMUTED TO: " << *NewMI);
|
2009-01-23 23:27:33 +00:00
|
|
|
// If the instruction changed to commute it, update livevar.
|
|
|
|
if (NewMI != MI) {
|
|
|
|
if (LV)
|
|
|
|
// Update live variables
|
|
|
|
LV->replaceKillInstruction(RegC, MI, NewMI);
|
|
|
|
|
|
|
|
mbbi->insert(mi, NewMI); // Insert the new inst
|
|
|
|
mbbi->erase(mi); // Nuke the old inst.
|
|
|
|
mi = NewMI;
|
|
|
|
DistanceMap.insert(std::make_pair(NewMI, Dist));
|
|
|
|
}
|
2009-03-01 02:03:43 +00:00
|
|
|
|
|
|
|
// Update source register map.
|
|
|
|
unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
|
|
|
|
if (FromRegC) {
|
|
|
|
unsigned RegA = MI->getOperand(0).getReg();
|
|
|
|
SrcRegMap[RegA] = FromRegC;
|
|
|
|
}
|
|
|
|
|
2009-01-23 23:27:33 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-03-30 21:34:07 +00:00
|
|
|
/// isProfitableToConv3Addr - Return true if it is profitable to convert the
|
|
|
|
/// given 2-address instruction to a 3-address one.
|
|
|
|
bool
|
|
|
|
TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) {
|
|
|
|
// Look for situations like this:
|
|
|
|
// %reg1024<def> = MOV r1
|
|
|
|
// %reg1025<def> = MOV r0
|
|
|
|
// %reg1026<def> = ADD %reg1024, %reg1025
|
|
|
|
// r2 = MOV %reg1026
|
|
|
|
// Turn ADD into a 3-address instruction to avoid a copy.
|
|
|
|
unsigned FromRegA = getMappedReg(RegA, SrcRegMap);
|
|
|
|
unsigned ToRegA = getMappedReg(RegA, DstRegMap);
|
|
|
|
return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI));
|
|
|
|
}
|
|
|
|
|
|
|
|
/// ConvertInstTo3Addr - Convert the specified two-address instruction into a
|
|
|
|
/// three address one. Return true if this transformation was successful.
|
|
|
|
bool
|
|
|
|
TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
|
|
|
|
MachineBasicBlock::iterator &nmi,
|
|
|
|
MachineFunction::iterator &mbbi,
|
|
|
|
unsigned RegB, unsigned Dist) {
|
|
|
|
MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
|
|
|
|
if (NewMI) {
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << "2addr: CONVERTING 2-ADDR: " << *mi);
|
|
|
|
DEBUG(errs() << "2addr: TO 3-ADDR: " << *NewMI);
|
2009-03-30 21:34:07 +00:00
|
|
|
bool Sunk = false;
|
|
|
|
|
|
|
|
if (NewMI->findRegisterUseOperand(RegB, false, TRI))
|
|
|
|
// FIXME: Temporary workaround. If the new instruction doesn't
|
|
|
|
// uses RegB, convertToThreeAddress must have created more
|
|
|
|
// then one instruction.
|
|
|
|
Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
|
|
|
|
|
|
|
|
mbbi->erase(mi); // Nuke the old inst.
|
|
|
|
|
|
|
|
if (!Sunk) {
|
|
|
|
DistanceMap.insert(std::make_pair(NewMI, Dist));
|
|
|
|
mi = NewMI;
|
|
|
|
nmi = next(mi);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-03-01 02:03:43 +00:00
|
|
|
/// ProcessCopy - If the specified instruction is not yet processed, process it
|
|
|
|
/// if it's a copy. For a copy instruction, we find the physical registers the
|
|
|
|
/// source and destination registers might be mapped to. These are kept in
|
|
|
|
/// point-to maps used to determine future optimizations. e.g.
|
|
|
|
/// v1024 = mov r0
|
|
|
|
/// v1025 = mov r1
|
|
|
|
/// v1026 = add v1024, v1025
|
|
|
|
/// r1 = mov r1026
|
|
|
|
/// If 'add' is a two-address instruction, v1024, v1026 are both potentially
|
|
|
|
/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
|
|
|
|
/// potentially joined with r1 on the output side. It's worthwhile to commute
|
|
|
|
/// 'add' to eliminate a copy.
|
|
|
|
void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB,
|
|
|
|
SmallPtrSet<MachineInstr*, 8> &Processed) {
|
|
|
|
if (Processed.count(MI))
|
|
|
|
return;
|
|
|
|
|
|
|
|
bool IsSrcPhys, IsDstPhys;
|
|
|
|
unsigned SrcReg, DstReg;
|
|
|
|
if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (IsDstPhys && !IsSrcPhys)
|
|
|
|
DstRegMap.insert(std::make_pair(SrcReg, DstReg));
|
|
|
|
else if (!IsDstPhys && IsSrcPhys) {
|
2009-04-13 20:04:24 +00:00
|
|
|
bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
|
|
|
|
if (!isNew)
|
|
|
|
assert(SrcRegMap[DstReg] == SrcReg &&
|
|
|
|
"Can't map to two src physical registers!");
|
2009-03-01 02:03:43 +00:00
|
|
|
|
|
|
|
SmallVector<unsigned, 4> VirtRegPairs;
|
2009-04-14 00:32:25 +00:00
|
|
|
bool IsCopy = false;
|
2009-03-01 02:03:43 +00:00
|
|
|
unsigned NewReg = 0;
|
|
|
|
while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
|
2009-04-14 00:32:25 +00:00
|
|
|
IsCopy, NewReg, IsDstPhys)) {
|
|
|
|
if (IsCopy) {
|
|
|
|
if (!Processed.insert(UseMI))
|
2009-03-01 02:03:43 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
|
|
|
|
if (DI != DistanceMap.end())
|
|
|
|
// Earlier in the same MBB.Reached via a back edge.
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (IsDstPhys) {
|
|
|
|
VirtRegPairs.push_back(NewReg);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second;
|
2009-04-13 20:04:24 +00:00
|
|
|
if (!isNew)
|
2009-04-14 00:32:25 +00:00
|
|
|
assert(SrcRegMap[NewReg] == DstReg &&
|
|
|
|
"Can't map to two src physical registers!");
|
2009-03-01 02:03:43 +00:00
|
|
|
VirtRegPairs.push_back(NewReg);
|
|
|
|
DstReg = NewReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!VirtRegPairs.empty()) {
|
|
|
|
unsigned ToReg = VirtRegPairs.back();
|
|
|
|
VirtRegPairs.pop_back();
|
|
|
|
while (!VirtRegPairs.empty()) {
|
|
|
|
unsigned FromReg = VirtRegPairs.back();
|
|
|
|
VirtRegPairs.pop_back();
|
|
|
|
bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
|
2009-04-13 20:04:24 +00:00
|
|
|
if (!isNew)
|
|
|
|
assert(DstRegMap[FromReg] == ToReg &&
|
|
|
|
"Can't map to two dst physical registers!");
|
2009-03-01 02:03:43 +00:00
|
|
|
ToReg = FromReg;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Processed.insert(MI);
|
|
|
|
}
|
|
|
|
|
2009-02-21 03:14:25 +00:00
|
|
|
/// isSafeToDelete - If the specified instruction does not produce any side
|
|
|
|
/// effects and all of its defs are dead, then it's safe to delete.
|
2009-04-28 02:12:36 +00:00
|
|
|
static bool isSafeToDelete(MachineInstr *MI, unsigned Reg,
|
|
|
|
const TargetInstrInfo *TII,
|
|
|
|
SmallVector<unsigned, 4> &Kills) {
|
2009-02-21 03:14:25 +00:00
|
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
|
|
if (TID.mayStore() || TID.isCall())
|
|
|
|
return false;
|
|
|
|
if (TID.isTerminator() || TID.hasUnmodeledSideEffects())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2009-04-28 02:12:36 +00:00
|
|
|
if (!MO.isReg())
|
2009-02-21 03:14:25 +00:00
|
|
|
continue;
|
2009-04-28 02:12:36 +00:00
|
|
|
if (MO.isDef() && !MO.isDead())
|
2009-02-21 03:14:25 +00:00
|
|
|
return false;
|
2009-04-28 02:12:36 +00:00
|
|
|
if (MO.isUse() && MO.getReg() != Reg && MO.isKill())
|
|
|
|
Kills.push_back(MO.getReg());
|
2009-02-21 03:14:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2008-05-10 00:12:52 +00:00
|
|
|
/// runOnMachineFunction - Reduce two-address instructions to two operands.
|
2003-12-18 13:06:04 +00:00
|
|
|
///
|
2004-01-31 21:14:04 +00:00
|
|
|
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << "Machine Function\n");
|
2004-07-22 15:26:23 +00:00
|
|
|
const TargetMachine &TM = MF.getTarget();
|
2008-03-13 06:37:55 +00:00
|
|
|
MRI = &MF.getRegInfo();
|
|
|
|
TII = TM.getInstrInfo();
|
|
|
|
TRI = TM.getRegisterInfo();
|
2009-01-28 13:14:17 +00:00
|
|
|
LV = getAnalysisIfAvailable<LiveVariables>();
|
2004-07-22 15:26:23 +00:00
|
|
|
|
|
|
|
bool MadeChange = false;
|
|
|
|
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
|
2009-07-25 00:23:56 +00:00
|
|
|
DEBUG(errs() << "********** Function: "
|
|
|
|
<< MF.getFunction()->getName() << '\n');
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2008-06-18 07:49:14 +00:00
|
|
|
// ReMatRegs - Keep track of the registers whose def's are remat'ed.
|
|
|
|
BitVector ReMatRegs;
|
|
|
|
ReMatRegs.resize(MRI->getLastVirtReg()+1);
|
|
|
|
|
2009-03-01 02:03:43 +00:00
|
|
|
SmallPtrSet<MachineInstr*, 8> Processed;
|
2004-07-22 15:26:23 +00:00
|
|
|
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
|
|
|
|
mbbi != mbbe; ++mbbi) {
|
2008-06-18 07:49:14 +00:00
|
|
|
unsigned Dist = 0;
|
|
|
|
DistanceMap.clear();
|
2009-03-01 02:03:43 +00:00
|
|
|
SrcRegMap.clear();
|
|
|
|
DstRegMap.clear();
|
|
|
|
Processed.clear();
|
2004-07-22 15:26:23 +00:00
|
|
|
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
|
2008-03-27 01:27:25 +00:00
|
|
|
mi != me; ) {
|
|
|
|
MachineBasicBlock::iterator nmi = next(mi);
|
2008-01-07 07:27:27 +00:00
|
|
|
const TargetInstrDesc &TID = mi->getDesc();
|
2006-11-01 23:06:55 +00:00
|
|
|
bool FirstTied = true;
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2008-06-18 07:49:14 +00:00
|
|
|
DistanceMap.insert(std::make_pair(mi, ++Dist));
|
2009-03-01 02:03:43 +00:00
|
|
|
|
|
|
|
ProcessCopy(&*mi, &*mbbi, Processed);
|
|
|
|
|
2009-03-23 08:01:15 +00:00
|
|
|
unsigned NumOps = (mi->getOpcode() == TargetInstrInfo::INLINEASM)
|
|
|
|
? mi->getNumOperands() : TID.getNumOperands();
|
|
|
|
for (unsigned si = 0; si < NumOps; ++si) {
|
2009-03-19 20:30:06 +00:00
|
|
|
unsigned ti = 0;
|
|
|
|
if (!mi->isRegTiedToDefOperand(si, &ti))
|
2006-11-01 23:06:55 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
if (FirstTied) {
|
|
|
|
++NumTwoAddressInstrs;
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << '\t' << *mi);
|
2006-11-01 23:06:55 +00:00
|
|
|
}
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2006-11-01 23:06:55 +00:00
|
|
|
FirstTied = false;
|
|
|
|
|
2008-10-03 15:45:36 +00:00
|
|
|
assert(mi->getOperand(si).isReg() && mi->getOperand(si).getReg() &&
|
2006-11-01 23:06:55 +00:00
|
|
|
mi->getOperand(si).isUse() && "two address instruction invalid");
|
|
|
|
|
2008-05-10 00:12:52 +00:00
|
|
|
// If the two operands are the same we just remove the use
|
2006-11-01 23:06:55 +00:00
|
|
|
// and mark the def as def&use, otherwise we have to insert a copy.
|
|
|
|
if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
|
2008-05-10 00:12:52 +00:00
|
|
|
// Rewrite:
|
2006-11-01 23:06:55 +00:00
|
|
|
// a = b op c
|
|
|
|
// to:
|
|
|
|
// a = b
|
|
|
|
// a = a op c
|
|
|
|
unsigned regA = mi->getOperand(ti).getReg();
|
|
|
|
unsigned regB = mi->getOperand(si).getReg();
|
2009-07-16 09:20:10 +00:00
|
|
|
unsigned regASubIdx = mi->getOperand(ti).getSubReg();
|
2006-11-01 23:06:55 +00:00
|
|
|
|
2009-03-23 08:01:15 +00:00
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(regB) &&
|
2009-08-07 00:28:58 +00:00
|
|
|
"cannot make instruction into two-address form");
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2004-07-21 23:17:57 +00:00
|
|
|
#ifndef NDEBUG
|
2006-11-01 23:06:55 +00:00
|
|
|
// First, verify that we don't have a use of a in the instruction (a =
|
|
|
|
// b + a for example) because our transformation will not work. This
|
|
|
|
// should never occur because we are in SSA form.
|
|
|
|
for (unsigned i = 0; i != mi->getNumOperands(); ++i)
|
2009-03-19 20:30:06 +00:00
|
|
|
assert(i == ti ||
|
2008-10-03 15:45:36 +00:00
|
|
|
!mi->getOperand(i).isReg() ||
|
2006-11-01 23:06:55 +00:00
|
|
|
mi->getOperand(i).getReg() != regA);
|
2004-07-21 23:17:57 +00:00
|
|
|
#endif
|
2004-02-04 22:17:40 +00:00
|
|
|
|
2006-11-01 23:06:55 +00:00
|
|
|
// If this instruction is not the killing user of B, see if we can
|
|
|
|
// rearrange the code to make it so. Making it the killing user will
|
|
|
|
// allow us to coalesce A and B together, eliminating the copy we are
|
|
|
|
// about to insert.
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 00:15:30 +00:00
|
|
|
if (!isKilled(*mi, regB, MRI, TII)) {
|
2009-02-21 03:14:25 +00:00
|
|
|
// If regA is dead and the instruction can be deleted, just delete
|
|
|
|
// it so it doesn't clobber regB.
|
2009-04-28 02:12:36 +00:00
|
|
|
SmallVector<unsigned, 4> Kills;
|
|
|
|
if (mi->getOperand(ti).isDead() &&
|
|
|
|
isSafeToDelete(mi, regB, TII, Kills)) {
|
|
|
|
SmallVector<std::pair<std::pair<unsigned, bool>
|
|
|
|
,MachineInstr*>, 4> NewKills;
|
|
|
|
bool ReallySafe = true;
|
|
|
|
// If this instruction kills some virtual registers, we need
|
|
|
|
// update the kill information. If it's not possible to do so,
|
|
|
|
// then bail out.
|
|
|
|
while (!Kills.empty()) {
|
|
|
|
unsigned Kill = Kills.back();
|
|
|
|
Kills.pop_back();
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Kill)) {
|
|
|
|
ReallySafe = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
MachineInstr *LastKill = FindLastUseInMBB(Kill, &*mbbi, Dist);
|
|
|
|
if (LastKill) {
|
|
|
|
bool isModRef = LastKill->modifiesRegister(Kill);
|
|
|
|
NewKills.push_back(std::make_pair(std::make_pair(Kill,isModRef),
|
|
|
|
LastKill));
|
|
|
|
} else {
|
|
|
|
ReallySafe = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ReallySafe) {
|
|
|
|
if (LV) {
|
|
|
|
while (!NewKills.empty()) {
|
|
|
|
MachineInstr *NewKill = NewKills.back().second;
|
|
|
|
unsigned Kill = NewKills.back().first.first;
|
|
|
|
bool isDead = NewKills.back().first.second;
|
|
|
|
NewKills.pop_back();
|
|
|
|
if (LV->removeVirtualRegisterKilled(Kill, mi)) {
|
|
|
|
if (isDead)
|
|
|
|
LV->addVirtualRegisterDead(Kill, NewKill);
|
|
|
|
else
|
|
|
|
LV->addVirtualRegisterKilled(Kill, NewKill);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2009-05-13 04:18:47 +00:00
|
|
|
|
|
|
|
// We're really going to nuke the old inst. If regB was marked
|
|
|
|
// as a kill we need to update its Kills list.
|
|
|
|
if (mi->getOperand(si).isKill())
|
|
|
|
LV->removeVirtualRegisterKilled(regB, mi);
|
|
|
|
|
2009-04-28 02:12:36 +00:00
|
|
|
mbbi->erase(mi); // Nuke the old inst.
|
|
|
|
mi = nmi;
|
|
|
|
++NumDeletes;
|
|
|
|
break; // Done with this instruction.
|
|
|
|
}
|
2009-02-21 03:14:25 +00:00
|
|
|
}
|
|
|
|
|
2006-11-01 23:06:55 +00:00
|
|
|
// If this instruction is commutative, check to see if C dies. If
|
|
|
|
// so, swap the B and C operands. This makes the live ranges of A
|
|
|
|
// and C joinable.
|
|
|
|
// FIXME: This code also works for A := B op C instructions.
|
2009-07-20 21:16:08 +00:00
|
|
|
unsigned SrcOp1, SrcOp2;
|
|
|
|
if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
|
|
|
|
TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
|
|
|
|
unsigned regC = 0;
|
|
|
|
if (si == SrcOp1)
|
|
|
|
regC = mi->getOperand(SrcOp2).getReg();
|
|
|
|
else if (si == SrcOp2)
|
|
|
|
regC = mi->getOperand(SrcOp1).getReg();
|
Implement support for using modeling implicit-zero-extension on x86-64
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08 00:15:30 +00:00
|
|
|
if (isKilled(*mi, regC, MRI, TII)) {
|
2009-03-01 02:03:43 +00:00
|
|
|
if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
|
2006-11-01 23:06:55 +00:00
|
|
|
++NumCommuted;
|
|
|
|
regB = regC;
|
|
|
|
goto InstructionRearranged;
|
2005-04-21 22:36:52 +00:00
|
|
|
}
|
2005-01-19 07:08:42 +00:00
|
|
|
}
|
Make the 2-address instruction lowering pass smarter in two ways:
1. If we are two-addressing a commutable instruction and the LHS is not the
last use of the variable, see if the instruction is the last use of the
RHS. If so, commute the instruction, allowing us to avoid a
register-register copy in many cases for common instructions like ADD, OR,
AND, etc on X86.
2. If #1 doesn't hold, and if this is an instruction that also existing in
3-address form, promote the instruction to a 3-address instruction to
avoid the register-register copy. We can do this for several common
instructions in X86, including ADDrr, INC, DEC, etc.
This patch implements test/Regression/CodeGen/X86/commute-two-addr.ll,
overlap-add.ll, and overlap-shift.ll when I check in the X86 support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19245 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-02 02:34:12 +00:00
|
|
|
}
|
2006-11-01 23:06:55 +00:00
|
|
|
|
|
|
|
// If this instruction is potentially convertible to a true
|
|
|
|
// three-address instruction,
|
2008-01-07 07:27:27 +00:00
|
|
|
if (TID.isConvertibleTo3Addr()) {
|
2006-11-01 23:06:55 +00:00
|
|
|
// FIXME: This assumes there are no more operands which are tied
|
|
|
|
// to another register.
|
|
|
|
#ifndef NDEBUG
|
2008-05-10 00:12:52 +00:00
|
|
|
for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i)
|
2008-01-07 07:27:27 +00:00
|
|
|
assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
|
2006-11-01 23:06:55 +00:00
|
|
|
#endif
|
|
|
|
|
2009-03-30 21:34:07 +00:00
|
|
|
if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
|
2006-11-01 23:06:55 +00:00
|
|
|
++NumConvertedTo3Addr;
|
2008-05-10 00:12:52 +00:00
|
|
|
break; // Done with this instruction.
|
2006-11-01 23:06:55 +00:00
|
|
|
}
|
2007-10-20 04:01:47 +00:00
|
|
|
}
|
Make the 2-address instruction lowering pass smarter in two ways:
1. If we are two-addressing a commutable instruction and the LHS is not the
last use of the variable, see if the instruction is the last use of the
RHS. If so, commute the instruction, allowing us to avoid a
register-register copy in many cases for common instructions like ADD, OR,
AND, etc on X86.
2. If #1 doesn't hold, and if this is an instruction that also existing in
3-address form, promote the instruction to a 3-address instruction to
avoid the register-register copy. We can do this for several common
instructions in X86, including ADDrr, INC, DEC, etc.
This patch implements test/Regression/CodeGen/X86/commute-two-addr.ll,
overlap-add.ll, and overlap-shift.ll when I check in the X86 support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19245 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-02 02:34:12 +00:00
|
|
|
}
|
2004-07-22 15:26:23 +00:00
|
|
|
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
// If it's profitable to commute the instruction, do so.
|
2009-07-11 00:04:23 +00:00
|
|
|
unsigned SrcOp1, SrcOp2;
|
|
|
|
if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
|
|
|
|
TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
|
|
|
|
unsigned regC = 0;
|
|
|
|
if (si == SrcOp1)
|
|
|
|
regC = mi->getOperand(SrcOp2).getReg();
|
|
|
|
else if (si == SrcOp2)
|
|
|
|
regC = mi->getOperand(SrcOp1).getReg();
|
|
|
|
|
|
|
|
if (regC && isProfitableToCommute(regB, regC, mi, mbbi, Dist))
|
2009-03-01 02:03:43 +00:00
|
|
|
if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
++NumAggrCommuted;
|
|
|
|
++NumCommuted;
|
|
|
|
regB = regC;
|
2009-03-30 21:34:07 +00:00
|
|
|
goto InstructionRearranged;
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-03-30 21:34:07 +00:00
|
|
|
// If it's profitable to convert the 2-address instruction to a
|
|
|
|
// 3-address one, do so.
|
|
|
|
if (TID.isConvertibleTo3Addr() && isProfitableToConv3Addr(regA)) {
|
|
|
|
if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
|
|
|
|
++NumConvertedTo3Addr;
|
|
|
|
break; // Done with this instruction.
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-11-01 23:06:55 +00:00
|
|
|
InstructionRearranged:
|
2009-03-23 08:01:15 +00:00
|
|
|
const TargetRegisterClass* rc = MRI->getRegClass(regB);
|
2008-06-18 07:49:14 +00:00
|
|
|
MachineInstr *DefMI = MRI->getVRegDef(regB);
|
|
|
|
// If it's safe and profitable, remat the definition instead of
|
|
|
|
// copying it.
|
2008-06-25 01:16:38 +00:00
|
|
|
if (DefMI &&
|
2008-08-27 20:58:54 +00:00
|
|
|
DefMI->getDesc().isAsCheapAsAMove() &&
|
2008-08-27 20:33:50 +00:00
|
|
|
DefMI->isSafeToReMat(TII, regB) &&
|
2009-03-01 02:03:43 +00:00
|
|
|
isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << "2addr: REMATTING : " << *DefMI << "\n");
|
2009-07-16 09:20:10 +00:00
|
|
|
TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI);
|
2008-06-18 07:49:14 +00:00
|
|
|
ReMatRegs.set(regB);
|
|
|
|
++NumReMats;
|
A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
|
|
|
} else {
|
2009-04-13 15:16:56 +00:00
|
|
|
bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
|
2009-05-08 22:53:06 +00:00
|
|
|
(void)Emitted;
|
2009-04-13 15:16:56 +00:00
|
|
|
assert(Emitted && "Unable to issue a copy instruction!\n");
|
A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
|
|
|
}
|
2006-11-01 23:06:55 +00:00
|
|
|
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
MachineBasicBlock::iterator prevMI = prior(mi);
|
|
|
|
// Update DistanceMap.
|
|
|
|
DistanceMap.insert(std::make_pair(prevMI, Dist));
|
|
|
|
DistanceMap[mi] = ++Dist;
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2008-05-10 00:12:52 +00:00
|
|
|
// Update live variables for regB.
|
2008-07-02 21:28:58 +00:00
|
|
|
if (LV) {
|
2008-07-03 09:09:37 +00:00
|
|
|
if (LV->removeVirtualRegisterKilled(regB, mi))
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
LV->addVirtualRegisterKilled(regB, prevMI);
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2008-07-03 09:09:37 +00:00
|
|
|
if (LV->removeVirtualRegisterDead(regB, mi))
|
Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1028
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
In this case, it might not be possible to coalesce the second MOV8rr
instruction if the first one is coalesced. So it would be profitable to
commute it:
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
%reg1029<def> = MOV8rr %reg1028
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
insert => %reg1030<def> = MOV8rr %reg1029
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-25 03:53:59 +00:00
|
|
|
LV->addVirtualRegisterDead(regB, prevMI);
|
2008-07-02 21:28:58 +00:00
|
|
|
}
|
2008-11-12 17:15:19 +00:00
|
|
|
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << "\t\tprepend:\t" << *prevMI);
|
2008-07-02 21:28:58 +00:00
|
|
|
|
2008-05-10 00:12:52 +00:00
|
|
|
// Replace all occurences of regB with regA.
|
2006-11-01 23:06:55 +00:00
|
|
|
for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
|
2008-10-03 15:45:36 +00:00
|
|
|
if (mi->getOperand(i).isReg() &&
|
2006-11-01 23:06:55 +00:00
|
|
|
mi->getOperand(i).getReg() == regB)
|
|
|
|
mi->getOperand(i).setReg(regA);
|
|
|
|
}
|
2004-07-22 15:26:23 +00:00
|
|
|
}
|
|
|
|
|
2006-11-01 23:06:55 +00:00
|
|
|
assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
|
|
|
|
mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
|
|
|
|
MadeChange = true;
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2009-08-23 03:20:44 +00:00
|
|
|
DEBUG(errs() << "\t\trewrite to:\t" << *mi);
|
2006-11-01 23:06:55 +00:00
|
|
|
}
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2008-03-27 01:27:25 +00:00
|
|
|
mi = nmi;
|
2003-12-18 13:06:04 +00:00
|
|
|
}
|
2004-07-22 15:26:23 +00:00
|
|
|
}
|
2003-12-18 13:06:04 +00:00
|
|
|
|
2008-06-25 01:16:38 +00:00
|
|
|
// Some remat'ed instructions are dead.
|
|
|
|
int VReg = ReMatRegs.find_first();
|
|
|
|
while (VReg != -1) {
|
|
|
|
if (MRI->use_empty(VReg)) {
|
|
|
|
MachineInstr *DefMI = MRI->getVRegDef(VReg);
|
|
|
|
DefMI->eraseFromParent();
|
2008-05-26 05:49:49 +00:00
|
|
|
}
|
2008-06-25 01:16:38 +00:00
|
|
|
VReg = ReMatRegs.find_next(VReg);
|
A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
|
|
|
}
|
|
|
|
|
2004-07-22 15:26:23 +00:00
|
|
|
return MadeChange;
|
2003-12-18 13:06:04 +00:00
|
|
|
}
|