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llvm-6502/include/llvm/IR/IntrinsicsX86.td

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Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
//===- IntrinsicsX86.td - Defines X86 intrinsics -----------*- tablegen -*-===//
Whitespace cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79036 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:12 +00:00
//
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
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// The LLVM Compiler Infrastructure
//
remove attribution from a variety of miscellaneous files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45425 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 22:59:10 +00:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Whitespace cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79036 91177308-0d34-0410-b5e6-96231b3b80d8
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//
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
//===----------------------------------------------------------------------===//
//
// This file defines all of the X86-specific intrinsics.
//
//===----------------------------------------------------------------------===//
Add a new llvm.x86.int intrinsic, allowing access to the x86 int and int3 instructions. Patch by Peter Housel! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 19:39:25 +00:00
//===----------------------------------------------------------------------===//
// Interrupt traps
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_int : Intrinsic<[], [llvm_i8_ty]>;
}
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
Add 3DNow! intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 00:32:41 +00:00
//===----------------------------------------------------------------------===//
// 3DNow!
let TargetPrefix = "x86" in {
def int_x86_3dnow_pavgusb : GCCBuiltin<"__builtin_ia32_pavgusb">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pf2id : GCCBuiltin<"__builtin_ia32_pf2id">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
def int_x86_3dnow_pfacc : GCCBuiltin<"__builtin_ia32_pfacc">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfadd : GCCBuiltin<"__builtin_ia32_pfadd">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfcmpeq : GCCBuiltin<"__builtin_ia32_pfcmpeq">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfcmpge : GCCBuiltin<"__builtin_ia32_pfcmpge">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfcmpgt : GCCBuiltin<"__builtin_ia32_pfcmpgt">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfmax : GCCBuiltin<"__builtin_ia32_pfmax">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfmin : GCCBuiltin<"__builtin_ia32_pfmin">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfmul : GCCBuiltin<"__builtin_ia32_pfmul">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfrcp : GCCBuiltin<"__builtin_ia32_pfrcp">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
def int_x86_3dnow_pfrcpit1 : GCCBuiltin<"__builtin_ia32_pfrcpit1">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfrcpit2 : GCCBuiltin<"__builtin_ia32_pfrcpit2">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfrsqrt : GCCBuiltin<"__builtin_ia32_pfrsqrt">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
def int_x86_3dnow_pfrsqit1 : GCCBuiltin<"__builtin_ia32_pfrsqit1">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfsub : GCCBuiltin<"__builtin_ia32_pfsub">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pfsubr : GCCBuiltin<"__builtin_ia32_pfsubr">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnow_pi2fd : GCCBuiltin<"__builtin_ia32_pi2fd">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
def int_x86_3dnow_pmulhrw : GCCBuiltin<"__builtin_ia32_pmulhrw">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
}
//===----------------------------------------------------------------------===//
// 3DNow! extensions
let TargetPrefix = "x86" in {
def int_x86_3dnowa_pf2iw : GCCBuiltin<"__builtin_ia32_pf2iw">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
def int_x86_3dnowa_pfnacc : GCCBuiltin<"__builtin_ia32_pfnacc">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnowa_pfpnacc : GCCBuiltin<"__builtin_ia32_pfpnacc">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
[IntrNoMem]>;
def int_x86_3dnowa_pi2fw : GCCBuiltin<"__builtin_ia32_pi2fw">,
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
def int_x86_3dnowa_pswapd :
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
}
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
//===----------------------------------------------------------------------===//
// SSE1
// Arithmetic ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_add_ss : GCCBuiltin<"__builtin_ia32_addss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65499 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-26 03:12:02 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_sub_ss : GCCBuiltin<"__builtin_ia32_subss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_mul_ss : GCCBuiltin<"__builtin_ia32_mulss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65499 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-26 03:12:02 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_div_ss : GCCBuiltin<"__builtin_ia32_divss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
[IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_sqrt_ps : GCCBuiltin<"__builtin_ia32_sqrtps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
[IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_rcp_ss : GCCBuiltin<"__builtin_ia32_rcpss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
[IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_rcp_ps : GCCBuiltin<"__builtin_ia32_rcpps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
[IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_rsqrt_ss : GCCBuiltin<"__builtin_ia32_rsqrtss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
[IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_rsqrt_ps : GCCBuiltin<"__builtin_ia32_rsqrtps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
[IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_min_ps : GCCBuiltin<"__builtin_ia32_minps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
}
// Comparison ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Add GCCBuiltin declarations for cmpsd/cmpss/cmppd/cmpps to allow custom code to be removed from clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 08:33:36 +00:00
def int_x86_sse_cmp_ss : GCCBuiltin<"__builtin_ia32_cmpss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Convert the intrinsic function definitions to use llvm_i32_ty instead of llvm_uint_ty or llvm_int_ty. Similarly for i8, i16 and i64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32802 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-31 22:24:55 +00:00
llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;
Add GCCBuiltin declarations for cmpsd/cmpss/cmppd/cmpps to allow custom code to be removed from clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 08:33:36 +00:00
def int_x86_sse_cmp_ps : GCCBuiltin<"__builtin_ia32_cmpps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Convert the intrinsic function definitions to use llvm_i32_ty instead of llvm_uint_ty or llvm_int_ty. Similarly for i8, i16 and i64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32802 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-31 22:24:55 +00:00
llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_comile_ss : GCCBuiltin<"__builtin_ia32_comile">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_comigt_ss : GCCBuiltin<"__builtin_ia32_comigt">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_comige_ss : GCCBuiltin<"__builtin_ia32_comige">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_comineq_ss : GCCBuiltin<"__builtin_ia32_comineq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_ucomieq_ss : GCCBuiltin<"__builtin_ia32_ucomieq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_ucomilt_ss : GCCBuiltin<"__builtin_ia32_ucomilt">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_ucomile_ss : GCCBuiltin<"__builtin_ia32_ucomile">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_ucomigt_ss : GCCBuiltin<"__builtin_ia32_ucomigt">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_ucomige_ss : GCCBuiltin<"__builtin_ia32_ucomige">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse_ucomineq_ss : GCCBuiltin<"__builtin_ia32_ucomineq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
}
// Conversion ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_cvtss2si : GCCBuiltin<"__builtin_ia32_cvtss2si">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Add missing SSE builtins: __builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-23 03:07:27 +00:00
def int_x86_sse_cvtss2si64 : GCCBuiltin<"__builtin_ia32_cvtss2si64">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Add missing SSE builtins: __builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-23 03:07:27 +00:00
def int_x86_sse_cvttss2si64 : GCCBuiltin<"__builtin_ia32_cvttss2si64">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Convert the intrinsic function definitions to use llvm_i32_ty instead of llvm_uint_ty or llvm_int_ty. Similarly for i8, i16 and i64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32802 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-31 22:24:55 +00:00
llvm_i32_ty], [IntrNoMem]>;
Add missing SSE builtins: __builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-23 03:07:27 +00:00
def int_x86_sse_cvtsi642ss : GCCBuiltin<"__builtin_ia32_cvtsi642ss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Add missing SSE builtins: __builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-23 03:07:27 +00:00
llvm_i64_ty], [IntrNoMem]>;
Add missing SSE builtins: CVTPD2PI, CVTPS2PI, CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43523 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-30 22:15:38 +00:00
def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Add missing SSE builtins: CVTPD2PI, CVTPS2PI, CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43523 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-30 22:15:38 +00:00
def int_x86_sse_cvttps2pi: GCCBuiltin<"__builtin_ia32_cvttps2pi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Add missing SSE builtins: CVTPD2PI, CVTPS2PI, CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43523 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-30 22:15:38 +00:00
def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">,
Whitespace cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79036 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:12 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
llvm_x86mmx_ty], [IntrNoMem]>;
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
}
// SIMD store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
[llvm_void_ty] is no longer needed for result types, just use an empty result list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:07 +00:00
Intrinsic<[], [llvm_ptr_ty,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 19:21:38 +00:00
llvm_v4f32_ty], [IntrReadWriteArgMem]>;
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
}
// Cacheability support ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
Intrinsic<[], [], []>;
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
}
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
// Control register.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Fix int_x86_sse_stmxcsr and int_x86_sse_ldmxcsr. Not directly translated from gcc builtins. They are not lowered into these intrinsics which take a ptr argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27505 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 00:47:01 +00:00
def int_x86_sse_stmxcsr :
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
Intrinsic<[], [llvm_ptr_ty], []>;
Fix int_x86_sse_stmxcsr and int_x86_sse_ldmxcsr. Not directly translated from gcc builtins. They are not lowered into these intrinsics which take a ptr argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27505 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 00:47:01 +00:00
def int_x86_sse_ldmxcsr :
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
Intrinsic<[], [llvm_ptr_ty], []>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
}
Intrinsics naming convention change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27172 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 08:23:12 +00:00
// Misc.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_movmsk_ps : GCCBuiltin<"__builtin_ia32_movmskps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
}
//===----------------------------------------------------------------------===//
// SSE2
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
// FP arithmetic ops
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_add_sd : GCCBuiltin<"__builtin_ia32_addsd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65499 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-26 03:12:02 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse2_sub_sd : GCCBuiltin<"__builtin_ia32_subsd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse2_mul_sd : GCCBuiltin<"__builtin_ia32_mulsd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65499 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-26 03:12:02 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse2_div_sd : GCCBuiltin<"__builtin_ia32_divsd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse2_sqrt_sd : GCCBuiltin<"__builtin_ia32_sqrtsd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
[IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse2_sqrt_pd : GCCBuiltin<"__builtin_ia32_sqrtpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
[IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse2_min_sd : GCCBuiltin<"__builtin_ia32_minsd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse2_min_pd : GCCBuiltin<"__builtin_ia32_minpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse2_max_sd : GCCBuiltin<"__builtin_ia32_maxsd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
def int_x86_sse2_max_pd : GCCBuiltin<"__builtin_ia32_maxpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Add more SSE intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27247 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 06:07:16 +00:00
}
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
// FP comparison ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Add GCCBuiltin declarations for cmpsd/cmpss/cmppd/cmpps to allow custom code to be removed from clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 08:33:36 +00:00
def int_x86_sse2_cmp_sd : GCCBuiltin<"__builtin_ia32_cmpsd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Convert the intrinsic function definitions to use llvm_i32_ty instead of llvm_uint_ty or llvm_int_ty. Similarly for i8, i16 and i64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32802 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-31 22:24:55 +00:00
llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>;
Add GCCBuiltin declarations for cmpsd/cmpss/cmppd/cmpps to allow custom code to be removed from clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 08:33:36 +00:00
def int_x86_sse2_cmp_pd : GCCBuiltin<"__builtin_ia32_cmppd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Convert the intrinsic function definitions to use llvm_i32_ty instead of llvm_uint_ty or llvm_int_ty. Similarly for i8, i16 and i64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32802 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-31 22:24:55 +00:00
llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_comieq_sd : GCCBuiltin<"__builtin_ia32_comisdeq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_comilt_sd : GCCBuiltin<"__builtin_ia32_comisdlt">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_comile_sd : GCCBuiltin<"__builtin_ia32_comisdle">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_comigt_sd : GCCBuiltin<"__builtin_ia32_comisdgt">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_comige_sd : GCCBuiltin<"__builtin_ia32_comisdge">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_comineq_sd : GCCBuiltin<"__builtin_ia32_comisdneq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_ucomieq_sd : GCCBuiltin<"__builtin_ia32_ucomisdeq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_ucomilt_sd : GCCBuiltin<"__builtin_ia32_ucomisdlt">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_ucomile_sd : GCCBuiltin<"__builtin_ia32_ucomisdle">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_ucomigt_sd : GCCBuiltin<"__builtin_ia32_ucomisdgt">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_ucomige_sd : GCCBuiltin<"__builtin_ia32_ucomisdge">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
def int_x86_sse2_ucomineq_sd : GCCBuiltin<"__builtin_ia32_ucomisdneq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added comi and ucomi SSE intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27443 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 23:37:18 +00:00
}
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
// Integer arithmetic ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_padds_b : GCCBuiltin<"__builtin_ia32_paddsb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v16i8_ty], [IntrNoMem, Commutative]>;
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
def int_x86_sse2_padds_w : GCCBuiltin<"__builtin_ia32_paddsw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
def int_x86_sse2_paddus_b : GCCBuiltin<"__builtin_ia32_paddusb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v16i8_ty], [IntrNoMem, Commutative]>;
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
def int_x86_sse2_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
def int_x86_sse2_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_sse2_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_sse2_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_sse2_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
pmul*, pmadd*, and pavg* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27642 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 05:09:06 +00:00
def int_x86_sse2_pmulhu_w : GCCBuiltin<"__builtin_ia32_pmulhuw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
pmul*, pmadd*, and pavg* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27642 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 05:09:06 +00:00
def int_x86_sse2_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
pmul*, pmadd*, and pavg* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27642 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 05:09:06 +00:00
def int_x86_sse2_pmulu_dq : GCCBuiltin<"__builtin_ia32_pmuludq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v4i32_ty], [IntrNoMem, Commutative]>;
pmul*, pmadd*, and pavg* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27642 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 05:09:06 +00:00
def int_x86_sse2_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
pmul*, pmadd*, and pavg* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27642 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 05:09:06 +00:00
def int_x86_sse2_pavg_b : GCCBuiltin<"__builtin_ia32_pavgb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v16i8_ty], [IntrNoMem, Commutative]>;
pmul*, pmadd*, and pavg* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27642 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 05:09:06 +00:00
def int_x86_sse2_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
pmin, pmax, and psad intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27646 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 06:09:41 +00:00
def int_x86_sse2_pmaxu_b : GCCBuiltin<"__builtin_ia32_pmaxub128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v16i8_ty], [IntrNoMem, Commutative]>;
pmin, pmax, and psad intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27646 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 06:09:41 +00:00
def int_x86_sse2_pmaxs_w : GCCBuiltin<"__builtin_ia32_pmaxsw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
pmin, pmax, and psad intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27646 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 06:09:41 +00:00
def int_x86_sse2_pminu_b : GCCBuiltin<"__builtin_ia32_pminub128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v16i8_ty], [IntrNoMem, Commutative]>;
pmin, pmax, and psad intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27646 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 06:09:41 +00:00
def int_x86_sse2_pmins_w : GCCBuiltin<"__builtin_ia32_pminsw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
pmin, pmax, and psad intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27646 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 06:09:41 +00:00
def int_x86_sse2_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v16i8_ty], [IntrNoMem, Commutative]>;
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:43:35 +00:00
}
Added intrinsics to match __builtin_ia32_pslldqi128 and __builtin_ia32_psrldqi128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27411 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 21:48:31 +00:00
// Integer shift ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Add a few more missing gcc builtin's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45278 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-21 01:30:39 +00:00
def int_x86_sse2_psll_w : GCCBuiltin<"__builtin_ia32_psllw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Add a few more missing gcc builtin's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45278 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-21 01:30:39 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_sse2_psll_d : GCCBuiltin<"__builtin_ia32_pslld128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
psll*, psrl*, and psra* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27684 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 00:14:05 +00:00
llvm_v4i32_ty], [IntrNoMem]>;
Add a few more missing gcc builtin's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45278 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-21 01:30:39 +00:00
def int_x86_sse2_psll_q : GCCBuiltin<"__builtin_ia32_psllq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
Add a few more missing gcc builtin's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45278 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-21 01:30:39 +00:00
llvm_v2i64_ty], [IntrNoMem]>;
def int_x86_sse2_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Fix sse2.psrl.w and sse2.psrl.q definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45772 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-09 02:16:44 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
Add a few more missing gcc builtin's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45278 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-21 01:30:39 +00:00
def int_x86_sse2_psrl_d : GCCBuiltin<"__builtin_ia32_psrld128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
psll*, psrl*, and psra* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27684 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 00:14:05 +00:00
llvm_v4i32_ty], [IntrNoMem]>;
Add a few more missing gcc builtin's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45278 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-21 01:30:39 +00:00
def int_x86_sse2_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
Fix sse2.psrl.w and sse2.psrl.q definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45772 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-09 02:16:44 +00:00
llvm_v2i64_ty], [IntrNoMem]>;
These have matching builtin's in 4.2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45139 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-18 00:52:20 +00:00
def int_x86_sse2_psra_w : GCCBuiltin<"__builtin_ia32_psraw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Type specification didn't match gcc's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45260 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-20 09:35:28 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
These have matching builtin's in 4.2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45139 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-18 00:52:20 +00:00
def int_x86_sse2_psra_d : GCCBuiltin<"__builtin_ia32_psrad128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
psll*, psrl*, and psra* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27684 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 00:14:05 +00:00
llvm_v4i32_ty], [IntrNoMem]>;
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
def int_x86_sse2_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_psrai_d : GCCBuiltin<"__builtin_ia32_psradi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
"The original bug was a complaint that _mm_srli_si128 mis-compiled when passed a constant vector ("{0x123, 0x456}" syntax). The fix is to simplify the _mm_srli_si128 macro, and move the "* 8" from the macro into the compiler back-end. I can't change the existing __builtins because so many people are using them :-(." Patch by Stuart Hastings! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56944 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-02 05:56:52 +00:00
def int_x86_sse2_psll_dq_bs : GCCBuiltin<"__builtin_ia32_pslldqi128_byteshift">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
"The original bug was a complaint that _mm_srli_si128 mis-compiled when passed a constant vector ("{0x123, 0x456}" syntax). The fix is to simplify the _mm_srli_si128 macro, and move the "* 8" from the macro into the compiler back-end. I can't change the existing __builtins because so many people are using them :-(." Patch by Stuart Hastings! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56944 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-02 05:56:52 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse2_psrl_dq_bs : GCCBuiltin<"__builtin_ia32_psrldqi128_byteshift">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty,
"The original bug was a complaint that _mm_srli_si128 mis-compiled when passed a constant vector ("{0x123, 0x456}" syntax). The fix is to simplify the _mm_srli_si128 macro, and move the "* 8" from the macro into the compiler back-end. I can't change the existing __builtins because so many people are using them :-(." Patch by Stuart Hastings! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56944 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-02 05:56:52 +00:00
llvm_i32_ty], [IntrNoMem]>;
Added intrinsics to match __builtin_ia32_pslldqi128 and __builtin_ia32_psrldqi128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27411 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-04 21:48:31 +00:00
}
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
// Conversion ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_cvtdq2pd : GCCBuiltin<"__builtin_ia32_cvtdq2pd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
def int_x86_sse2_cvtdq2ps : GCCBuiltin<"__builtin_ia32_cvtdq2ps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
def int_x86_sse2_cvtpd2dq : GCCBuiltin<"__builtin_ia32_cvtpd2dq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
def int_x86_sse2_cvttpd2dq : GCCBuiltin<"__builtin_ia32_cvttpd2dq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
def int_x86_sse2_cvtpd2ps : GCCBuiltin<"__builtin_ia32_cvtpd2ps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
def int_x86_sse2_cvtps2dq : GCCBuiltin<"__builtin_ia32_cvtps2dq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
def int_x86_sse2_cvttps2dq : GCCBuiltin<"__builtin_ia32_cvttps2dq">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
def int_x86_sse2_cvtps2pd : GCCBuiltin<"__builtin_ia32_cvtps2pd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
def int_x86_sse2_cvtsd2si : GCCBuiltin<"__builtin_ia32_cvtsd2si">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Add missing SSE builtins: __builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-23 03:07:27 +00:00
def int_x86_sse2_cvtsd2si64 : GCCBuiltin<"__builtin_ia32_cvtsd2si64">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
def int_x86_sse2_cvttsd2si : GCCBuiltin<"__builtin_ia32_cvttsd2si">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Add missing SSE builtins: __builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-23 03:07:27 +00:00
def int_x86_sse2_cvttsd2si64 : GCCBuiltin<"__builtin_ia32_cvttsd2si64">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
SSE / SSE2 conversion intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27637 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 23:42:44 +00:00
def int_x86_sse2_cvtsi2sd : GCCBuiltin<"__builtin_ia32_cvtsi2sd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Convert the intrinsic function definitions to use llvm_i32_ty instead of llvm_uint_ty or llvm_int_ty. Similarly for i8, i16 and i64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32802 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-31 22:24:55 +00:00
llvm_i32_ty], [IntrNoMem]>;
Add missing SSE builtins: __builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-23 03:07:27 +00:00
def int_x86_sse2_cvtsi642sd : GCCBuiltin<"__builtin_ia32_cvtsi642sd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Add missing SSE builtins: __builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-23 03:07:27 +00:00
llvm_i64_ty], [IntrNoMem]>;
SSE / SSE2 conversion intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27637 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 23:42:44 +00:00
def int_x86_sse2_cvtsd2ss : GCCBuiltin<"__builtin_ia32_cvtsd2ss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
SSE / SSE2 conversion intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27637 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 23:42:44 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_sse2_cvtss2sd : GCCBuiltin<"__builtin_ia32_cvtss2sd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
SSE / SSE2 conversion intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27637 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 23:42:44 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Add missing SSE builtins: CVTPD2PI, CVTPS2PI, CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43523 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-30 22:15:38 +00:00
def int_x86_sse_cvtpd2pi : GCCBuiltin<"__builtin_ia32_cvtpd2pi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Add missing SSE builtins: CVTPD2PI, CVTPS2PI, CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43523 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-30 22:15:38 +00:00
def int_x86_sse_cvttpd2pi: GCCBuiltin<"__builtin_ia32_cvttpd2pi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Add missing SSE builtins: CVTPD2PI, CVTPS2PI, CVTTPD2PI, CVTTPS2PI, CVTPI2PD, CVTPI2PS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43523 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-30 22:15:38 +00:00
def int_x86_sse_cvtpi2pd : GCCBuiltin<"__builtin_ia32_cvtpi2pd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
Various SSE2 conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27603 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 05:20:24 +00:00
}
__builtin_ia32_loadup{s|d}, __builtin_ia32_storeup{s|d} git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27561 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 21:09:59 +00:00
// SIMD store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
[llvm_void_ty] is no longer needed for result types, just use an empty result list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:07 +00:00
Intrinsic<[], [llvm_ptr_ty,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 19:21:38 +00:00
llvm_v2f64_ty], [IntrReadWriteArgMem]>;
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si, __builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27599 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 22:28:25 +00:00
def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">,
[llvm_void_ty] is no longer needed for result types, just use an empty result list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:07 +00:00
Intrinsic<[], [llvm_ptr_ty,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 19:21:38 +00:00
llvm_v16i8_ty], [IntrReadWriteArgMem]>;
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si, __builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27599 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 22:28:25 +00:00
def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">,
[llvm_void_ty] is no longer needed for result types, just use an empty result list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:07 +00:00
Intrinsic<[], [llvm_ptr_ty,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 19:21:38 +00:00
llvm_v4i32_ty], [IntrReadWriteArgMem]>;
__builtin_ia32_loadup{s|d}, __builtin_ia32_storeup{s|d} git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27561 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 21:09:59 +00:00
}
Add SSE2 integer pack with saturation intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27253 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 23:09:19 +00:00
// Misc.
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Add SSE2 integer pack with saturation intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27253 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 23:09:19 +00:00
def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
Fix PR5315, original patch by Nicolas Capens! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86203 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 00:11:57 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v8i16_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
Add SSE2 integer pack with saturation intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27253 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 23:09:19 +00:00
def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">,
Fix PR5315, original patch by Nicolas Capens! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86203 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 00:11:57 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4i32_ty], [IntrNoMem]>;
Add SSE2 integer pack with saturation intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27253 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 23:09:19 +00:00
def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">,
Fix PR5315, original patch by Nicolas Capens! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86203 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-06 00:11:57 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v8i16_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
Naming inconsistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27638 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-13 00:00:23 +00:00
def int_x86_sse2_movmsk_pd : GCCBuiltin<"__builtin_ia32_movmskpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Add 128-bit pmovmskb intrinsic support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27255 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-30 00:33:26 +00:00
def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
movnt* and maskmovdqu intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27587 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-11 06:57:30 +00:00
def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">,
[llvm_void_ty] is no longer needed for result types, just use an empty result list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:07 +00:00
Intrinsic<[], [llvm_v16i8_ty,
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
llvm_v16i8_ty, llvm_ptr_ty], []>;
Misc. SSE2 intrinsics: clflush, lfench, mfence git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27699 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 07:43:12 +00:00
def int_x86_sse2_clflush : GCCBuiltin<"__builtin_ia32_clflush">,
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
Intrinsic<[], [llvm_ptr_ty], []>;
Misc. SSE2 intrinsics: clflush, lfench, mfence git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27699 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 07:43:12 +00:00
def int_x86_sse2_lfence : GCCBuiltin<"__builtin_ia32_lfence">,
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
Intrinsic<[], [], []>;
Misc. SSE2 intrinsics: clflush, lfench, mfence git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27699 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 07:43:12 +00:00
def int_x86_sse2_mfence : GCCBuiltin<"__builtin_ia32_mfence">,
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
Intrinsic<[], [], []>;
Split the PPC and X86 intrinsics out to their own files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:37:19 +00:00
}
Added haddp{s|d} and hsubp{s|d} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27309 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 21:28:46 +00:00
//===----------------------------------------------------------------------===//
// SSE3
Last few SSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 21:59:03 +00:00
// Addition / subtraction ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse3_addsub_ps : GCCBuiltin<"__builtin_ia32_addsubps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Last few SSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 21:59:03 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_sse3_addsub_pd : GCCBuiltin<"__builtin_ia32_addsubpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Last few SSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 21:59:03 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
}
Added haddp{s|d} and hsubp{s|d} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27309 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 21:28:46 +00:00
// Horizontal ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse3_hadd_ps : GCCBuiltin<"__builtin_ia32_haddps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added haddp{s|d} and hsubp{s|d} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27309 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 21:28:46 +00:00
def int_x86_sse3_hadd_pd : GCCBuiltin<"__builtin_ia32_haddpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added haddp{s|d} and hsubp{s|d} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27309 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 21:28:46 +00:00
def int_x86_sse3_hsub_ps : GCCBuiltin<"__builtin_ia32_hsubps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v4f32_ty], [IntrNoMem]>;
Added haddp{s|d} and hsubp{s|d} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27309 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 21:28:46 +00:00
def int_x86_sse3_hsub_pd : GCCBuiltin<"__builtin_ia32_hsubpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
Fix a typo: Instr* -> Intr* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-10 22:02:59 +00:00
llvm_v2f64_ty], [IntrNoMem]>;
Added haddp{s|d} and hsubp{s|d} intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27309 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 21:28:46 +00:00
}
Last few SSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 21:59:03 +00:00
// Specialized unaligned load.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse3_ldu_dq : GCCBuiltin<"__builtin_ia32_lddqu">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty], [IntrReadMem]>;
Last few SSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 21:59:03 +00:00
}
// Thread synchronization ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse3_monitor : GCCBuiltin<"__builtin_ia32_monitor">,
[llvm_void_ty] is no longer needed for result types, just use an empty result list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:07 +00:00
Intrinsic<[], [llvm_ptr_ty,
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
llvm_i32_ty, llvm_i32_ty], []>;
Last few SSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 21:59:03 +00:00
def int_x86_sse3_mwait : GCCBuiltin<"__builtin_ia32_mwait">,
[llvm_void_ty] is no longer needed for result types, just use an empty result list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:07 +00:00
Intrinsic<[], [llvm_i32_ty,
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
llvm_i32_ty], []>;
Last few SSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-14 21:59:03 +00:00
}
Add the emms intrinsic for MMX support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34938 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-05 23:09:45 +00:00
Add support for our first SSSE3 instruction "pmulhrsw". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10 22:10:25 +00:00
//===----------------------------------------------------------------------===//
// SSSE3
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
// Horizontal arithmetic ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_ssse3_phadd_w : GCCBuiltin<"__builtin_ia32_phaddw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_phadd_w_128 : GCCBuiltin<"__builtin_ia32_phaddw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Horizontal-add instructions are not commutative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52363 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 21:16:24 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_phadd_d : GCCBuiltin<"__builtin_ia32_phaddd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_phadd_d_128 : GCCBuiltin<"__builtin_ia32_phaddd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
Horizontal-add instructions are not commutative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52363 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 21:16:24 +00:00
llvm_v4i32_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_phadd_sw : GCCBuiltin<"__builtin_ia32_phaddsw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_phadd_sw_128 : GCCBuiltin<"__builtin_ia32_phaddsw128">,
Fix operand type for int_x86_ssse3_phadd_sw_128 intrinsic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143336 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-31 07:16:37 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_phsub_w : GCCBuiltin<"__builtin_ia32_phsubw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_phsub_w_128 : GCCBuiltin<"__builtin_ia32_phsubw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_ssse3_phsub_d : GCCBuiltin<"__builtin_ia32_phsubd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_phsub_d_128 : GCCBuiltin<"__builtin_ia32_phsubd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_ssse3_phsub_sw : GCCBuiltin<"__builtin_ia32_phsubsw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_phsub_sw_128 : GCCBuiltin<"__builtin_ia32_phsubsw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_ssse3_pmadd_ub_sw : GCCBuiltin<"__builtin_ia32_pmaddubsw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_pmadd_ub_sw_128 : GCCBuiltin<"__builtin_ia32_pmaddubsw128">,
Fix operand type for x86 pmadd_ub_sw intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-01 07:25:22 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty,
llvm_v16i8_ty], [IntrNoMem]>;
Horizontal-add instructions are not commutative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52363 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 21:16:24 +00:00
}
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
Horizontal-add instructions are not commutative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52363 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 21:16:24 +00:00
// Packed multiply high with round and scale
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_pmul_hr_sw : GCCBuiltin<"__builtin_ia32_pmulhrsw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_pmul_hr_sw_128 : GCCBuiltin<"__builtin_ia32_pmulhrsw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
}
// Shuffle ops
Add support for our first SSSE3 instruction "pmulhrsw". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10 22:10:25 +00:00
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_pshuf_b : GCCBuiltin<"__builtin_ia32_pshufb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
llvm_v16i8_ty], [IntrNoMem]>;
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place it in with the SSSE3 instructions. Steward! Could you place this chair by the aft sun deck? I'm trying to get away from the Astors. They are such boors! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-04 20:24:01 +00:00
def int_x86_sse_pshuf_w : GCCBuiltin<"__builtin_ia32_pshufw">,
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 19:09:13 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_i8_ty],
Recommit with changes. Comment out palignr for the moment, as there's a testcase that uses it and expects it to be subject to optimizations; we won't be doing that. Some adjustments based on feedback from Bill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:43:48 +00:00
[IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
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}
// Sign ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_ssse3_psign_b : GCCBuiltin<"__builtin_ia32_psignb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_psign_b_128 : GCCBuiltin<"__builtin_ia32_psignb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_ssse3_psign_w : GCCBuiltin<"__builtin_ia32_psignw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_psign_w_128 : GCCBuiltin<"__builtin_ia32_psignw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
Add support for our first SSSE3 instruction "pmulhrsw". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10 22:10:25 +00:00
llvm_v8i16_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_psign_d : GCCBuiltin<"__builtin_ia32_psignd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_psign_d_128 : GCCBuiltin<"__builtin_ia32_psignd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_v4i32_ty], [IntrNoMem]>;
}
// Absolute value ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_ssse3_pabs_b : GCCBuiltin<"__builtin_ia32_pabsb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_ssse3_pabs_b_128 : GCCBuiltin<"__builtin_ia32_pabsb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-10 06:22:27 +00:00
def int_x86_ssse3_pabs_w : GCCBuiltin<"__builtin_ia32_pabsw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_ssse3_pabs_w_128 : GCCBuiltin<"__builtin_ia32_pabsw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_ssse3_pabs_d : GCCBuiltin<"__builtin_ia32_pabsd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_ssse3_pabs_d_128 : GCCBuiltin<"__builtin_ia32_pabsd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
Adding SSSE3 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40982 91177308-0d34-0410-b5e6-96231b3b80d8
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}
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
//===----------------------------------------------------------------------===//
// SSE4.1
// FP rounding ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_round_ss : GCCBuiltin<"__builtin_ia32_roundss">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse41_round_ps : GCCBuiltin<"__builtin_ia32_roundps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse41_round_sd : GCCBuiltin<"__builtin_ia32_roundsd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_sse41_round_pd : GCCBuiltin<"__builtin_ia32_roundpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
llvm_i32_ty], [IntrNoMem]>;
}
// Vector sign and zero extend
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_pmovsxbd : GCCBuiltin<"__builtin_ia32_pmovsxbd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovsxbq : GCCBuiltin<"__builtin_ia32_pmovsxbq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovsxbw : GCCBuiltin<"__builtin_ia32_pmovsxbw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovsxdq : GCCBuiltin<"__builtin_ia32_pmovsxdq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovsxwd : GCCBuiltin<"__builtin_ia32_pmovsxwd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovsxwq : GCCBuiltin<"__builtin_ia32_pmovsxwq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovzxbd : GCCBuiltin<"__builtin_ia32_pmovzxbd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovzxbq : GCCBuiltin<"__builtin_ia32_pmovzxbq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovzxbw : GCCBuiltin<"__builtin_ia32_pmovzxbw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovzxdq : GCCBuiltin<"__builtin_ia32_pmovzxdq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovzxwd : GCCBuiltin<"__builtin_ia32_pmovzxwd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmovzxwq : GCCBuiltin<"__builtin_ia32_pmovzxwq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
// Vector min element
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_phminposuw : GCCBuiltin<"__builtin_ia32_phminposuw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
// Vector compare, min, max
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_pmaxsb : GCCBuiltin<"__builtin_ia32_pmaxsb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmaxsd : GCCBuiltin<"__builtin_ia32_pmaxsd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmaxud : GCCBuiltin<"__builtin_ia32_pmaxud128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pmaxuw : GCCBuiltin<"__builtin_ia32_pmaxuw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pminsb : GCCBuiltin<"__builtin_ia32_pminsb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pminsd : GCCBuiltin<"__builtin_ia32_pminsd128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pminud : GCCBuiltin<"__builtin_ia32_pminud128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pminuw : GCCBuiltin<"__builtin_ia32_pminuw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
Reapply Kevin's change 94440, now that Chris has fixed the limitation on opcode values fitting in one byte (svn r99494). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 16:36:14 +00:00
// Advanced Encryption Standard (AES) Instructions
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Add aeskeygenassist intrinsic and rename all of the aes intrinsics to aes instead of sse4.2. Add a brief todo for a subtarget flag and rework the aeskeygenassist instruction to more closely match the docs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01 03:05:45 +00:00
def int_x86_aesni_aesimc : GCCBuiltin<"__builtin_ia32_aesimc128">,
Rewrite aesimc handling. It only takes a single input and has a single dest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 23:48:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty],
Reapply Kevin's change 94440, now that Chris has fixed the limitation on opcode values fitting in one byte (svn r99494). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 16:36:14 +00:00
[IntrNoMem]>;
Add aeskeygenassist intrinsic and rename all of the aes intrinsics to aes instead of sse4.2. Add a brief todo for a subtarget flag and rework the aeskeygenassist instruction to more closely match the docs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01 03:05:45 +00:00
def int_x86_aesni_aesenc : GCCBuiltin<"__builtin_ia32_aesenc128">,
Reapply Kevin's change 94440, now that Chris has fixed the limitation on opcode values fitting in one byte (svn r99494). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 16:36:14 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
Add aeskeygenassist intrinsic and rename all of the aes intrinsics to aes instead of sse4.2. Add a brief todo for a subtarget flag and rework the aeskeygenassist instruction to more closely match the docs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01 03:05:45 +00:00
def int_x86_aesni_aesenclast : GCCBuiltin<"__builtin_ia32_aesenclast128">,
Reapply Kevin's change 94440, now that Chris has fixed the limitation on opcode values fitting in one byte (svn r99494). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 16:36:14 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
Add aeskeygenassist intrinsic and rename all of the aes intrinsics to aes instead of sse4.2. Add a brief todo for a subtarget flag and rework the aeskeygenassist instruction to more closely match the docs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01 03:05:45 +00:00
def int_x86_aesni_aesdec : GCCBuiltin<"__builtin_ia32_aesdec128">,
Reapply Kevin's change 94440, now that Chris has fixed the limitation on opcode values fitting in one byte (svn r99494). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 16:36:14 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
Add aeskeygenassist intrinsic and rename all of the aes intrinsics to aes instead of sse4.2. Add a brief todo for a subtarget flag and rework the aeskeygenassist instruction to more closely match the docs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01 03:05:45 +00:00
def int_x86_aesni_aesdeclast : GCCBuiltin<"__builtin_ia32_aesdeclast128">,
Reapply Kevin's change 94440, now that Chris has fixed the limitation on opcode values fitting in one byte (svn r99494). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 16:36:14 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
Make sure aeskeygenassist uses an unsigned immediate field. Fixes rdar://8017638 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:33:22 +00:00
def int_x86_aesni_aeskeygenassist :
Fix typo aeskeygenassist -> aeskeygenassist128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100250 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 23:29:36 +00:00
GCCBuiltin<"__builtin_ia32_aeskeygenassist128">,
Make sure aeskeygenassist uses an unsigned immediate field. Fixes rdar://8017638 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:33:22 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i8_ty],
Add aeskeygenassist intrinsic and rename all of the aes intrinsics to aes instead of sse4.2. Add a brief todo for a subtarget flag and rework the aeskeygenassist instruction to more closely match the docs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01 03:05:45 +00:00
[IntrNoMem]>;
Reapply Kevin's change 94440, now that Chris has fixed the limitation on opcode values fitting in one byte (svn r99494). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 16:36:14 +00:00
}
Add intrinsic for pclmulqdq instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157731 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31 04:37:40 +00:00
// PCLMUL instruction
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_pclmulqdq : GCCBuiltin<"__builtin_ia32_pclmulqdq128">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty],
[IntrNoMem]>;
}
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
// Vector pack
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_packusdw : GCCBuiltin<"__builtin_ia32_packusdw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
// Vector multiply
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_pmuldq : GCCBuiltin<"__builtin_ia32_pmuldq128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
// Vector extract
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Missed one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46733 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-05 01:12:10 +00:00
def int_x86_sse41_pextrb :
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty, llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
Missed one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46733 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-05 01:12:10 +00:00
def int_x86_sse41_pextrd :
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty, llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
Missed one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46733 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-05 01:12:10 +00:00
def int_x86_sse41_pextrq :
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i64_ty], [llvm_v2i64_ty, llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_extractps : GCCBuiltin<"__builtin_ia32_extractps128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
// Vector insert
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_insertps : GCCBuiltin<"__builtin_ia32_insertps128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
// Vector blend
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_pblendvb : GCCBuiltin<"__builtin_ia32_pblendvb128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,llvm_v16i8_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_pblendw : GCCBuiltin<"__builtin_ia32_pblendw128">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_blendpd : GCCBuiltin<"__builtin_ia32_blendpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_blendps : GCCBuiltin<"__builtin_ia32_blendps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_blendvpd : GCCBuiltin<"__builtin_ia32_blendvpd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,llvm_v2f64_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_blendvps : GCCBuiltin<"__builtin_ia32_blendvps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,llvm_v4f32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
// Vector dot product
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_dppd : GCCBuiltin<"__builtin_ia32_dppd">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
def int_x86_sse41_dpps : GCCBuiltin<"__builtin_ia32_dpps">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
// Vector sum of absolute differences
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_mpsadbw : GCCBuiltin<"__builtin_ia32_mpsadbw128">,
Fix return type for X86 mpsadbw instrinsic. The instruction takes in a vector of 8-bit integers, but produces a vector of 16-bit integers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-30 17:22:45 +00:00
Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty,llvm_i32_ty],
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
[IntrNoMem, Commutative]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
- Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 20:29:38 +00:00
// Cacheability support ops
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_movntdqa : GCCBuiltin<"__builtin_ia32_movntdqa">,
Modify the intrinsics pattern to separate out the "return" types from the "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13 09:08:33 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty], [IntrReadMem]>;
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
}
Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower to ptest instruction plus setcc. Revamp ptest instruction. Add test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 00:28:05 +00:00
// Test instruction with bitwise comparison.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_ptestz : GCCBuiltin<"__builtin_ia32_ptestz128">,
Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are integer instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12 07:23:00 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower to ptest instruction plus setcc. Revamp ptest instruction. Add test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 00:28:05 +00:00
[IntrNoMem]>;
def int_x86_sse41_ptestc : GCCBuiltin<"__builtin_ia32_ptestc128">,
Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are integer instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12 07:23:00 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower to ptest instruction plus setcc. Revamp ptest instruction. Add test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 00:28:05 +00:00
[IntrNoMem]>;
def int_x86_sse41_ptestnzc : GCCBuiltin<"__builtin_ia32_ptestnzc128">,
Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are integer instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-12 07:23:00 +00:00
Intrinsic<[llvm_i32_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower to ptest instruction plus setcc. Revamp ptest instruction. Add test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77407 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29 00:28:05 +00:00
[IntrNoMem]>;
}
SSE 4.1 Intrinsics and detection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
Define intrinsics for crc instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78482 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 18:07:59 +00:00
//===----------------------------------------------------------------------===//
// SSE4.2
// Miscellaneous
// CRC Instruction
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 23:13:19 +00:00
def int_x86_sse42_crc32_32_8 : GCCBuiltin<"__builtin_ia32_crc32qi">,
Define intrinsics for crc instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78482 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 18:07:59 +00:00
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i8_ty],
[IntrNoMem]>;
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 23:13:19 +00:00
def int_x86_sse42_crc32_32_16 : GCCBuiltin<"__builtin_ia32_crc32hi">,
Fix some cut and paste-os. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78493 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:09:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i16_ty],
Define intrinsics for crc instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78482 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 18:07:59 +00:00
[IntrNoMem]>;
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 23:13:19 +00:00
def int_x86_sse42_crc32_32_32 : GCCBuiltin<"__builtin_ia32_crc32si">,
Fix some cut and paste-os. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78493 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:09:33 +00:00
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
Define intrinsics for crc instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78482 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 18:07:59 +00:00
[IntrNoMem]>;
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 23:13:19 +00:00
def int_x86_sse42_crc32_64_8 :
Fixed the encoding problems of the crc32 instructions. All had the Operand size override prefix and only the r/m16 forms should have had that. Also for variant one, the AT&T syntax, added suffixes to all forms. Also added the missing 64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and tweaked one test case to add the needed suffixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 20:04:42 +00:00
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i8_ty],
[IntrNoMem]>;
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 23:13:19 +00:00
def int_x86_sse42_crc32_64_64 : GCCBuiltin<"__builtin_ia32_crc32di">,
Fix some cut and paste-os. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78493 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 20:09:33 +00:00
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
Define intrinsics for crc instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78482 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-08 18:07:59 +00:00
[IntrNoMem]>;
}
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
// String/text processing ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse42_pcmpistrm128 : GCCBuiltin<"__builtin_ia32_pcmpistrm128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_v16i8_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpistri128 : GCCBuiltin<"__builtin_ia32_pcmpistri128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpistria128 : GCCBuiltin<"__builtin_ia32_pcmpistria128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpistric128 : GCCBuiltin<"__builtin_ia32_pcmpistric128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpistrio128 : GCCBuiltin<"__builtin_ia32_pcmpistrio128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpistris128 : GCCBuiltin<"__builtin_ia32_pcmpistris128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpistriz128 : GCCBuiltin<"__builtin_ia32_pcmpistriz128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpestrm128 : GCCBuiltin<"__builtin_ia32_pcmpestrm128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_v16i8_ty],
[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpestri128 : GCCBuiltin<"__builtin_ia32_pcmpestri128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpestria128 : GCCBuiltin<"__builtin_ia32_pcmpestria128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpestric128 : GCCBuiltin<"__builtin_ia32_pcmpestric128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpestrio128 : GCCBuiltin<"__builtin_ia32_pcmpestrio128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpestris128 : GCCBuiltin<"__builtin_ia32_pcmpestris128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 20:27:57 +00:00
def int_x86_sse42_pcmpestriz128 : GCCBuiltin<"__builtin_ia32_pcmpestriz128">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty],
[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i8_ty],
[IntrNoMem]>;
Add sse4.2 string/text processing intrinsics. We'll select these later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79037 91177308-0d34-0410-b5e6-96231b3b80d8
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}
Add SSE4A MOVNTSS/MOVNTSD instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
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//===----------------------------------------------------------------------===//
// SSE4A
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_sse4a_extrqi : GCCBuiltin<"__builtin_ia32_extrqi">,
Mark insertq/extrq intrinsic readnone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157688 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i8_ty, llvm_i8_ty],
[IntrNoMem]>;
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_sse4a_extrq : GCCBuiltin<"__builtin_ia32_extrq">,
Mark insertq/extrq intrinsic readnone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157688 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v16i8_ty], [IntrNoMem]>;
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_sse4a_insertqi : GCCBuiltin<"__builtin_ia32_insertqi">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
Mark insertq/extrq intrinsic readnone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157688 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_i8_ty, llvm_i8_ty], [IntrNoMem]>;
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_sse4a_insertq : GCCBuiltin<"__builtin_ia32_insertq">,
Mark insertq/extrq intrinsic readnone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157688 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
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Add SSE4A MOVNTSS/MOVNTSD instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 05:36:19 +00:00
def int_x86_sse4a_movnt_ss : GCCBuiltin<"__builtin_ia32_movntss">,
Intrinsic<[], [llvm_ptr_ty, llvm_v4f32_ty], []>;
def int_x86_sse4a_movnt_sd : GCCBuiltin<"__builtin_ia32_movntsd">,
Intrinsic<[], [llvm_ptr_ty, llvm_v2f64_ty], []>;
}
Support x86 AVX 256-bit instruction intrinsics. Right now support all of them, but as soon as we properly codegen the simple vector operations in clang, remove the unnecessary builti-ins/intrinsics from clang and llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110094 91177308-0d34-0410-b5e6-96231b3b80d8
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//===----------------------------------------------------------------------===//
// AVX
// Arithmetic ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_addsub_pd_256 : GCCBuiltin<"__builtin_ia32_addsubpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_addsub_ps_256 : GCCBuiltin<"__builtin_ia32_addsubps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_max_pd_256 : GCCBuiltin<"__builtin_ia32_maxpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_max_ps_256 : GCCBuiltin<"__builtin_ia32_maxps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_min_pd_256 : GCCBuiltin<"__builtin_ia32_minpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_min_ps_256 : GCCBuiltin<"__builtin_ia32_minps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_sqrt_pd_256 : GCCBuiltin<"__builtin_ia32_sqrtpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_sqrt_ps_256 : GCCBuiltin<"__builtin_ia32_sqrtps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_rsqrt_ps_256 : GCCBuiltin<"__builtin_ia32_rsqrtps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_rcp_ps_256 : GCCBuiltin<"__builtin_ia32_rcpps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_round_pd_256 : GCCBuiltin<"__builtin_ia32_roundpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx_round_ps_256 : GCCBuiltin<"__builtin_ia32_roundps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_i32_ty], [IntrNoMem]>;
}
// Horizontal ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_hadd_pd_256 : GCCBuiltin<"__builtin_ia32_haddpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_hsub_ps_256 : GCCBuiltin<"__builtin_ia32_hsubps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_hsub_pd_256 : GCCBuiltin<"__builtin_ia32_hsubpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_hadd_ps_256 : GCCBuiltin<"__builtin_ia32_haddps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>;
}
// Vector permutation
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_vpermilvar_pd : GCCBuiltin<"__builtin_ia32_vpermilvarpd">,
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
llvm_v2i64_ty], [IntrNoMem]>;
def int_x86_avx_vpermilvar_ps : GCCBuiltin<"__builtin_ia32_vpermilvarps">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_avx_vpermilvar_pd_256 :
GCCBuiltin<"__builtin_ia32_vpermilvarpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4i64_ty], [IntrNoMem]>;
def int_x86_avx_vpermilvar_ps_256 :
GCCBuiltin<"__builtin_ia32_vpermilvarps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8i32_ty], [IntrNoMem]>;
def int_x86_avx_vperm2f128_pd_256 :
GCCBuiltin<"__builtin_ia32_vperm2f128_pd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx_vperm2f128_ps_256 :
Fix accidental edit to __builtin_ia32_vperm2f128_ps256's name git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143901 91177308-0d34-0410-b5e6-96231b3b80d8
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GCCBuiltin<"__builtin_ia32_vperm2f128_ps256">,
Support x86 AVX 256-bit instruction intrinsics. Right now support all of them, but as soon as we properly codegen the simple vector operations in clang, remove the unnecessary builti-ins/intrinsics from clang and llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110094 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx_vperm2f128_si_256 :
GCCBuiltin<"__builtin_ia32_vperm2f128_si256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;
}
// Vector blend
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_blend_pd_256 : GCCBuiltin<"__builtin_ia32_blendpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
Fix the last argument type of AVX vblend intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110628 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_v4f64_ty, llvm_i32_ty], [IntrNoMem]>;
Support x86 AVX 256-bit instruction intrinsics. Right now support all of them, but as soon as we properly codegen the simple vector operations in clang, remove the unnecessary builti-ins/intrinsics from clang and llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110094 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_blend_ps_256 : GCCBuiltin<"__builtin_ia32_blendps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
Fix the last argument type of AVX vblend intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110628 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_v8f32_ty, llvm_i32_ty], [IntrNoMem]>;
Support x86 AVX 256-bit instruction intrinsics. Right now support all of them, but as soon as we properly codegen the simple vector operations in clang, remove the unnecessary builti-ins/intrinsics from clang and llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110094 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_blendv_pd_256 : GCCBuiltin<"__builtin_ia32_blendvpd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v4f64_ty, llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_blendv_ps_256 : GCCBuiltin<"__builtin_ia32_blendvps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty, llvm_v8f32_ty], [IntrNoMem]>;
}
// Vector dot product
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_dp_ps_256 : GCCBuiltin<"__builtin_ia32_dpps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
Use i32 instead of i8 for dot product intrinsic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110643 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_v8f32_ty, llvm_i32_ty], [IntrNoMem]>;
Support x86 AVX 256-bit instruction intrinsics. Right now support all of them, but as soon as we properly codegen the simple vector operations in clang, remove the unnecessary builti-ins/intrinsics from clang and llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110094 91177308-0d34-0410-b5e6-96231b3b80d8
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}
// Vector compare
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_cmp_pd_256 : GCCBuiltin<"__builtin_ia32_cmppd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx_cmp_ps_256 : GCCBuiltin<"__builtin_ia32_cmpps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>;
}
// Vector extract and insert
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_vextractf128_pd_256 :
GCCBuiltin<"__builtin_ia32_vextractf128_pd256">,
Intrinsic<[llvm_v2f64_ty], [llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx_vextractf128_ps_256 :
GCCBuiltin<"__builtin_ia32_vextractf128_ps256">,
Intrinsic<[llvm_v4f32_ty], [llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx_vextractf128_si_256 :
GCCBuiltin<"__builtin_ia32_vextractf128_si256">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx_vinsertf128_pd_256 :
GCCBuiltin<"__builtin_ia32_vinsertf128_pd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty,
llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx_vinsertf128_ps_256 :
GCCBuiltin<"__builtin_ia32_vinsertf128_ps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx_vinsertf128_si_256 :
GCCBuiltin<"__builtin_ia32_vinsertf128_si256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>;
}
// Vector convert
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_cvtdq2_pd_256 : GCCBuiltin<"__builtin_ia32_cvtdq2pd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_avx_cvtdq2_ps_256 : GCCBuiltin<"__builtin_ia32_cvtdq2ps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8i32_ty], [IntrNoMem]>;
def int_x86_avx_cvt_pd2_ps_256 : GCCBuiltin<"__builtin_ia32_cvtpd2ps256">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_cvt_ps2dq_256 : GCCBuiltin<"__builtin_ia32_cvtps2dq256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_cvt_ps2_pd_256 : GCCBuiltin<"__builtin_ia32_cvtps2pd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_avx_cvtt_pd2dq_256 : GCCBuiltin<"__builtin_ia32_cvttpd2dq256">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_cvt_pd2dq_256 : GCCBuiltin<"__builtin_ia32_cvtpd2dq256">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_cvtt_ps2dq_256 : GCCBuiltin<"__builtin_ia32_cvttps2dq256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
}
// Vector bit test
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_vtestz_pd : GCCBuiltin<"__builtin_ia32_vtestzpd">,
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_avx_vtestc_pd : GCCBuiltin<"__builtin_ia32_vtestcpd">,
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_avx_vtestnzc_pd : GCCBuiltin<"__builtin_ia32_vtestnzcpd">,
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty,
llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_avx_vtestz_ps : GCCBuiltin<"__builtin_ia32_vtestzps">,
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_avx_vtestc_ps : GCCBuiltin<"__builtin_ia32_vtestcps">,
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_avx_vtestnzc_ps : GCCBuiltin<"__builtin_ia32_vtestnzcps">,
Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty,
llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_avx_vtestz_pd_256 : GCCBuiltin<"__builtin_ia32_vtestzpd256">,
Intrinsic<[llvm_i32_ty], [llvm_v4f64_ty,
llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_vtestc_pd_256 : GCCBuiltin<"__builtin_ia32_vtestcpd256">,
Intrinsic<[llvm_i32_ty], [llvm_v4f64_ty,
llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_vtestnzc_pd_256 : GCCBuiltin<"__builtin_ia32_vtestnzcpd256">,
Intrinsic<[llvm_i32_ty], [llvm_v4f64_ty,
llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_vtestz_ps_256 : GCCBuiltin<"__builtin_ia32_vtestzps256">,
Intrinsic<[llvm_i32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_vtestc_ps_256 : GCCBuiltin<"__builtin_ia32_vtestcps256">,
Intrinsic<[llvm_i32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_vtestnzc_ps_256 : GCCBuiltin<"__builtin_ia32_vtestnzcps256">,
Intrinsic<[llvm_i32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>;
def int_x86_avx_ptestz_256 : GCCBuiltin<"__builtin_ia32_ptestz256">,
Intrinsic<[llvm_i32_ty], [llvm_v4i64_ty,
llvm_v4i64_ty], [IntrNoMem]>;
def int_x86_avx_ptestc_256 : GCCBuiltin<"__builtin_ia32_ptestc256">,
Intrinsic<[llvm_i32_ty], [llvm_v4i64_ty,
llvm_v4i64_ty], [IntrNoMem]>;
def int_x86_avx_ptestnzc_256 : GCCBuiltin<"__builtin_ia32_ptestnzc256">,
Intrinsic<[llvm_i32_ty], [llvm_v4i64_ty,
llvm_v4i64_ty], [IntrNoMem]>;
}
// Vector extract sign mask
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_movmsk_pd_256 : GCCBuiltin<"__builtin_ia32_movmskpd256">,
Intrinsic<[llvm_i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;
def int_x86_avx_movmsk_ps_256 : GCCBuiltin<"__builtin_ia32_movmskps256">,
Intrinsic<[llvm_i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
}
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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// Vector zero
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_vzeroall : GCCBuiltin<"__builtin_ia32_vzeroall">,
Patterns to match AVX 256-bit vzero intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110480 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[], [], []>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_vzeroupper : GCCBuiltin<"__builtin_ia32_vzeroupper">,
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Intrinsic<[], [], []>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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}
// Vector load with broadcast
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Add new X86 AVX2 VBROADCAST instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143612 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_vbroadcast_ss :
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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GCCBuiltin<"__builtin_ia32_vbroadcastss">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_vbroadcast_sd_256 :
GCCBuiltin<"__builtin_ia32_vbroadcastsd256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
Add new X86 AVX2 VBROADCAST instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143612 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_vbroadcast_ss_256 :
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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GCCBuiltin<"__builtin_ia32_vbroadcastss256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_vbroadcastf128_pd_256 :
GCCBuiltin<"__builtin_ia32_vbroadcastf128_pd256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_vbroadcastf128_ps_256 :
GCCBuiltin<"__builtin_ia32_vbroadcastf128_ps256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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}
// SIMD load ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_ldu_dq_256 : GCCBuiltin<"__builtin_ia32_lddqu256">,
Intrinsic<[llvm_v32i8_ty], [llvm_ptr_ty], [IntrReadMem]>;
}
// SIMD store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_storeu_pd_256 : GCCBuiltin<"__builtin_ia32_storeupd256">,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], [IntrReadWriteArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_storeu_ps_256 : GCCBuiltin<"__builtin_ia32_storeups256">,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], [IntrReadWriteArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_storeu_dq_256 : GCCBuiltin<"__builtin_ia32_storedqu256">,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[], [llvm_ptr_ty, llvm_v32i8_ty], [IntrReadWriteArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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}
// Conditional load ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_maskload_pd : GCCBuiltin<"__builtin_ia32_maskloadpd">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty, llvm_v2f64_ty],
[IntrReadArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_maskload_ps : GCCBuiltin<"__builtin_ia32_maskloadps">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty, llvm_v4f32_ty],
[IntrReadArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_maskload_pd_256 : GCCBuiltin<"__builtin_ia32_maskloadpd256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty, llvm_v4f64_ty],
[IntrReadArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_maskload_ps_256 : GCCBuiltin<"__builtin_ia32_maskloadps256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty, llvm_v8f32_ty],
[IntrReadArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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}
// Conditional store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx_maskstore_pd : GCCBuiltin<"__builtin_ia32_maskstorepd">,
Intrinsic<[], [llvm_ptr_ty,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_v2f64_ty, llvm_v2f64_ty], [IntrReadWriteArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_maskstore_ps : GCCBuiltin<"__builtin_ia32_maskstoreps">,
Intrinsic<[], [llvm_ptr_ty,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_v4f32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_maskstore_pd_256 :
GCCBuiltin<"__builtin_ia32_maskstorepd256">,
Intrinsic<[], [llvm_ptr_ty,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_v4f64_ty, llvm_v4f64_ty], [IntrReadWriteArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx_maskstore_ps_256 :
GCCBuiltin<"__builtin_ia32_maskstoreps256">,
Intrinsic<[], [llvm_ptr_ty,
Fix attributes on X86 store intrinsics. These intrinsics don't have unmodeled side effects, they are just stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459 91177308-0d34-0410-b5e6-96231b3b80d8
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llvm_v8f32_ty, llvm_v8f32_ty], [IntrReadWriteArgMem]>;
Fix a comment typo and add more 256-bit intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110177 91177308-0d34-0410-b5e6-96231b3b80d8
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}
Begin adding AVX2 instructions. No selection support yet other than intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
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//===----------------------------------------------------------------------===//
// AVX2
// Integer arithmetic ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_padds_b : GCCBuiltin<"__builtin_ia32_paddsb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_padds_w : GCCBuiltin<"__builtin_ia32_paddsw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_paddus_b : GCCBuiltin<"__builtin_ia32_paddusb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem]>;
def int_x86_avx2_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem]>;
def int_x86_avx2_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem]>;
def int_x86_avx2_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem]>;
def int_x86_avx2_pmulhu_w : GCCBuiltin<"__builtin_ia32_pmulhuw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pmulu_dq : GCCBuiltin<"__builtin_ia32_pmuludq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem, Commutative]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx2_pmul_dq : GCCBuiltin<"__builtin_ia32_pmuldq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem, Commutative]>;
Begin adding AVX2 instructions. No selection support yet other than intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx2_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pavg_b : GCCBuiltin<"__builtin_ia32_pavgb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx2_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem, Commutative]>;
}
// Vector min, max
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Begin adding AVX2 instructions. No selection support yet other than intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx2_pmaxu_b : GCCBuiltin<"__builtin_ia32_pmaxub256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem, Commutative]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
def int_x86_avx2_pmaxu_w : GCCBuiltin<"__builtin_ia32_pmaxuw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pmaxu_d : GCCBuiltin<"__builtin_ia32_pmaxud256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pmaxs_b : GCCBuiltin<"__builtin_ia32_pmaxsb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem, Commutative]>;
Begin adding AVX2 instructions. No selection support yet other than intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_avx2_pmaxs_w : GCCBuiltin<"__builtin_ia32_pmaxsw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
def int_x86_avx2_pmaxs_d : GCCBuiltin<"__builtin_ia32_pmaxsd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem, Commutative]>;
Begin adding AVX2 instructions. No selection support yet other than intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-31 02:15:10 +00:00
def int_x86_avx2_pminu_b : GCCBuiltin<"__builtin_ia32_pminub256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem, Commutative]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
def int_x86_avx2_pminu_w : GCCBuiltin<"__builtin_ia32_pminuw256">,
Begin adding AVX2 instructions. No selection support yet other than intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-31 02:15:10 +00:00
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
def int_x86_avx2_pminu_d : GCCBuiltin<"__builtin_ia32_pminud256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pmins_b : GCCBuiltin<"__builtin_ia32_pminsb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
Begin adding AVX2 instructions. No selection support yet other than intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-31 02:15:10 +00:00
llvm_v32i8_ty], [IntrNoMem, Commutative]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
def int_x86_avx2_pmins_w : GCCBuiltin<"__builtin_ia32_pminsw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pmins_d : GCCBuiltin<"__builtin_ia32_pminsd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem, Commutative]>;
Begin adding AVX2 instructions. No selection support yet other than intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-31 02:15:10 +00:00
}
// Integer shift ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_psll_w : GCCBuiltin<"__builtin_ia32_psllw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_avx2_psll_d : GCCBuiltin<"__builtin_ia32_pslld256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_avx2_psll_q : GCCBuiltin<"__builtin_ia32_psllq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_v2i64_ty], [IntrNoMem]>;
def int_x86_avx2_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_avx2_psrl_d : GCCBuiltin<"__builtin_ia32_psrld256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_avx2_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_v2i64_ty], [IntrNoMem]>;
def int_x86_avx2_psra_w : GCCBuiltin<"__builtin_ia32_psraw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_avx2_psra_d : GCCBuiltin<"__builtin_ia32_psrad256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_avx2_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_psrai_d : GCCBuiltin<"__builtin_ia32_psradi256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_psll_dq_bs : GCCBuiltin<"__builtin_ia32_pslldqi256_byteshift">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_psrl_dq_bs : GCCBuiltin<"__builtin_ia32_psrldqi256_byteshift">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_i32_ty], [IntrNoMem]>;
}
// Pack ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_packsswb : GCCBuiltin<"__builtin_ia32_packsswb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem]>;
def int_x86_avx2_packssdw : GCCBuiltin<"__builtin_ia32_packssdw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem]>;
def int_x86_avx2_packuswb : GCCBuiltin<"__builtin_ia32_packuswb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
def int_x86_avx2_packusdw : GCCBuiltin<"__builtin_ia32_packusdw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem]>;
Begin adding AVX2 instructions. No selection support yet other than intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-31 02:15:10 +00:00
}
Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143529 91177308-0d34-0410-b5e6-96231b3b80d8
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// Absolute value ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_pabs_b : GCCBuiltin<"__builtin_ia32_pabsb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty], [IntrNoMem]>;
def int_x86_avx2_pabs_w : GCCBuiltin<"__builtin_ia32_pabsw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty], [IntrNoMem]>;
def int_x86_avx2_pabs_d : GCCBuiltin<"__builtin_ia32_pabsd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty], [IntrNoMem]>;
}
// Horizontal arithmetic ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_phadd_w : GCCBuiltin<"__builtin_ia32_phaddw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem]>;
def int_x86_avx2_phadd_d : GCCBuiltin<"__builtin_ia32_phaddd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem]>;
def int_x86_avx2_phadd_sw : GCCBuiltin<"__builtin_ia32_phaddsw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem]>;
def int_x86_avx2_phsub_w : GCCBuiltin<"__builtin_ia32_phsubw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem]>;
def int_x86_avx2_phsub_d : GCCBuiltin<"__builtin_ia32_phsubd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem]>;
def int_x86_avx2_phsub_sw : GCCBuiltin<"__builtin_ia32_phsubsw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem]>;
def int_x86_avx2_pmadd_ub_sw : GCCBuiltin<"__builtin_ia32_pmaddubsw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem]>;
}
// Sign ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_psign_b : GCCBuiltin<"__builtin_ia32_psignb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem]>;
def int_x86_avx2_psign_w : GCCBuiltin<"__builtin_ia32_psignw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem]>;
def int_x86_avx2_psign_d : GCCBuiltin<"__builtin_ia32_psignd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
llvm_v8i32_ty], [IntrNoMem]>;
}
// Packed multiply high with round and scale
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_pmul_hr_sw : GCCBuiltin<"__builtin_ia32_pmulhrsw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
}
// Vector sign and zero extend
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_pmovsxbd : GCCBuiltin<"__builtin_ia32_pmovsxbd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovsxbq : GCCBuiltin<"__builtin_ia32_pmovsxbq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovsxbw : GCCBuiltin<"__builtin_ia32_pmovsxbw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovsxdq : GCCBuiltin<"__builtin_ia32_pmovsxdq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovsxwd : GCCBuiltin<"__builtin_ia32_pmovsxwd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovsxwq : GCCBuiltin<"__builtin_ia32_pmovsxwq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovzxbd : GCCBuiltin<"__builtin_ia32_pmovzxbd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovzxbq : GCCBuiltin<"__builtin_ia32_pmovzxbq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovzxbw : GCCBuiltin<"__builtin_ia32_pmovzxbw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovzxdq : GCCBuiltin<"__builtin_ia32_pmovzxdq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovzxwd : GCCBuiltin<"__builtin_ia32_pmovzxwd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_avx2_pmovzxwq : GCCBuiltin<"__builtin_ia32_pmovzxwq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v8i16_ty],
[IntrNoMem]>;
}
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
// Vector blend
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_pblendvb : GCCBuiltin<"__builtin_ia32_pblendvb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty, llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem]>;
def int_x86_avx2_pblendw : GCCBuiltin<"__builtin_ia32_pblendw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_v16i16_ty,
llvm_i32_ty], [IntrNoMem]>;
Add more AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06 06:12:20 +00:00
def int_x86_avx2_pblendd_128 : GCCBuiltin<"__builtin_ia32_pblendd128">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_avx2_pblendd_256 : GCCBuiltin<"__builtin_ia32_pblendd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty,
llvm_i32_ty], [IntrNoMem]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
}
// Vector load with broadcast
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Add new X86 AVX2 VBROADCAST instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143612 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-03 07:35:53 +00:00
def int_x86_avx2_vbroadcast_ss_ps :
Add more AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06 06:12:20 +00:00
GCCBuiltin<"__builtin_ia32_vbroadcastss_ps">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Add new X86 AVX2 VBROADCAST instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143612 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-03 07:35:53 +00:00
def int_x86_avx2_vbroadcast_sd_pd_256 :
Add more AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06 06:12:20 +00:00
GCCBuiltin<"__builtin_ia32_vbroadcastsd_pd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Add new X86 AVX2 VBROADCAST instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143612 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-03 07:35:53 +00:00
def int_x86_avx2_vbroadcast_ss_ps_256 :
Add more AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06 06:12:20 +00:00
GCCBuiltin<"__builtin_ia32_vbroadcastss_ps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
def int_x86_avx2_vbroadcasti128 :
Add more AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06 06:12:20 +00:00
GCCBuiltin<"__builtin_ia32_vbroadcastsi256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
Add more AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06 06:12:20 +00:00
def int_x86_avx2_pbroadcastb_128 :
GCCBuiltin<"__builtin_ia32_pbroadcastb128">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastb_256 :
GCCBuiltin<"__builtin_ia32_pbroadcastb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastw_128 :
GCCBuiltin<"__builtin_ia32_pbroadcastw128">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastw_256 :
GCCBuiltin<"__builtin_ia32_pbroadcastw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastd_128 :
GCCBuiltin<"__builtin_ia32_pbroadcastd128">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastd_256 :
GCCBuiltin<"__builtin_ia32_pbroadcastd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastq_128 :
GCCBuiltin<"__builtin_ia32_pbroadcastq128">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
def int_x86_avx2_pbroadcastq_256 :
GCCBuiltin<"__builtin_ia32_pbroadcastq256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
}
More AVX2 instructions and their intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06 23:04:08 +00:00
// Vector permutation
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_permd : GCCBuiltin<"__builtin_ia32_permvarsi256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
[IntrNoMem]>;
def int_x86_avx2_permps : GCCBuiltin<"__builtin_ia32_permvarsf256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>;
def int_x86_avx2_vperm2i128 : GCCBuiltin<"__builtin_ia32_permti256">,
Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 02:00:04 +00:00
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>;
More AVX2 instructions and their intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-06 23:04:08 +00:00
}
Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 02:00:04 +00:00
// Vector extract and insert
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_vextracti128 : GCCBuiltin<"__builtin_ia32_extract128i256">,
Intrinsic<[llvm_v2i64_ty], [llvm_v4i64_ty,
llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx2_vinserti128 : GCCBuiltin<"__builtin_ia32_insert128i256">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
}
Add AVX2 VPMOVMASK instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 03:20:35 +00:00
// Conditional load ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_maskload_d : GCCBuiltin<"__builtin_ia32_maskloadd">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_v4i32_ty],
[IntrReadArgMem]>;
Add AVX2 VPMOVMASK instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 03:20:35 +00:00
def int_x86_avx2_maskload_q : GCCBuiltin<"__builtin_ia32_maskloadq">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_v2i64_ty],
[IntrReadArgMem]>;
Add AVX2 VPMOVMASK instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 03:20:35 +00:00
def int_x86_avx2_maskload_d_256 : GCCBuiltin<"__builtin_ia32_maskloadd256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Intrinsic<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_v8i32_ty],
[IntrReadArgMem]>;
Add AVX2 VPMOVMASK instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 03:20:35 +00:00
def int_x86_avx2_maskload_q_256 : GCCBuiltin<"__builtin_ia32_maskloadq256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_v4i64_ty],
[IntrReadArgMem]>;
Add AVX2 VPMOVMASK instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 03:20:35 +00:00
}
// Conditional store ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_maskstore_d : GCCBuiltin<"__builtin_ia32_maskstored">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Intrinsic<[], [llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty],
[IntrReadWriteArgMem]>;
Add AVX2 VPMOVMASK instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 03:20:35 +00:00
def int_x86_avx2_maskstore_q : GCCBuiltin<"__builtin_ia32_maskstoreq">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Intrinsic<[], [llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty],
[IntrReadWriteArgMem]>;
Add AVX2 VPMOVMASK instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 03:20:35 +00:00
def int_x86_avx2_maskstore_d_256 :
GCCBuiltin<"__builtin_ia32_maskstored256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Intrinsic<[], [llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty],
[IntrReadWriteArgMem]>;
Add AVX2 VPMOVMASK instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 03:20:35 +00:00
def int_x86_avx2_maskstore_q_256 :
GCCBuiltin<"__builtin_ia32_maskstoreq256">,
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26 22:01:42 +00:00
Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty],
[IntrReadWriteArgMem]>;
Add AVX2 VPMOVMASK instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 03:20:35 +00:00
}
Add AVX2 variable shift instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 08:26:24 +00:00
// Variable bit shift ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_psllv_d : GCCBuiltin<"__builtin_ia32_psllv4si">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_avx2_psllv_d_256 : GCCBuiltin<"__builtin_ia32_psllv8si">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
[IntrNoMem]>;
def int_x86_avx2_psllv_q : GCCBuiltin<"__builtin_ia32_psllv2di">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_avx2_psllv_q_256 : GCCBuiltin<"__builtin_ia32_psllv4di">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty],
[IntrNoMem]>;
def int_x86_avx2_psrlv_d : GCCBuiltin<"__builtin_ia32_psrlv4si">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_avx2_psrlv_d_256 : GCCBuiltin<"__builtin_ia32_psrlv8si">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
[IntrNoMem]>;
def int_x86_avx2_psrlv_q : GCCBuiltin<"__builtin_ia32_psrlv2di">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_avx2_psrlv_q_256 : GCCBuiltin<"__builtin_ia32_psrlv4di">,
Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty],
[IntrNoMem]>;
def int_x86_avx2_psrav_d : GCCBuiltin<"__builtin_ia32_psrav4si">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_avx2_psrav_d_256 : GCCBuiltin<"__builtin_ia32_psrav8si">,
Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
[IntrNoMem]>;
}
X86: add GATHER intrinsics (AVX2) in LLVM Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26 19:47:59 +00:00
// Gather ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_gather_d_pd : GCCBuiltin<"__builtin_ia32_gatherd_pd">,
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v2f64_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_pd_256 : GCCBuiltin<"__builtin_ia32_gatherd_pd256">,
Intrinsic<[llvm_v4f64_ty],
X86: add more GATHER intrinsics in LLVM Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29 00:54:20 +00:00
[llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4f64_ty, llvm_i8_ty],
X86: add GATHER intrinsics (AVX2) in LLVM Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26 19:47:59 +00:00
[IntrReadMem]>;
def int_x86_avx2_gather_q_pd : GCCBuiltin<"__builtin_ia32_gatherq_pd">,
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v2f64_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_pd_256 : GCCBuiltin<"__builtin_ia32_gatherq_pd256">,
Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4f64_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_ps : GCCBuiltin<"__builtin_ia32_gatherd_ps">,
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4f32_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_ps_256 : GCCBuiltin<"__builtin_ia32_gatherd_ps256">,
Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_v8f32_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_ps : GCCBuiltin<"__builtin_ia32_gatherq_ps">,
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v4f32_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_ps_256 : GCCBuiltin<"__builtin_ia32_gatherq_ps256">,
X86: add more GATHER intrinsics in LLVM Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29 00:54:20 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4f32_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_q : GCCBuiltin<"__builtin_ia32_gatherd_q">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v2i64_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_q_256 : GCCBuiltin<"__builtin_ia32_gatherd_q256">,
Intrinsic<[llvm_v4i64_ty],
[llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i64_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_q : GCCBuiltin<"__builtin_ia32_gatherq_q">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_q_256 : GCCBuiltin<"__builtin_ia32_gatherq_q256">,
Intrinsic<[llvm_v4i64_ty],
[llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_d : GCCBuiltin<"__builtin_ia32_gatherd_d">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_d_d_256 : GCCBuiltin<"__builtin_ia32_gatherd_d256">,
Intrinsic<[llvm_v8i32_ty],
[llvm_v8i32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_d : GCCBuiltin<"__builtin_ia32_gatherq_d">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_ty],
[IntrReadMem]>;
def int_x86_avx2_gather_q_d_256 : GCCBuiltin<"__builtin_ia32_gatherq_d256">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_ty],
X86: add GATHER intrinsics (AVX2) in LLVM Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26 19:47:59 +00:00
[IntrReadMem]>;
}
Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 04:42:13 +00:00
// Misc.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx2_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb256">,
Intrinsic<[llvm_i32_ty], [llvm_v32i8_ty], [IntrNoMem]>;
def int_x86_avx2_pshuf_b : GCCBuiltin<"__builtin_ia32_pshufb256">,
Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
llvm_v32i8_ty], [IntrNoMem]>;
More AVX2 instructions and intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 06:54:17 +00:00
def int_x86_avx2_mpsadbw : GCCBuiltin<"__builtin_ia32_mpsadbw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v32i8_ty, llvm_v32i8_ty,
llvm_i32_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_movntdqa : GCCBuiltin<"__builtin_ia32_movntdqa256">,
Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadMem]>;
Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02 04:42:13 +00:00
}
This patch contains support for encoding FMA4 instructions and tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-25 19:33:42 +00:00
//===----------------------------------------------------------------------===//
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
// FMA3 and FMA4
This patch contains support for encoding FMA4 instructions and tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-25 19:33:42 +00:00
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmadd_ss : GCCBuiltin<"__builtin_ia32_vfmaddss">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmadd_sd : GCCBuiltin<"__builtin_ia32_vfmaddsd">,
This patch contains support for encoding FMA4 instructions and tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-25 19:33:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmadd_ps : GCCBuiltin<"__builtin_ia32_vfmaddps">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmadd_pd : GCCBuiltin<"__builtin_ia32_vfmaddpd">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfmaddps256">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfmaddpd256">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsub_ss : GCCBuiltin<"__builtin_ia32_vfmsubss">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsub_sd : GCCBuiltin<"__builtin_ia32_vfmsubsd">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsub_ps : GCCBuiltin<"__builtin_ia32_vfmsubps">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsub_pd : GCCBuiltin<"__builtin_ia32_vfmsubpd">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfmsubps256">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfmsubpd256">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmadd_ss : GCCBuiltin<"__builtin_ia32_vfnmaddss">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmadd_sd : GCCBuiltin<"__builtin_ia32_vfnmaddsd">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmadd_ps : GCCBuiltin<"__builtin_ia32_vfnmaddps">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmadd_pd : GCCBuiltin<"__builtin_ia32_vfnmaddpd">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmaddps256">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmaddpd256">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmsub_ss : GCCBuiltin<"__builtin_ia32_vfnmsubss">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmsub_sd : GCCBuiltin<"__builtin_ia32_vfnmsubsd">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmsub_ps : GCCBuiltin<"__builtin_ia32_vfnmsubps">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmsub_pd : GCCBuiltin<"__builtin_ia32_vfnmsubpd">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmsubps256">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfnmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmsubpd256">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmaddsub_ps : GCCBuiltin<"__builtin_ia32_vfmaddsubps">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmaddsub_pd : GCCBuiltin<"__builtin_ia32_vfmaddsubpd">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmaddsub_ps_256 :
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
GCCBuiltin<"__builtin_ia32_vfmaddsubps256">,
Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmaddsub_pd_256 :
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
GCCBuiltin<"__builtin_ia32_vfmaddsubpd256">,
Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsubadd_ps : GCCBuiltin<"__builtin_ia32_vfmsubaddps">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsubadd_pd : GCCBuiltin<"__builtin_ia32_vfmsubaddpd">,
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Intrinsic<[llvm_v2f64_ty],
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsubadd_ps_256 :
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
GCCBuiltin<"__builtin_ia32_vfmsubaddps256">,
Intrinsic<[llvm_v8f32_ty],
[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
[IntrNoMem]>;
Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03 07:26:46 +00:00
def int_x86_fma_vfmsubadd_pd_256 :
Support for encoding all FMA4 instructions and tablegen patterns for all remaining FMA4 instructions and intrinsics with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
GCCBuiltin<"__builtin_ia32_vfmsubaddpd256">,
Intrinsic<[llvm_v4f64_ty],
[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
[IntrNoMem]>;
This patch contains support for encoding FMA4 instructions and tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
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}
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//===----------------------------------------------------------------------===//
// XOP
def int_x86_xop_vpermil2pd : GCCBuiltin<"__builtin_ia32_vpermil2pd">,
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
llvm_v2f64_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpermil2pd_256 :
GCCBuiltin<"__builtin_ia32_vpermil2pd256">,
Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty,
llvm_v4f64_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpermil2ps : GCCBuiltin<"__builtin_ia32_vpermil2ps">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpermil2ps_256 :
GCCBuiltin<"__builtin_ia32_vpermil2ps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty,
llvm_v8f32_ty, llvm_i8_ty],
[IntrNoMem]>;
Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158396 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vfrcz_pd : GCCBuiltin<"__builtin_ia32_vfrczpd">,
Add XOP Intrinsics and tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-13 07:18:53 +00:00
def int_x86_xop_vfrcz_ps : GCCBuiltin<"__builtin_ia32_vfrczps">,
Add XOP Intrinsics and tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158396 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vfrcz_sd : GCCBuiltin<"__builtin_ia32_vfrczsd">,
Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
def int_x86_xop_vfrcz_ss : GCCBuiltin<"__builtin_ia32_vfrczss">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_x86_xop_vfrcz_pd_256 : GCCBuiltin<"__builtin_ia32_vfrczpd256">,
Add XOP Intrinsics and tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty], [IntrNoMem]>;
Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158396 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vfrcz_ps_256 : GCCBuiltin<"__builtin_ia32_vfrczps256">,
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Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>;
Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-13 07:18:53 +00:00
Add XOP Intrinsics and tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vpcmov :
GCCBuiltin<"__builtin_ia32_vpcmov">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpcmov_256 :
GCCBuiltin<"__builtin_ia32_vpcmov_256">,
Intrinsic<[llvm_v4i64_ty],
[llvm_v4i64_ty, llvm_v4i64_ty, llvm_v4i64_ty],
[IntrNoMem]>;
Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate as an argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158278 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vpcomb : GCCBuiltin<"__builtin_ia32_vpcomb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,
llvm_i8_ty], [IntrNoMem]>;
def int_x86_xop_vpcomw : GCCBuiltin<"__builtin_ia32_vpcomw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_i8_ty], [IntrNoMem]>;
def int_x86_xop_vpcomd : GCCBuiltin<"__builtin_ia32_vpcomd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
llvm_i8_ty], [IntrNoMem]>;
def int_x86_xop_vpcomq : GCCBuiltin<"__builtin_ia32_vpcomq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
llvm_i8_ty], [IntrNoMem]>;
def int_x86_xop_vpcomub : GCCBuiltin<"__builtin_ia32_vpcomub">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,
llvm_i8_ty], [IntrNoMem]>;
def int_x86_xop_vpcomuw : GCCBuiltin<"__builtin_ia32_vpcomuw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_i8_ty], [IntrNoMem]>;
def int_x86_xop_vpcomud : GCCBuiltin<"__builtin_ia32_vpcomud">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
llvm_i8_ty], [IntrNoMem]>;
def int_x86_xop_vpcomuq : GCCBuiltin<"__builtin_ia32_vpcomuq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
llvm_i8_ty], [IntrNoMem]>;
Add XOP Intrinsics and tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vphaddbd :
GCCBuiltin<"__builtin_ia32_vphaddbd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphaddbq :
GCCBuiltin<"__builtin_ia32_vphaddbq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphaddbw :
GCCBuiltin<"__builtin_ia32_vphaddbw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphadddq :
GCCBuiltin<"__builtin_ia32_vphadddq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_xop_vphaddubd :
GCCBuiltin<"__builtin_ia32_vphaddubd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphaddubq :
GCCBuiltin<"__builtin_ia32_vphaddubq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphaddubw :
GCCBuiltin<"__builtin_ia32_vphaddubw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphaddudq :
GCCBuiltin<"__builtin_ia32_vphaddudq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_xop_vphadduwd :
GCCBuiltin<"__builtin_ia32_vphadduwd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_xop_vphadduwq :
GCCBuiltin<"__builtin_ia32_vphadduwq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_xop_vphaddwd :
GCCBuiltin<"__builtin_ia32_vphaddwd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_xop_vphaddwq :
GCCBuiltin<"__builtin_ia32_vphaddwq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_xop_vphsubbw :
GCCBuiltin<"__builtin_ia32_vphsubbw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_xop_vphsubdq :
GCCBuiltin<"__builtin_ia32_vphsubdq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
def int_x86_xop_vphsubwd :
GCCBuiltin<"__builtin_ia32_vphsubwd">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_xop_vpmacsdd :
GCCBuiltin<"__builtin_ia32_vpmacsdd">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpmacsdqh :
GCCBuiltin<"__builtin_ia32_vpmacsdqh">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpmacsdql :
GCCBuiltin<"__builtin_ia32_vpmacsdql">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpmacssdd :
GCCBuiltin<"__builtin_ia32_vpmacssdd">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpmacssdqh :
GCCBuiltin<"__builtin_ia32_vpmacssdqh">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpmacssdql :
GCCBuiltin<"__builtin_ia32_vpmacssdql">,
Intrinsic<[llvm_v2i64_ty],
[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpmacsswd :
GCCBuiltin<"__builtin_ia32_vpmacsswd">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpmacssww :
GCCBuiltin<"__builtin_ia32_vpmacssww">,
Intrinsic<[llvm_v8i16_ty],
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpmacswd :
GCCBuiltin<"__builtin_ia32_vpmacswd">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpmacsww :
GCCBuiltin<"__builtin_ia32_vpmacsww">,
Intrinsic<[llvm_v8i16_ty],
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpmadcsswd :
GCCBuiltin<"__builtin_ia32_vpmadcsswd">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpmadcswd :
GCCBuiltin<"__builtin_ia32_vpmadcswd">,
Intrinsic<[llvm_v4i32_ty],
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpperm :
GCCBuiltin<"__builtin_ia32_vpperm">,
Intrinsic<[llvm_v16i8_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-10 07:31:56 +00:00
def int_x86_xop_vprotb : GCCBuiltin<"__builtin_ia32_vprotb">,
Add XOP Intrinsics and tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158291 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vprotd : GCCBuiltin<"__builtin_ia32_vprotd">,
Add XOP Intrinsics and tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158291 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vprotq : GCCBuiltin<"__builtin_ia32_vprotq">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-10 07:31:56 +00:00
def int_x86_xop_vprotw : GCCBuiltin<"__builtin_ia32_vprotw">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158291 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vprotbi : GCCBuiltin<"__builtin_ia32_vprotbi">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vprotdi : GCCBuiltin<"__builtin_ia32_vprotdi">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vprotqi : GCCBuiltin<"__builtin_ia32_vprotqi">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_xop_vprotwi : GCCBuiltin<"__builtin_ia32_vprotwi">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i8_ty],
[IntrNoMem]>;
Add XOP Intrinsics and tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147949 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_xop_vpshab :
GCCBuiltin<"__builtin_ia32_vpshab">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpshad :
GCCBuiltin<"__builtin_ia32_vpshad">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpshaq :
GCCBuiltin<"__builtin_ia32_vpshaq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpshaw :
GCCBuiltin<"__builtin_ia32_vpshaw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
def int_x86_xop_vpshlb :
GCCBuiltin<"__builtin_ia32_vpshlb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
def int_x86_xop_vpshld :
GCCBuiltin<"__builtin_ia32_vpshld">,
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
[IntrNoMem]>;
def int_x86_xop_vpshlq :
GCCBuiltin<"__builtin_ia32_vpshlq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
def int_x86_xop_vpshlw :
GCCBuiltin<"__builtin_ia32_vpshlw">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
Add the emms intrinsic for MMX support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34938 91177308-0d34-0410-b5e6-96231b3b80d8
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//===----------------------------------------------------------------------===//
// MMX
// Empty MMX state op.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35616 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_mmx_emms : GCCBuiltin<"__builtin_ia32_emms">,
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 23:36:21 +00:00
Intrinsic<[], [], []>;
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35616 91177308-0d34-0410-b5e6-96231b3b80d8
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def int_x86_mmx_femms : GCCBuiltin<"__builtin_ia32_femms">,
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
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Intrinsic<[], [], []>;
Add the emms intrinsic for MMX support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34938 91177308-0d34-0410-b5e6-96231b3b80d8
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}
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that moves, loads, etc. are recognized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-08 22:09:11 +00:00
// Integer arithmetic ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Adding more arithmetic operators to MMX. This is an almost exact copy of the addition. Please let me know if you have suggestions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-10 09:57:05 +00:00
// Addition
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
def int_x86_mmx_padd_b : GCCBuiltin<"__builtin_ia32_paddb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_padd_w : GCCBuiltin<"__builtin_ia32_paddw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_padd_d : GCCBuiltin<"__builtin_ia32_paddd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_padd_q : GCCBuiltin<"__builtin_ia32_paddq">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that moves, loads, etc. are recognized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-08 22:09:11 +00:00
def int_x86_mmx_padds_b : GCCBuiltin<"__builtin_ia32_paddsb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that moves, loads, etc. are recognized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-08 22:09:11 +00:00
def int_x86_mmx_padds_w : GCCBuiltin<"__builtin_ia32_paddsw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that moves, loads, etc. are recognized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-08 22:09:11 +00:00
def int_x86_mmx_paddus_b : GCCBuiltin<"__builtin_ia32_paddusb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that moves, loads, etc. are recognized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-08 22:09:11 +00:00
def int_x86_mmx_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more arithmetic operators to MMX. This is an almost exact copy of the addition. Please let me know if you have suggestions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-10 09:57:05 +00:00
// Subtraction
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
def int_x86_mmx_psub_b : GCCBuiltin<"__builtin_ia32_psubb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_psub_w : GCCBuiltin<"__builtin_ia32_psubw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_psub_d : GCCBuiltin<"__builtin_ia32_psubd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_psub_q : GCCBuiltin<"__builtin_ia32_psubq">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
Adding more arithmetic operators to MMX. This is an almost exact copy of the addition. Please let me know if you have suggestions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-10 09:57:05 +00:00
def int_x86_mmx_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding more arithmetic operators to MMX. This is an almost exact copy of the addition. Please let me know if you have suggestions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-10 09:57:05 +00:00
def int_x86_mmx_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding more arithmetic operators to MMX. This is an almost exact copy of the addition. Please let me know if you have suggestions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-10 09:57:05 +00:00
def int_x86_mmx_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Adding more arithmetic operators to MMX. This is an almost exact copy of the addition. Please let me know if you have suggestions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-10 09:57:05 +00:00
def int_x86_mmx_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Multiplication support for MMX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35118 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-15 21:24:36 +00:00
// Multiplication
def int_x86_mmx_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
def int_x86_mmx_pmull_w : GCCBuiltin<"__builtin_ia32_pmullw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
def int_x86_mmx_pmulhu_w : GCCBuiltin<"__builtin_ia32_pmulhuw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
def int_x86_mmx_pmulu_dq : GCCBuiltin<"__builtin_ia32_pmuludq">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Multiplication support for MMX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35118 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-15 21:24:36 +00:00
def int_x86_mmx_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
// Bitwise operations
def int_x86_mmx_pand : GCCBuiltin<"__builtin_ia32_pand">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_pandn : GCCBuiltin<"__builtin_ia32_pandn">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_por : GCCBuiltin<"__builtin_ia32_por">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_pxor : GCCBuiltin<"__builtin_ia32_pxor">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
// Averages
def int_x86_mmx_pavg_b : GCCBuiltin<"__builtin_ia32_pavgb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
def int_x86_mmx_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
// Maximum
def int_x86_mmx_pmaxu_b : GCCBuiltin<"__builtin_ia32_pmaxub">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
def int_x86_mmx_pmaxs_w : GCCBuiltin<"__builtin_ia32_pmaxsw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
// Minimum
def int_x86_mmx_pminu_b : GCCBuiltin<"__builtin_ia32_pminub">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
def int_x86_mmx_pmins_w : GCCBuiltin<"__builtin_ia32_pminsw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
// Packed sum of absolute differences
def int_x86_mmx_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that moves, loads, etc. are recognized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-08 22:09:11 +00:00
}
Support added for shifts and unpacking MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22 18:42:45 +00:00
// Integer shift ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Shift left logical
def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Support added for shifts and unpacking MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22 18:42:45 +00:00
def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Support added for shifts and unpacking MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22 18:42:45 +00:00
def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Support added for shifts and unpacking MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22 18:42:45 +00:00
def int_x86_mmx_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Support added for shifts and unpacking MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22 18:42:45 +00:00
def int_x86_mmx_psrl_d : GCCBuiltin<"__builtin_ia32_psrld">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Support added for shifts and unpacking MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22 18:42:45 +00:00
def int_x86_mmx_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Support added for shifts and unpacking MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22 18:42:45 +00:00
def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Support added for shifts and unpacking MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22 18:42:45 +00:00
def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
def int_x86_mmx_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrai_d : GCCBuiltin<"__builtin_ia32_psradi">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
llvm_i32_ty], [IntrNoMem]>;
PR1260: Add final support to get the QT example to compile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35290 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23 22:35:46 +00:00
}
// Pack ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_mmx_packsswb : GCCBuiltin<"__builtin_ia32_packsswb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
PR1260: Add final support to get the QT example to compile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35290 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23 22:35:46 +00:00
def int_x86_mmx_packssdw : GCCBuiltin<"__builtin_ia32_packssdw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
PR1260: Add final support to get the QT example to compile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35290 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23 22:35:46 +00:00
def int_x86_mmx_packuswb : GCCBuiltin<"__builtin_ia32_packuswb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Support added for shifts and unpacking MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22 18:42:45 +00:00
}
Add support for integer comparison builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 20:21:31 +00:00
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
// Unpacking ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_mmx_punpckhbw : GCCBuiltin<"__builtin_ia32_punpckhbw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_punpckhwd : GCCBuiltin<"__builtin_ia32_punpckhwd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_punpckhdq : GCCBuiltin<"__builtin_ia32_punpckhdq">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_punpcklbw : GCCBuiltin<"__builtin_ia32_punpcklbw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_punpcklwd : GCCBuiltin<"__builtin_ia32_punpcklwd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
def int_x86_mmx_punpckldq : GCCBuiltin<"__builtin_ia32_punpckldq">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
[IntrNoMem]>;
}
Add support for integer comparison builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 20:21:31 +00:00
// Integer comparison ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_mmx_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Mark X86 pcmpeq b/w/d intrinsics as being Commutative. pcmpeqq is already marked as Commutative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-30 18:33:35 +00:00
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Add support for integer comparison builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 20:21:31 +00:00
def int_x86_mmx_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Mark X86 pcmpeq b/w/d intrinsics as being Commutative. pcmpeqq is already marked as Commutative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-30 18:33:35 +00:00
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Add support for integer comparison builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 20:21:31 +00:00
def int_x86_mmx_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Mark X86 pcmpeq b/w/d intrinsics as being Commutative. pcmpeqq is already marked as Commutative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-30 18:33:35 +00:00
llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
Add support for integer comparison builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 20:21:31 +00:00
def int_x86_mmx_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Add support for integer comparison builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 20:21:31 +00:00
def int_x86_mmx_pcmpgt_w : GCCBuiltin<"__builtin_ia32_pcmpgtw">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Add support for integer comparison builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 20:21:31 +00:00
def int_x86_mmx_pcmpgt_d : GCCBuiltin<"__builtin_ia32_pcmpgtd">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
llvm_x86mmx_ty], [IntrNoMem]>;
Add support for integer comparison builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-27 20:21:31 +00:00
}
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
// Misc.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
add missing mmx intrinsic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37099 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 06:03:49 +00:00
def int_x86_mmx_maskmovq : GCCBuiltin<"__builtin_ia32_maskmovq">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[], [llvm_x86mmx_ty, llvm_x86mmx_ty, llvm_ptr_ty], []>;
add missing mmx intrinsic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37099 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 06:03:49 +00:00
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
def int_x86_mmx_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[llvm_i32_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
Add the final MMX instructions. Correct a few wrong patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36405 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-24 21:18:37 +00:00
def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
Intrinsic<[], [llvm_ptrx86mmx_ty, llvm_x86mmx_ty], []>;
Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 00:40:09 +00:00
Add patterns for MMX that use the new intrinsics. Enable palignr intrinsic. These may need adjustment for a new VT in due course. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 18:10:56 +00:00
def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
llvm_x86mmx_ty, llvm_i8_ty], [IntrNoMem]>;
Recommit with changes. Comment out palignr for the moment, as there's a testcase that uses it and expects it to be subject to optimizations; we won't be doing that. Some adjustments based on feedback from Bill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:43:48 +00:00
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
def int_x86_mmx_pextr_w : GCCBuiltin<"__builtin_ia32_vec_ext_v4hi">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_i32_ty], [llvm_x86mmx_ty, llvm_i32_ty],
Recommit with changes. Comment out palignr for the moment, as there's a testcase that uses it and expects it to be subject to optimizations; we won't be doing that. Some adjustments based on feedback from Bill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:43:48 +00:00
[IntrNoMem]>;
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 23:57:10 +00:00
def int_x86_mmx_pinsr_w : GCCBuiltin<"__builtin_ia32_vec_set_v4hi">,
Fix whitespace and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 14:33:36 +00:00
Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
Recommit with changes. Comment out palignr for the moment, as there's a testcase that uses it and expects it to be subject to optimizations; we won't be doing that. Some adjustments based on feedback from Bill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01 22:43:48 +00:00
llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
Adding more MMX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:48:32 +00:00
}
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
//===----------------------------------------------------------------------===//
// BMI
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_bmi_bextr_32 : GCCBuiltin<"__builtin_ia32_bextr_u32">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_x86_bmi_bextr_64 : GCCBuiltin<"__builtin_ia32_bextr_u64">,
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
def int_x86_bmi_bzhi_32 : GCCBuiltin<"__builtin_ia32_bzhi_si">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_x86_bmi_bzhi_64 : GCCBuiltin<"__builtin_ia32_bzhi_di">,
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 06:55:01 +00:00
def int_x86_bmi_pdep_32 : GCCBuiltin<"__builtin_ia32_pdep_si">,
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 06:55:01 +00:00
def int_x86_bmi_pdep_64 : GCCBuiltin<"__builtin_ia32_pdep_di">,
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 06:55:01 +00:00
def int_x86_bmi_pext_32 : GCCBuiltin<"__builtin_ia32_pext_si">,
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 06:55:01 +00:00
def int_x86_bmi_pext_64 : GCCBuiltin<"__builtin_ia32_pext_di">,
Rename PEXTR to PEXT. Add intrinsics for BMI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-19 07:48:35 +00:00
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
}
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-30 19:57:21 +00:00
//===----------------------------------------------------------------------===//
// FS/GS Base
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_rdfsbase_32 : GCCBuiltin<"__builtin_ia32_rdfsbase32">,
Intrinsic<[llvm_i32_ty], []>;
def int_x86_rdgsbase_32 : GCCBuiltin<"__builtin_ia32_rdgsbase32">,
Intrinsic<[llvm_i32_ty], []>;
def int_x86_rdfsbase_64 : GCCBuiltin<"__builtin_ia32_rdfsbase64">,
Intrinsic<[llvm_i64_ty], []>;
def int_x86_rdgsbase_64 : GCCBuiltin<"__builtin_ia32_rdgsbase64">,
Intrinsic<[llvm_i64_ty], []>;
def int_x86_wrfsbase_32 : GCCBuiltin<"__builtin_ia32_wrfsbase32">,
Intrinsic<[], [llvm_i32_ty]>;
def int_x86_wrgsbase_32 : GCCBuiltin<"__builtin_ia32_wrgsbase32">,
Intrinsic<[], [llvm_i32_ty]>;
def int_x86_wrfsbase_64 : GCCBuiltin<"__builtin_ia32_wrfsbase64">,
Intrinsic<[], [llvm_i64_ty]>;
def int_x86_wrgsbase_64 : GCCBuiltin<"__builtin_ia32_wrgsbase64">,
Intrinsic<[], [llvm_i64_ty]>;
}
Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-04 06:59:49 +00:00
//===----------------------------------------------------------------------===//
// Half float conversion
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_vcvtph2ps_128 : GCCBuiltin<"__builtin_ia32_vcvtph2ps">,
Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_vcvtph2ps_256 : GCCBuiltin<"__builtin_ia32_vcvtph2ps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_vcvtps2ph_128 : GCCBuiltin<"__builtin_ia32_vcvtps2ph">,
Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_x86_vcvtps2ph_256 : GCCBuiltin<"__builtin_ia32_vcvtps2ph256">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8f32_ty, llvm_i32_ty],
[IntrNoMem]>;
}
Add intrinsics for Ivy Bridge's rdrand instruction. The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12 09:31:43 +00:00
//===----------------------------------------------------------------------===//
Add support of RDSEED defined in AVX2 extension git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:41:26 +00:00
// RDRAND intrinsics - Return a random value and whether it is valid.
// RDSEED intrinsics - Return a NIST SP800-90B & C compliant random value and
// whether it is valid.
Add intrinsics for Ivy Bridge's rdrand instruction. The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12 09:31:43 +00:00
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// These are declared side-effecting so they don't get eliminated by CSE or
// LICM.
def int_x86_rdrand_16 : Intrinsic<[llvm_i16_ty, llvm_i32_ty], [], []>;
def int_x86_rdrand_32 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [], []>;
def int_x86_rdrand_64 : Intrinsic<[llvm_i64_ty, llvm_i32_ty], [], []>;
Add support of RDSEED defined in AVX2 extension git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:41:26 +00:00
def int_x86_rdseed_16 : Intrinsic<[llvm_i16_ty, llvm_i32_ty], [], []>;
def int_x86_rdseed_32 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [], []>;
def int_x86_rdseed_64 : Intrinsic<[llvm_i64_ty, llvm_i32_ty], [], []>;
Add intrinsics for Ivy Bridge's rdrand instruction. The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12 09:31:43 +00:00
}
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08 07:28:54 +00:00
//===----------------------------------------------------------------------===//
// RTM intrinsics. Transactional Memory support.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_xbegin : GCCBuiltin<"__builtin_ia32_xbegin">,
Intrinsic<[llvm_i32_ty], [], []>;
def int_x86_xend : GCCBuiltin<"__builtin_ia32_xend">,
Intrinsic<[], [], []>;
def int_x86_xabort : GCCBuiltin<"__builtin_ia32_xabort">,
Intrinsic<[], [llvm_i8_ty], [IntrNoReturn]>;
Add XTEST codegen support git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 22:47:01 +00:00
def int_x86_xtest : GCCBuiltin<"__builtin_ia32_xtest">,
Intrinsic<[llvm_i32_ty], [], []>;
Add support of RTM from TSX extension - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08 07:28:54 +00:00
}
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