2003-12-20 01:22:19 +00:00
|
|
|
//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
|
2005-04-21 23:38:14 +00:00
|
|
|
//
|
2003-10-21 15:17:13 +00:00
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2005-04-21 23:38:14 +00:00
|
|
|
//
|
2003-10-21 15:17:13 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2002-10-25 22:55:53 +00:00
|
|
|
//
|
2003-01-14 22:00:31 +00:00
|
|
|
// This file contains the X86 implementation of the TargetInstrInfo class.
|
2002-10-25 22:55:53 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef X86INSTRUCTIONINFO_H
|
|
|
|
#define X86INSTRUCTIONINFO_H
|
|
|
|
|
2003-01-14 22:00:31 +00:00
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
2008-04-16 20:10:13 +00:00
|
|
|
#include "X86.h"
|
2002-10-25 22:55:53 +00:00
|
|
|
#include "X86RegisterInfo.h"
|
2009-01-05 17:59:02 +00:00
|
|
|
#include "llvm/ADT/DenseMap.h"
|
2008-02-10 18:45:23 +00:00
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
2002-10-25 22:55:53 +00:00
|
|
|
|
2003-11-11 22:41:34 +00:00
|
|
|
namespace llvm {
|
2006-09-08 06:48:29 +00:00
|
|
|
class X86RegisterInfo;
|
2006-05-30 21:45:53 +00:00
|
|
|
class X86TargetMachine;
|
2003-11-11 22:41:34 +00:00
|
|
|
|
2006-10-20 17:42:20 +00:00
|
|
|
namespace X86 {
|
|
|
|
// X86 specific condition code. These correspond to X86_*_COND in
|
|
|
|
// X86InstrInfo.td. They must be kept in synch.
|
|
|
|
enum CondCode {
|
|
|
|
COND_A = 0,
|
|
|
|
COND_AE = 1,
|
|
|
|
COND_B = 2,
|
|
|
|
COND_BE = 3,
|
|
|
|
COND_E = 4,
|
|
|
|
COND_G = 5,
|
|
|
|
COND_GE = 6,
|
|
|
|
COND_L = 7,
|
|
|
|
COND_LE = 8,
|
|
|
|
COND_NE = 9,
|
|
|
|
COND_NO = 10,
|
|
|
|
COND_NP = 11,
|
|
|
|
COND_NS = 12,
|
2009-01-07 00:15:08 +00:00
|
|
|
COND_O = 13,
|
|
|
|
COND_P = 14,
|
|
|
|
COND_S = 15,
|
Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57873 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 03:29:32 +00:00
|
|
|
|
|
|
|
// Artificial condition codes. These are used by AnalyzeBranch
|
|
|
|
// to indicate a block terminated with two conditional branches to
|
|
|
|
// the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
|
|
|
|
// which can't be represented on x86 with a single condition. These
|
|
|
|
// are never used in MachineInstrs.
|
|
|
|
COND_NE_OR_P,
|
|
|
|
COND_NP_OR_E,
|
|
|
|
|
2006-10-20 17:42:20 +00:00
|
|
|
COND_INVALID
|
|
|
|
};
|
2008-03-13 05:47:01 +00:00
|
|
|
|
2006-10-20 17:42:20 +00:00
|
|
|
// Turn condition code into conditional branch opcode.
|
|
|
|
unsigned GetCondBranchFromCond(CondCode CC);
|
2006-10-21 05:52:40 +00:00
|
|
|
|
|
|
|
/// GetOppositeBranchCondition - Return the inverse of the specified cond,
|
|
|
|
/// e.g. turning COND_E to COND_NE.
|
|
|
|
CondCode GetOppositeBranchCondition(X86::CondCode CC);
|
|
|
|
|
2006-10-20 17:42:20 +00:00
|
|
|
}
|
|
|
|
|
2002-10-30 01:09:34 +00:00
|
|
|
/// X86II - This namespace holds all of the target specific flags that
|
|
|
|
/// instruction info tracks.
|
|
|
|
///
|
|
|
|
namespace X86II {
|
|
|
|
enum {
|
2002-11-18 05:37:11 +00:00
|
|
|
//===------------------------------------------------------------------===//
|
2009-06-25 17:38:33 +00:00
|
|
|
// X86 Specific MachineOperand flags.
|
|
|
|
|
|
|
|
MO_NO_FLAG = 0,
|
|
|
|
|
|
|
|
/// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
|
|
|
|
/// relocation of:
|
2009-06-26 00:43:52 +00:00
|
|
|
/// SYMBOL_LABEL + [. - PICBASELABEL]
|
2009-06-25 17:38:33 +00:00
|
|
|
MO_GOT_ABSOLUTE_ADDRESS = 1,
|
|
|
|
|
2009-06-26 00:43:52 +00:00
|
|
|
/// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
|
|
|
|
/// immediate should get the value of the symbol minus the PIC base label:
|
|
|
|
/// SYMBOL_LABEL - PICBASELABEL
|
|
|
|
MO_PIC_BASE_OFFSET = 2,
|
|
|
|
|
2009-06-26 21:20:29 +00:00
|
|
|
/// MO_GOT - On a symbol operand this indicates that the immediate is the
|
|
|
|
/// offset to the GOT entry for the symbol name from the base of the GOT.
|
|
|
|
///
|
|
|
|
/// See the X86-64 ELF ABI supplement for more details.
|
|
|
|
/// SYMBOL_LABEL @GOT
|
|
|
|
MO_GOT = 3,
|
|
|
|
|
|
|
|
/// MO_GOTOFF - On a symbol operand this indicates that the immediate is
|
|
|
|
/// the offset to the location of the symbol name from the base of the GOT.
|
|
|
|
///
|
|
|
|
/// See the X86-64 ELF ABI supplement for more details.
|
2009-06-26 00:43:52 +00:00
|
|
|
/// SYMBOL_LABEL @GOTOFF
|
2009-06-26 21:20:29 +00:00
|
|
|
MO_GOTOFF = 4,
|
|
|
|
|
|
|
|
/// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
|
|
|
|
/// offset to the GOT entry for the symbol name from the current code
|
|
|
|
/// location.
|
|
|
|
///
|
|
|
|
/// See the X86-64 ELF ABI supplement for more details.
|
|
|
|
/// SYMBOL_LABEL @GOTPCREL
|
|
|
|
MO_GOTPCREL = 5,
|
|
|
|
|
|
|
|
/// MO_PLT - On a symbol operand this indicates that the immediate is
|
|
|
|
/// offset to the PLT entry of symbol name from the current code location.
|
|
|
|
///
|
|
|
|
/// See the X86-64 ELF ABI supplement for more details.
|
|
|
|
/// SYMBOL_LABEL @PLT
|
|
|
|
MO_PLT = 6,
|
|
|
|
|
|
|
|
/// MO_TLSGD - On a symbol operand this indicates that the immediate is
|
|
|
|
/// some TLS offset.
|
|
|
|
///
|
|
|
|
/// See 'ELF Handling for Thread-Local Storage' for more details.
|
|
|
|
/// SYMBOL_LABEL @TLSGD
|
|
|
|
MO_TLSGD = 7,
|
|
|
|
|
|
|
|
/// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
|
|
|
|
/// some TLS offset.
|
|
|
|
///
|
|
|
|
/// See 'ELF Handling for Thread-Local Storage' for more details.
|
|
|
|
/// SYMBOL_LABEL @GOTTPOFF
|
|
|
|
MO_GOTTPOFF = 8,
|
|
|
|
|
|
|
|
/// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
|
|
|
|
/// some TLS offset.
|
|
|
|
///
|
|
|
|
/// See 'ELF Handling for Thread-Local Storage' for more details.
|
|
|
|
/// SYMBOL_LABEL @INDNTPOFF
|
|
|
|
MO_INDNTPOFF = 9,
|
|
|
|
|
|
|
|
/// MO_TPOFF - On a symbol operand this indicates that the immediate is
|
|
|
|
/// some TLS offset.
|
|
|
|
///
|
|
|
|
/// See 'ELF Handling for Thread-Local Storage' for more details.
|
|
|
|
/// SYMBOL_LABEL @TPOFF
|
|
|
|
MO_TPOFF = 10,
|
2009-06-26 00:43:52 +00:00
|
|
|
|
2009-06-26 21:20:29 +00:00
|
|
|
/// MO_NTPOFF - On a symbol operand this indicates that the immediate is
|
|
|
|
/// some TLS offset.
|
|
|
|
///
|
|
|
|
/// See 'ELF Handling for Thread-Local Storage' for more details.
|
|
|
|
/// SYMBOL_LABEL @NTPOFF
|
|
|
|
MO_NTPOFF = 11,
|
2009-06-25 17:38:33 +00:00
|
|
|
|
2009-07-09 00:58:53 +00:00
|
|
|
/// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
|
|
|
|
/// reference is actually to the "__imp_FOO" symbol. This is used for
|
|
|
|
/// dllimport linkage on windows.
|
|
|
|
MO_DLLIMPORT = 12,
|
|
|
|
|
2009-07-09 05:27:35 +00:00
|
|
|
/// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
|
|
|
|
/// reference is actually to the "FOO$stub" symbol. This is used for calls
|
|
|
|
/// and jumps to external functions on Tiger and before.
|
|
|
|
MO_DARWIN_STUB = 13,
|
|
|
|
|
2009-07-09 06:59:17 +00:00
|
|
|
/// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
|
|
|
|
/// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
|
|
|
|
/// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
|
|
|
|
MO_DARWIN_NONLAZY = 14,
|
|
|
|
|
|
|
|
/// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
|
|
|
|
/// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
|
|
|
|
/// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
|
|
|
|
MO_DARWIN_NONLAZY_PIC_BASE = 15,
|
|
|
|
|
|
|
|
/// MO_DARWIN_HIDDEN_NONLAZY - On a symbol operand "FOO", this indicates
|
|
|
|
/// that the reference is actually to the "FOO$non_lazy_ptr" symbol, which
|
|
|
|
/// is a non-PIC-base-relative reference to a hidden dyld lazy pointer stub.
|
|
|
|
MO_DARWIN_HIDDEN_NONLAZY = 16,
|
|
|
|
|
|
|
|
/// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
|
|
|
|
/// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
|
|
|
|
/// which is a PIC-base-relative reference to a hidden dyld lazy pointer
|
|
|
|
/// stub.
|
|
|
|
MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE = 17,
|
2009-07-09 00:58:53 +00:00
|
|
|
|
2009-06-25 17:38:33 +00:00
|
|
|
//===------------------------------------------------------------------===//
|
|
|
|
// Instruction encodings. These are the standard/most common forms for X86
|
2002-11-18 05:37:11 +00:00
|
|
|
// instructions.
|
|
|
|
//
|
|
|
|
|
2002-12-25 05:09:59 +00:00
|
|
|
// PseudoFrm - This represents an instruction that is a pseudo instruction
|
|
|
|
// or one that has not been implemented yet. It is illegal to code generate
|
|
|
|
// it, but tolerated for intermediate implementation stages.
|
|
|
|
Pseudo = 0,
|
|
|
|
|
2002-11-18 05:37:11 +00:00
|
|
|
/// Raw - This form is for instructions that don't have any operands, so
|
|
|
|
/// they are just a fixed opcode value, like 'leave'.
|
2002-12-25 05:09:59 +00:00
|
|
|
RawFrm = 1,
|
2005-04-21 23:38:14 +00:00
|
|
|
|
2002-11-18 05:37:11 +00:00
|
|
|
/// AddRegFrm - This form is used for instructions like 'push r32' that have
|
|
|
|
/// their one register operand added to their opcode.
|
2002-12-25 05:09:59 +00:00
|
|
|
AddRegFrm = 2,
|
2002-11-18 05:37:11 +00:00
|
|
|
|
|
|
|
/// MRMDestReg - This form is used for instructions that use the Mod/RM byte
|
|
|
|
/// to specify a destination, which in this case is a register.
|
|
|
|
///
|
2002-12-25 05:09:59 +00:00
|
|
|
MRMDestReg = 3,
|
2002-11-18 05:37:11 +00:00
|
|
|
|
|
|
|
/// MRMDestMem - This form is used for instructions that use the Mod/RM byte
|
|
|
|
/// to specify a destination, which in this case is memory.
|
|
|
|
///
|
2002-12-25 05:09:59 +00:00
|
|
|
MRMDestMem = 4,
|
2002-11-18 05:37:11 +00:00
|
|
|
|
|
|
|
/// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
|
|
|
|
/// to specify a source, which in this case is a register.
|
|
|
|
///
|
2002-12-25 05:09:59 +00:00
|
|
|
MRMSrcReg = 5,
|
2002-11-18 05:37:11 +00:00
|
|
|
|
|
|
|
/// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
|
|
|
|
/// to specify a source, which in this case is memory.
|
|
|
|
///
|
2002-12-25 05:09:59 +00:00
|
|
|
MRMSrcMem = 6,
|
2005-04-21 23:38:14 +00:00
|
|
|
|
2004-02-27 18:55:12 +00:00
|
|
|
/// MRM[0-7][rm] - These forms are used to represent instructions that use
|
2002-11-21 17:08:49 +00:00
|
|
|
/// a Mod/RM byte, and use the middle field to hold extended opcode
|
|
|
|
/// information. In the intel manual these are represented as /0, /1, ...
|
|
|
|
///
|
|
|
|
|
|
|
|
// First, instructions that operate on a register r/m operand...
|
2004-02-27 18:55:12 +00:00
|
|
|
MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
|
|
|
|
MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
|
2002-11-21 17:08:49 +00:00
|
|
|
|
|
|
|
// Next, instructions that operate on a memory r/m operand...
|
2004-02-27 18:55:12 +00:00
|
|
|
MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
|
|
|
|
MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
|
2002-11-18 05:37:11 +00:00
|
|
|
|
2006-02-01 06:13:50 +00:00
|
|
|
// MRMInitReg - This form is used for instructions whose source and
|
|
|
|
// destinations are the same register.
|
|
|
|
MRMInitReg = 32,
|
|
|
|
|
|
|
|
FormMask = 63,
|
2002-11-18 05:37:11 +00:00
|
|
|
|
|
|
|
//===------------------------------------------------------------------===//
|
|
|
|
// Actual flags...
|
|
|
|
|
2002-11-21 01:32:55 +00:00
|
|
|
// OpSize - Set if this instruction requires an operand size prefix (0x66),
|
|
|
|
// which most often indicates that the instruction operates on 16 bit data
|
|
|
|
// instead of 32 bit data.
|
2006-02-01 06:13:50 +00:00
|
|
|
OpSize = 1 << 6,
|
2002-12-25 05:09:59 +00:00
|
|
|
|
2006-09-08 06:48:29 +00:00
|
|
|
// AsSize - Set if this instruction requires an operand size prefix (0x67),
|
|
|
|
// which most often indicates that the instruction address 16 bit address
|
|
|
|
// instead of 32 bit address (or 32 bit address in 64 bit mode).
|
|
|
|
AdSize = 1 << 7,
|
|
|
|
|
|
|
|
//===------------------------------------------------------------------===//
|
2002-12-25 05:09:59 +00:00
|
|
|
// Op0Mask - There are several prefix bytes that are used to form two byte
|
2004-02-12 17:53:22 +00:00
|
|
|
// opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
|
|
|
|
// used to obtain the setting of this field. If no bits in this field is
|
|
|
|
// set, there is no prefix byte for obtaining a multibyte opcode.
|
2002-12-25 05:09:59 +00:00
|
|
|
//
|
2006-09-08 06:48:29 +00:00
|
|
|
Op0Shift = 8,
|
2003-08-06 15:32:20 +00:00
|
|
|
Op0Mask = 0xF << Op0Shift,
|
2002-12-25 05:09:59 +00:00
|
|
|
|
|
|
|
// TB - TwoByte - Set if this instruction has a two byte opcode, which
|
|
|
|
// starts with a 0x0F byte before the real opcode.
|
2003-08-06 15:32:20 +00:00
|
|
|
TB = 1 << Op0Shift,
|
2002-12-25 05:09:59 +00:00
|
|
|
|
2004-02-12 17:53:22 +00:00
|
|
|
// REP - The 0xF3 prefix byte indicating repetition of the following
|
|
|
|
// instruction.
|
|
|
|
REP = 2 << Op0Shift,
|
|
|
|
|
2002-12-25 05:09:59 +00:00
|
|
|
// D8-DF - These escape opcodes are used by the floating point unit. These
|
|
|
|
// values must remain sequential.
|
2004-02-12 17:53:22 +00:00
|
|
|
D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
|
|
|
|
DA = 5 << Op0Shift, DB = 6 << Op0Shift,
|
|
|
|
DC = 7 << Op0Shift, DD = 8 << Op0Shift,
|
|
|
|
DE = 9 << Op0Shift, DF = 10 << Op0Shift,
|
2005-07-27 05:53:44 +00:00
|
|
|
|
2005-07-06 18:59:04 +00:00
|
|
|
// XS, XD - These prefix codes are for single and double precision scalar
|
|
|
|
// floating point operations performed in the SSE registers.
|
2007-04-10 22:10:25 +00:00
|
|
|
XD = 11 << Op0Shift, XS = 12 << Op0Shift,
|
|
|
|
|
|
|
|
// T8, TA - Prefix after the 0x0F prefix.
|
|
|
|
T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
|
2002-12-25 05:09:59 +00:00
|
|
|
|
2004-02-28 22:02:05 +00:00
|
|
|
//===------------------------------------------------------------------===//
|
2006-09-08 06:48:29 +00:00
|
|
|
// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
|
|
|
|
// They are used to specify GPRs and SSE registers, 64-bit operand size,
|
|
|
|
// etc. We only cares about REX.W and REX.R bits and only the former is
|
|
|
|
// statically determined.
|
|
|
|
//
|
|
|
|
REXShift = 12,
|
|
|
|
REX_W = 1 << REXShift,
|
|
|
|
|
|
|
|
//===------------------------------------------------------------------===//
|
|
|
|
// This three-bit field describes the size of an immediate operand. Zero is
|
2004-02-28 22:02:05 +00:00
|
|
|
// unused so that we can tell if we forgot to set a value.
|
2006-09-08 06:48:29 +00:00
|
|
|
ImmShift = 13,
|
|
|
|
ImmMask = 7 << ImmShift,
|
2004-02-28 22:02:05 +00:00
|
|
|
Imm8 = 1 << ImmShift,
|
|
|
|
Imm16 = 2 << ImmShift,
|
|
|
|
Imm32 = 3 << ImmShift,
|
2006-09-08 06:48:29 +00:00
|
|
|
Imm64 = 4 << ImmShift,
|
2002-12-25 05:09:59 +00:00
|
|
|
|
2003-01-13 00:49:24 +00:00
|
|
|
//===------------------------------------------------------------------===//
|
|
|
|
// FP Instruction Classification... Zero is non-fp instruction.
|
|
|
|
|
2003-08-06 15:32:20 +00:00
|
|
|
// FPTypeMask - Mask for all of the FP types...
|
2006-09-08 06:48:29 +00:00
|
|
|
FPTypeShift = 16,
|
2003-08-06 15:32:20 +00:00
|
|
|
FPTypeMask = 7 << FPTypeShift,
|
|
|
|
|
2004-01-30 22:24:18 +00:00
|
|
|
// NotFP - The default, set for instructions that do not use FP registers.
|
|
|
|
NotFP = 0 << FPTypeShift,
|
|
|
|
|
2003-01-13 00:49:24 +00:00
|
|
|
// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
|
2003-08-06 15:32:20 +00:00
|
|
|
ZeroArgFP = 1 << FPTypeShift,
|
2003-01-13 00:49:24 +00:00
|
|
|
|
|
|
|
// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
|
2003-08-06 15:32:20 +00:00
|
|
|
OneArgFP = 2 << FPTypeShift,
|
2003-01-13 00:49:24 +00:00
|
|
|
|
|
|
|
// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
|
|
|
|
// result back to ST(0). For example, fcos, fsqrt, etc.
|
|
|
|
//
|
2003-08-06 15:32:20 +00:00
|
|
|
OneArgFPRW = 3 << FPTypeShift,
|
2003-01-13 00:49:24 +00:00
|
|
|
|
|
|
|
// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
|
|
|
|
// explicit argument, storing the result to either ST(0) or the implicit
|
|
|
|
// argument. For example: fadd, fsub, fmul, etc...
|
2003-08-06 15:32:20 +00:00
|
|
|
TwoArgFP = 4 << FPTypeShift,
|
2003-01-13 00:49:24 +00:00
|
|
|
|
2004-06-11 04:41:24 +00:00
|
|
|
// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
|
|
|
|
// explicit argument, but have no destination. Example: fucom, fucomi, ...
|
|
|
|
CompareFP = 5 << FPTypeShift,
|
|
|
|
|
2004-03-31 22:02:13 +00:00
|
|
|
// CondMovFP - "2 operand" floating point conditional move instructions.
|
2004-06-11 04:41:24 +00:00
|
|
|
CondMovFP = 6 << FPTypeShift,
|
2004-03-31 22:02:13 +00:00
|
|
|
|
2003-01-13 00:49:24 +00:00
|
|
|
// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
|
2004-06-11 04:41:24 +00:00
|
|
|
SpecialFP = 7 << FPTypeShift,
|
2004-03-31 22:02:13 +00:00
|
|
|
|
2008-03-01 13:37:02 +00:00
|
|
|
// Lock prefix
|
|
|
|
LOCKShift = 19,
|
|
|
|
LOCK = 1 << LOCKShift,
|
|
|
|
|
2008-10-11 19:09:15 +00:00
|
|
|
// Segment override prefixes. Currently we just need ability to address
|
|
|
|
// stuff in gs and fs segments.
|
|
|
|
SegOvrShift = 20,
|
|
|
|
SegOvrMask = 3 << SegOvrShift,
|
|
|
|
FS = 1 << SegOvrShift,
|
|
|
|
GS = 2 << SegOvrShift,
|
|
|
|
|
|
|
|
// Bits 22 -> 23 are unused
|
2006-09-08 06:48:29 +00:00
|
|
|
OpcodeShift = 24,
|
2006-05-24 17:04:05 +00:00
|
|
|
OpcodeMask = 0xFF << OpcodeShift
|
2002-10-30 01:09:34 +00:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
const int X86AddrNumOperands = 5;
|
2009-03-28 18:55:31 +00:00
|
|
|
|
2008-06-28 11:07:54 +00:00
|
|
|
inline static bool isScale(const MachineOperand &MO) {
|
2008-10-03 15:45:36 +00:00
|
|
|
return MO.isImm() &&
|
2008-06-28 11:07:54 +00:00
|
|
|
(MO.getImm() == 1 || MO.getImm() == 2 ||
|
|
|
|
MO.getImm() == 4 || MO.getImm() == 8);
|
|
|
|
}
|
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
|
2008-10-03 15:45:36 +00:00
|
|
|
if (MI->getOperand(Op).isFI()) return true;
|
2008-06-28 11:07:54 +00:00
|
|
|
return Op+4 <= MI->getNumOperands() &&
|
2008-10-03 15:45:36 +00:00
|
|
|
MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
|
|
|
|
MI->getOperand(Op+2).isReg() &&
|
|
|
|
(MI->getOperand(Op+3).isImm() ||
|
|
|
|
MI->getOperand(Op+3).isGlobal() ||
|
|
|
|
MI->getOperand(Op+3).isCPI() ||
|
|
|
|
MI->getOperand(Op+3).isJTI());
|
2008-06-28 11:07:54 +00:00
|
|
|
}
|
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
inline static bool isMem(const MachineInstr *MI, unsigned Op) {
|
|
|
|
if (MI->getOperand(Op).isFI()) return true;
|
|
|
|
return Op+5 <= MI->getNumOperands() &&
|
|
|
|
MI->getOperand(Op+4).isReg() &&
|
|
|
|
isLeaMem(MI, Op);
|
|
|
|
}
|
|
|
|
|
2008-01-01 01:03:04 +00:00
|
|
|
class X86InstrInfo : public TargetInstrInfoImpl {
|
2006-05-30 21:45:53 +00:00
|
|
|
X86TargetMachine &TM;
|
2002-10-25 22:55:53 +00:00
|
|
|
const X86RegisterInfo RI;
|
2008-01-07 01:35:02 +00:00
|
|
|
|
|
|
|
/// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
|
|
|
|
/// RegOp2MemOpTable2 - Load / store folding opcode maps.
|
|
|
|
///
|
|
|
|
DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
|
|
|
|
DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
|
|
|
|
DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
|
|
|
|
DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
|
|
|
|
|
|
|
|
/// MemOp2RegOpTable - Load / store unfolding opcode map.
|
|
|
|
///
|
|
|
|
DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
|
|
|
|
|
2002-10-25 22:55:53 +00:00
|
|
|
public:
|
2008-03-25 22:06:05 +00:00
|
|
|
explicit X86InstrInfo(X86TargetMachine &tm);
|
2002-10-25 22:55:53 +00:00
|
|
|
|
2003-01-14 22:00:31 +00:00
|
|
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
2002-10-25 22:55:53 +00:00
|
|
|
/// such, whenever a client has an instance of instruction info, it should
|
|
|
|
/// always be able to get register info as well (through this method).
|
|
|
|
///
|
2008-05-14 01:58:56 +00:00
|
|
|
virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
|
2002-10-25 22:55:53 +00:00
|
|
|
|
2009-01-20 19:12:24 +00:00
|
|
|
/// Return true if the instruction is a register to register move and return
|
|
|
|
/// the source and dest operands and their sub-register indices by reference.
|
|
|
|
virtual bool isMoveInstr(const MachineInstr &MI,
|
|
|
|
unsigned &SrcReg, unsigned &DstReg,
|
|
|
|
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
|
|
|
|
|
2008-11-18 19:49:32 +00:00
|
|
|
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
|
|
|
|
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
|
2008-03-31 20:40:39 +00:00
|
|
|
|
2008-05-12 20:54:26 +00:00
|
|
|
bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const;
|
2008-03-31 20:40:39 +00:00
|
|
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
|
|
unsigned DestReg, const MachineInstr *Orig) const;
|
|
|
|
|
2008-11-18 19:49:32 +00:00
|
|
|
bool isInvariantLoad(const MachineInstr *MI) const;
|
2007-12-17 23:07:56 +00:00
|
|
|
|
2005-01-02 02:37:07 +00:00
|
|
|
/// convertToThreeAddress - This method must be implemented by targets that
|
|
|
|
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
|
|
|
|
/// may be able to convert a two-address instruction into a true
|
|
|
|
/// three-address instruction on demand. This allows the X86 target (for
|
|
|
|
/// example) to convert ADD and SHL instructions into LEA instructions if they
|
|
|
|
/// would require register copies due to two-addressness.
|
|
|
|
///
|
|
|
|
/// This method returns a null pointer if the transformation cannot be
|
|
|
|
/// performed, otherwise it returns the new instruction.
|
|
|
|
///
|
2006-12-01 21:52:58 +00:00
|
|
|
virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
|
|
|
|
MachineBasicBlock::iterator &MBBI,
|
2008-07-02 23:41:07 +00:00
|
|
|
LiveVariables *LV) const;
|
2005-01-02 02:37:07 +00:00
|
|
|
|
Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-19 07:11:01 +00:00
|
|
|
/// commuteInstruction - We have a few instructions that must be hacked on to
|
|
|
|
/// commute them.
|
|
|
|
///
|
2008-06-16 07:33:11 +00:00
|
|
|
virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
|
Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-19 07:11:01 +00:00
|
|
|
|
2006-10-20 17:42:20 +00:00
|
|
|
// Branch analysis.
|
2007-06-14 22:03:45 +00:00
|
|
|
virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
|
2006-10-20 17:42:20 +00:00
|
|
|
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|
|
|
MachineBasicBlock *&FBB,
|
2009-02-09 07:14:22 +00:00
|
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
|
|
bool AllowModify) const;
|
2007-05-18 00:18:17 +00:00
|
|
|
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
|
|
|
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
|
|
MachineBasicBlock *FBB,
|
2008-08-14 22:49:33 +00:00
|
|
|
const SmallVectorImpl<MachineOperand> &Cond) const;
|
2008-08-26 18:03:31 +00:00
|
|
|
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
2007-12-31 06:32:00 +00:00
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
unsigned DestReg, unsigned SrcReg,
|
|
|
|
const TargetRegisterClass *DestRC,
|
|
|
|
const TargetRegisterClass *SrcRC) const;
|
2008-01-01 21:11:32 +00:00
|
|
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
|
|
|
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
|
|
|
|
|
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
unsigned DestReg, int FrameIndex,
|
|
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
|
|
|
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
2008-01-04 23:57:37 +00:00
|
|
|
|
|
|
|
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
|
|
|
|
|
|
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
|
|
|
2008-01-07 01:35:02 +00:00
|
|
|
/// foldMemoryOperand - If this target supports it, fold a load or store of
|
|
|
|
/// the specified stack slot into the specified machine instruction for the
|
|
|
|
/// specified operand(s). If this is possible, the target should perform the
|
|
|
|
/// folding and return true, otherwise it should return false. If it folds
|
|
|
|
/// the instruction, it is likely that the MachineInstruction the iterator
|
|
|
|
/// references has been changed.
|
2008-12-03 18:43:12 +00:00
|
|
|
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
|
|
MachineInstr* MI,
|
|
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
|
|
int FrameIndex) const;
|
2008-01-07 01:35:02 +00:00
|
|
|
|
|
|
|
/// foldMemoryOperand - Same as the previous version except it allows folding
|
|
|
|
/// of any load and store from / to any address, not just from a specific
|
|
|
|
/// stack slot.
|
2008-12-03 18:43:12 +00:00
|
|
|
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
|
|
MachineInstr* MI,
|
|
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
|
|
MachineInstr* LoadMI) const;
|
2008-01-07 01:35:02 +00:00
|
|
|
|
|
|
|
/// canFoldMemoryOperand - Returns true if the specified load / store is
|
|
|
|
/// folding is possible.
|
2008-10-16 01:49:15 +00:00
|
|
|
virtual bool canFoldMemoryOperand(const MachineInstr*,
|
|
|
|
const SmallVectorImpl<unsigned> &) const;
|
2008-01-07 01:35:02 +00:00
|
|
|
|
|
|
|
/// unfoldMemoryOperand - Separate a single instruction which folded a load or
|
|
|
|
/// a store or a load and a store into two or more instruction. If this is
|
|
|
|
/// possible, returns true as well as the new instructions by reference.
|
|
|
|
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
|
|
|
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
|
|
|
|
|
|
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
|
|
|
SmallVectorImpl<SDNode*> &NewNodes) const;
|
|
|
|
|
|
|
|
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
|
|
|
|
/// instruction after load / store are unfolded from an instruction of the
|
|
|
|
/// specified opcode. It returns zero if the specified unfolding is not
|
|
|
|
/// possible.
|
|
|
|
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
|
|
|
bool UnfoldLoad, bool UnfoldStore) const;
|
|
|
|
|
2008-10-16 01:49:15 +00:00
|
|
|
virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
|
2008-08-14 22:49:33 +00:00
|
|
|
virtual
|
|
|
|
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-19 07:11:01 +00:00
|
|
|
|
2009-02-06 17:17:30 +00:00
|
|
|
/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
|
|
|
|
/// instruction that defines the specified register class.
|
|
|
|
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
|
2008-10-27 07:14:50 +00:00
|
|
|
|
2002-11-18 06:56:24 +00:00
|
|
|
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
|
2007-08-29 19:01:20 +00:00
|
|
|
// specified machine instruction.
|
2002-11-18 06:56:24 +00:00
|
|
|
//
|
2008-01-07 07:27:27 +00:00
|
|
|
unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
|
2006-12-05 04:01:03 +00:00
|
|
|
return TID->TSFlags >> X86II::OpcodeShift;
|
2003-08-03 21:56:22 +00:00
|
|
|
}
|
2008-01-07 02:48:55 +00:00
|
|
|
unsigned char getBaseOpcodeFor(unsigned Opcode) const {
|
2007-08-29 19:01:20 +00:00
|
|
|
return getBaseOpcodeFor(&get(Opcode));
|
|
|
|
}
|
2008-04-16 20:10:13 +00:00
|
|
|
|
|
|
|
static bool isX86_64NonExtLowByteReg(unsigned reg) {
|
|
|
|
return (reg == X86::SPL || reg == X86::BPL ||
|
|
|
|
reg == X86::SIL || reg == X86::DIL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned sizeOfImm(const TargetInstrDesc *Desc);
|
|
|
|
static bool isX86_64ExtendedReg(const MachineOperand &MO);
|
|
|
|
static unsigned determineREX(const MachineInstr &MI);
|
|
|
|
|
|
|
|
/// GetInstSize - Returns the size of the specified MachineInstr.
|
|
|
|
///
|
|
|
|
virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
|
2008-01-07 01:35:02 +00:00
|
|
|
|
2008-09-30 00:58:23 +00:00
|
|
|
/// getGlobalBaseReg - Return a virtual register initialized with the
|
|
|
|
/// the global base register value. Output instructions required to
|
|
|
|
/// initialize the register in the function entry block, if necessary.
|
2008-09-23 18:22:58 +00:00
|
|
|
///
|
2008-09-30 00:58:23 +00:00
|
|
|
unsigned getGlobalBaseReg(MachineFunction *MF) const;
|
2008-09-23 18:22:58 +00:00
|
|
|
|
2008-01-07 01:35:02 +00:00
|
|
|
private:
|
2008-12-03 18:43:12 +00:00
|
|
|
MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
|
|
MachineInstr* MI,
|
|
|
|
unsigned OpNum,
|
2009-01-05 17:59:02 +00:00
|
|
|
const SmallVectorImpl<MachineOperand> &MOs) const;
|
2002-10-25 22:55:53 +00:00
|
|
|
};
|
|
|
|
|
2003-11-11 22:41:34 +00:00
|
|
|
} // End llvm namespace
|
|
|
|
|
2002-10-25 22:55:53 +00:00
|
|
|
#endif
|