2009-07-16 13:27:25 +00:00
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//==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the SystemZ target.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZISelLowering.h"
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#include "SystemZTargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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2009-07-16 14:36:52 +00:00
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#include "llvm/Support/raw_ostream.h"
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2009-07-16 13:27:25 +00:00
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using namespace llvm;
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2009-07-16 14:18:17 +00:00
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static const unsigned subreg_even32 = 1;
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static const unsigned subreg_odd32 = 2;
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static const unsigned subreg_even = 3;
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static const unsigned subreg_odd = 4;
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2009-07-16 14:14:33 +00:00
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2009-07-16 13:44:00 +00:00
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namespace {
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/// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
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/// instead of register numbers for the leaves of the matched tree.
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struct SystemZRRIAddressMode {
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enum {
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RegBase,
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FrameIndexBase
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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SDValue Reg;
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int FrameIndex;
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} Base;
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SDValue IndexReg;
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2009-07-16 13:48:23 +00:00
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int64_t Disp;
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2009-07-16 14:10:17 +00:00
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bool isRI;
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2009-07-16 13:44:00 +00:00
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2009-07-16 14:10:17 +00:00
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SystemZRRIAddressMode(bool RI = false)
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: BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
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2009-07-16 13:44:00 +00:00
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}
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void dump() {
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2009-08-23 07:05:07 +00:00
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errs() << "SystemZRRIAddressMode " << this << '\n';
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2009-07-16 13:44:00 +00:00
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if (BaseType == RegBase) {
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2009-08-23 07:05:07 +00:00
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errs() << "Base.Reg ";
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if (Base.Reg.getNode() != 0)
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Base.Reg.getNode()->dump();
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else
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errs() << "nul";
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errs() << '\n';
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2009-07-16 13:44:00 +00:00
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} else {
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2009-08-23 07:05:07 +00:00
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errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
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2009-07-16 13:44:00 +00:00
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}
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2009-07-16 14:10:17 +00:00
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if (!isRI) {
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2009-08-23 07:05:07 +00:00
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errs() << "IndexReg ";
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2009-07-16 14:10:17 +00:00
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if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
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2009-08-23 07:05:07 +00:00
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else errs() << "nul";
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2009-07-16 14:10:17 +00:00
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}
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2009-08-23 07:05:07 +00:00
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errs() << " Disp " << Disp << '\n';
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2009-07-16 13:44:00 +00:00
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}
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};
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}
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2009-07-16 13:27:25 +00:00
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/// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class SystemZDAGToDAGISel : public SelectionDAGISel {
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SystemZTargetLowering &Lowering;
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const SystemZSubtarget &Subtarget;
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2009-07-16 14:10:17 +00:00
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void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
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SDValue &Base, SDValue &Disp);
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2009-07-16 14:09:35 +00:00
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void getAddressOperands(const SystemZRRIAddressMode &AM,
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SDValue &Base, SDValue &Disp,
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SDValue &Index);
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2009-07-16 13:27:25 +00:00
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public:
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SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel),
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Lowering(*TM.getTargetLowering()),
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Subtarget(*TM.getSubtargetImpl()) { }
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virtual void InstructionSelect();
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virtual const char *getPassName() const {
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return "SystemZ DAG->DAG Pattern Instruction Selection";
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}
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2009-07-16 14:26:38 +00:00
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/// getI8Imm - Return a target constant with the specified value, of type
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/// i8.
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inline SDValue getI8Imm(uint64_t Imm) {
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2009-08-11 20:47:22 +00:00
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return CurDAG->getTargetConstant(Imm, MVT::i8);
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2009-07-16 14:26:38 +00:00
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}
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2009-07-16 13:33:57 +00:00
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/// getI16Imm - Return a target constant with the specified value, of type
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/// i16.
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inline SDValue getI16Imm(uint64_t Imm) {
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2009-08-11 20:47:22 +00:00
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return CurDAG->getTargetConstant(Imm, MVT::i16);
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2009-07-16 13:33:57 +00:00
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}
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2009-07-16 13:34:50 +00:00
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDValue getI32Imm(uint64_t Imm) {
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2009-08-11 20:47:22 +00:00
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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2009-07-16 13:34:50 +00:00
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}
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2009-07-16 13:27:25 +00:00
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// Include the pieces autogenerated from the target description.
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2009-07-16 13:33:57 +00:00
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#include "SystemZGenDAGISel.inc"
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2009-07-16 13:27:25 +00:00
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private:
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2009-07-16 14:13:24 +00:00
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bool SelectAddrRI12Only(SDValue Op, SDValue& Addr,
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SDValue &Base, SDValue &Disp);
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2009-07-16 14:10:17 +00:00
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bool SelectAddrRI12(SDValue Op, SDValue& Addr,
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2009-07-16 14:13:24 +00:00
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SDValue &Base, SDValue &Disp,
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bool is12BitOnly = false);
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2009-07-16 14:10:17 +00:00
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bool SelectAddrRI(SDValue Op, SDValue& Addr,
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2009-07-16 13:48:42 +00:00
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SDValue &Base, SDValue &Disp);
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2009-07-16 14:09:35 +00:00
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bool SelectAddrRRI12(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index);
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bool SelectAddrRRI20(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index);
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2009-07-16 13:47:59 +00:00
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bool SelectLAAddr(SDValue Op, SDValue Addr,
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2009-07-16 13:48:42 +00:00
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SDValue &Base, SDValue &Disp, SDValue &Index);
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2009-07-16 13:47:59 +00:00
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2009-07-16 13:27:25 +00:00
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SDNode *Select(SDValue Op);
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2009-07-16 14:14:33 +00:00
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bool TryFoldLoad(SDValue P, SDValue N,
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SDValue &Base, SDValue &Disp, SDValue &Index);
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2009-07-16 14:09:35 +00:00
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bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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bool is12Bit, unsigned Depth = 0);
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2009-07-16 13:44:00 +00:00
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bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
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2009-07-16 14:10:17 +00:00
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bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
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bool is12Bit);
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2009-07-16 13:27:25 +00:00
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#ifndef NDEBUG
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unsigned Indent;
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#endif
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};
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} // end anonymous namespace
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/// createSystemZISelDag - This pass converts a legalized DAG into a
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/// SystemZ-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new SystemZDAGToDAGISel(TM, OptLevel);
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}
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2009-07-16 13:43:18 +00:00
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/// isImmSExt20 - This method tests to see if the node is either a 32-bit
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/// or 64-bit immediate, and if the value can be accurately represented as a
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/// sign extension from a 20-bit value. If so, this returns true and the
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/// immediate.
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2009-07-16 13:48:23 +00:00
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static bool isImmSExt20(int64_t Val, int64_t &Imm) {
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2009-07-16 13:44:00 +00:00
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if (Val >= -524288 && Val <= 524287) {
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2009-07-16 13:48:23 +00:00
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Imm = Val;
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2009-07-16 13:44:00 +00:00
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return true;
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}
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return false;
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}
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2009-07-16 14:09:35 +00:00
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/// isImmZExt12 - This method tests to see if the node is either a 32-bit
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2009-07-16 14:03:41 +00:00
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/// or 64-bit immediate, and if the value can be accurately represented as a
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/// zero extension from a 12-bit value. If so, this returns true and the
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/// immediate.
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2009-07-16 14:09:35 +00:00
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static bool isImmZExt12(int64_t Val, int64_t &Imm) {
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if (Val >= 0 && Val <= 0xFFF) {
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2009-07-16 14:03:41 +00:00
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Imm = Val;
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return true;
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}
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return false;
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}
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2009-07-16 13:44:00 +00:00
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/// MatchAddress - Add the specified node to the specified addressing mode,
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/// returning true if it cannot be done. This just pattern matches for the
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/// addressing mode.
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bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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2009-07-16 14:09:35 +00:00
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bool is12Bit, unsigned Depth) {
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2009-07-16 13:44:00 +00:00
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DebugLoc dl = N.getDebugLoc();
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2009-08-23 06:49:22 +00:00
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DEBUG(errs() << "MatchAddress: "; AM.dump());
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2009-07-16 13:44:00 +00:00
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// Limit recursion.
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if (Depth > 5)
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return MatchAddressBase(N, AM);
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2009-07-16 13:44:30 +00:00
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// FIXME: We can perform better here. If we have something like
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// (shift (add A, imm), N), we can try to reassociate stuff and fold shift of
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// imm into addressing mode.
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2009-07-16 13:44:00 +00:00
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switch (N.getOpcode()) {
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default: break;
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case ISD::Constant: {
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2009-07-16 13:48:23 +00:00
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int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
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2009-07-17 02:19:26 +00:00
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int64_t Imm = 0;
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2009-07-16 14:09:35 +00:00
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bool Match = (is12Bit ?
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isImmZExt12(AM.Disp + Val, Imm) :
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isImmSExt20(AM.Disp + Val, Imm));
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if (Match) {
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2009-07-16 13:44:00 +00:00
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AM.Disp = Imm;
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return false;
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}
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break;
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}
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case ISD::FrameIndex:
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2009-07-16 14:09:35 +00:00
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if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
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AM.Base.Reg.getNode() == 0) {
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2009-07-16 13:44:00 +00:00
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AM.BaseType = SystemZRRIAddressMode::FrameIndexBase;
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AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
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return false;
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}
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break;
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case ISD::SUB: {
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// Given A-B, if A can be completely folded into the address and
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// the index field with the index field unused, use -B as the index.
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// This is a win if a has multiple parts that can be folded into
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// the address. Also, this saves a mov if the base register has
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// other uses, since it avoids a two-address sub instruction, however
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// it costs an additional mov if the index register has other uses.
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// Test if the LHS of the sub can be folded.
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SystemZRRIAddressMode Backup = AM;
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2009-07-16 14:09:35 +00:00
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if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) {
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2009-07-16 13:44:00 +00:00
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AM = Backup;
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break;
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}
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// Test if the index field is free for use.
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2009-07-16 14:31:14 +00:00
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if (AM.IndexReg.getNode() || AM.isRI) {
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2009-07-16 13:44:00 +00:00
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AM = Backup;
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break;
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}
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// If the base is a register with multiple uses, this transformation may
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// save a mov. Otherwise it's probably better not to do it.
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if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
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(!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) {
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AM = Backup;
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break;
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}
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// Ok, the transformation is legal and appears profitable. Go for it.
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SDValue RHS = N.getNode()->getOperand(1);
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SDValue Zero = CurDAG->getConstant(0, N.getValueType());
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SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
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AM.IndexReg = Neg;
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// Insert the new nodes into the topological ordering.
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if (Zero.getNode()->getNodeId() == -1 ||
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Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
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CurDAG->RepositionNode(N.getNode(), Zero.getNode());
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Zero.getNode()->setNodeId(N.getNode()->getNodeId());
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}
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if (Neg.getNode()->getNodeId() == -1 ||
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Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
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CurDAG->RepositionNode(N.getNode(), Neg.getNode());
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Neg.getNode()->setNodeId(N.getNode()->getNodeId());
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}
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return false;
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}
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case ISD::ADD: {
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SystemZRRIAddressMode Backup = AM;
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2009-07-16 14:09:35 +00:00
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if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) &&
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!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1))
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2009-07-16 13:44:00 +00:00
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return false;
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AM = Backup;
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2009-07-16 14:09:35 +00:00
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if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) &&
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!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1))
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2009-07-16 13:44:00 +00:00
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return false;
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AM = Backup;
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// If we couldn't fold both operands into the address at the same time,
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// see if we can just put each operand into a register and fold at least
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// the add.
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2009-07-16 14:10:17 +00:00
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if (!AM.isRI &&
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AM.BaseType == SystemZRRIAddressMode::RegBase &&
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2009-07-16 13:44:00 +00:00
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|
!AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
|
|
|
|
AM.Base.Reg = N.getNode()->getOperand(0);
|
|
|
|
AM.IndexReg = N.getNode()->getOperand(1);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case ISD::OR:
|
|
|
|
// Handle "X | C" as "X + C" iff X is known to have C bits clear.
|
|
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
|
|
|
|
SystemZRRIAddressMode Backup = AM;
|
2009-07-16 13:48:23 +00:00
|
|
|
int64_t Offset = CN->getSExtValue();
|
2009-07-17 02:19:26 +00:00
|
|
|
int64_t Imm = 0;
|
2009-07-16 14:09:35 +00:00
|
|
|
bool MatchOffset = (is12Bit ?
|
|
|
|
isImmZExt12(AM.Disp + Offset, Imm) :
|
|
|
|
isImmSExt20(AM.Disp + Offset, Imm));
|
|
|
|
// The resultant disp must fit in 12 or 20-bits.
|
|
|
|
if (MatchOffset &&
|
|
|
|
// LHS should be an addr mode.
|
|
|
|
!MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) &&
|
2009-07-16 13:44:00 +00:00
|
|
|
// Check to see if the LHS & C is zero.
|
|
|
|
CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
|
|
|
|
AM.Disp = Imm;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
AM = Backup;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return MatchAddressBase(N, AM);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
|
|
|
|
/// specified addressing mode without any further recursion.
|
|
|
|
bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
|
|
|
|
SystemZRRIAddressMode &AM) {
|
|
|
|
// Is the base register already occupied?
|
|
|
|
if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
|
2009-07-16 14:10:35 +00:00
|
|
|
// If so, check to see if the index register is set.
|
2009-07-16 14:10:17 +00:00
|
|
|
if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
|
2009-07-16 13:44:00 +00:00
|
|
|
AM.IndexReg = N;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we cannot select it.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Default, generate it as a register.
|
|
|
|
AM.BaseType = SystemZRRIAddressMode::RegBase;
|
|
|
|
AM.Base.Reg = N;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-07-16 14:10:17 +00:00
|
|
|
void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
|
|
|
|
SDValue &Base, SDValue &Disp) {
|
2009-07-16 14:09:35 +00:00
|
|
|
if (AM.BaseType == SystemZRRIAddressMode::RegBase)
|
|
|
|
Base = AM.Base.Reg;
|
|
|
|
else
|
|
|
|
Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
|
2009-07-16 14:09:35 +00:00
|
|
|
}
|
|
|
|
|
2009-07-16 14:10:17 +00:00
|
|
|
void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
|
|
|
|
SDValue &Base, SDValue &Disp,
|
|
|
|
SDValue &Index) {
|
|
|
|
getAddressOperandsRI(AM, Base, Disp);
|
|
|
|
Index = AM.IndexReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns true if the address can be represented by a base register plus
|
|
|
|
/// an unsigned 12-bit displacement [r+imm].
|
2009-07-16 14:13:24 +00:00
|
|
|
bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue Op, SDValue& Addr,
|
|
|
|
SDValue &Base, SDValue &Disp) {
|
|
|
|
return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
|
|
|
|
}
|
|
|
|
|
2009-07-16 14:10:17 +00:00
|
|
|
bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
|
2009-07-16 14:13:24 +00:00
|
|
|
SDValue &Base, SDValue &Disp,
|
|
|
|
bool is12BitOnly) {
|
2009-07-16 14:10:17 +00:00
|
|
|
SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
|
|
|
|
bool Done = false;
|
|
|
|
|
|
|
|
if (!Addr.hasOneUse()) {
|
|
|
|
unsigned Opcode = Addr.getOpcode();
|
|
|
|
if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
|
|
|
|
// If we are able to fold N into addressing mode, then we'll allow it even
|
|
|
|
// if N has multiple uses. In general, addressing computation is used as
|
|
|
|
// addresses by all of its uses. But watch out for CopyToReg uses, that
|
|
|
|
// means the address computation is liveout. It will be computed by a LA
|
|
|
|
// so we want to avoid computing the address twice.
|
|
|
|
for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
|
|
|
|
UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
|
|
|
|
if (UI->getOpcode() == ISD::CopyToReg) {
|
|
|
|
MatchAddressBase(Addr, AM12);
|
|
|
|
Done = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Check, whether we can match stuff using 20-bit displacements
|
2009-07-16 14:13:24 +00:00
|
|
|
if (!Done && !is12BitOnly &&
|
|
|
|
!MatchAddress(Addr, AM20, /* is12Bit */ false))
|
2009-07-16 14:10:17 +00:00
|
|
|
if (AM12.Disp == 0 && AM20.Disp != 0)
|
|
|
|
return false;
|
|
|
|
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
|
2009-07-16 14:10:17 +00:00
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT VT = Addr.getValueType();
|
2009-07-16 14:10:17 +00:00
|
|
|
if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
|
|
|
|
if (!AM12.Base.Reg.getNode())
|
|
|
|
AM12.Base.Reg = CurDAG->getRegister(0, VT);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
|
|
|
|
|
|
|
|
getAddressOperandsRI(AM12, Base, Disp);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns true if the address can be represented by a base register plus
|
|
|
|
/// a signed 20-bit displacement [r+imm].
|
|
|
|
bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
|
|
|
|
SDValue &Base, SDValue &Disp) {
|
|
|
|
SystemZRRIAddressMode AM(/*isRI*/true);
|
|
|
|
bool Done = false;
|
|
|
|
|
|
|
|
if (!Addr.hasOneUse()) {
|
|
|
|
unsigned Opcode = Addr.getOpcode();
|
|
|
|
if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
|
|
|
|
// If we are able to fold N into addressing mode, then we'll allow it even
|
|
|
|
// if N has multiple uses. In general, addressing computation is used as
|
|
|
|
// addresses by all of its uses. But watch out for CopyToReg uses, that
|
|
|
|
// means the address computation is liveout. It will be computed by a LA
|
|
|
|
// so we want to avoid computing the address twice.
|
|
|
|
for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
|
|
|
|
UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
|
|
|
|
if (UI->getOpcode() == ISD::CopyToReg) {
|
|
|
|
MatchAddressBase(Addr, AM);
|
|
|
|
Done = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
|
|
|
|
return false;
|
|
|
|
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs() << "MatchAddress (final): "; AM.dump());
|
2009-07-16 14:10:17 +00:00
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT VT = Addr.getValueType();
|
2009-07-16 14:10:17 +00:00
|
|
|
if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
|
|
|
|
if (!AM.Base.Reg.getNode())
|
|
|
|
AM.Base.Reg = CurDAG->getRegister(0, VT);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
|
|
|
|
|
|
|
|
getAddressOperandsRI(AM, Base, Disp);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-07-16 14:09:35 +00:00
|
|
|
/// Returns true if the address can be represented by a base register plus
|
|
|
|
/// index register plus an unsigned 12-bit displacement [base + idx + imm].
|
|
|
|
bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
|
|
|
|
SDValue &Base, SDValue &Disp, SDValue &Index) {
|
2009-07-16 14:10:35 +00:00
|
|
|
SystemZRRIAddressMode AM20, AM12;
|
2009-07-16 14:09:35 +00:00
|
|
|
bool Done = false;
|
|
|
|
|
|
|
|
if (!Addr.hasOneUse()) {
|
|
|
|
unsigned Opcode = Addr.getOpcode();
|
|
|
|
if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
|
|
|
|
// If we are able to fold N into addressing mode, then we'll allow it even
|
|
|
|
// if N has multiple uses. In general, addressing computation is used as
|
|
|
|
// addresses by all of its uses. But watch out for CopyToReg uses, that
|
|
|
|
// means the address computation is liveout. It will be computed by a LA
|
|
|
|
// so we want to avoid computing the address twice.
|
|
|
|
for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
|
|
|
|
UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
|
|
|
|
if (UI->getOpcode() == ISD::CopyToReg) {
|
|
|
|
MatchAddressBase(Addr, AM12);
|
|
|
|
Done = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Check, whether we can match stuff using 20-bit displacements
|
|
|
|
if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
|
|
|
|
if (AM12.Disp == 0 && AM20.Disp != 0)
|
|
|
|
return false;
|
|
|
|
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
|
2009-07-16 14:09:35 +00:00
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT VT = Addr.getValueType();
|
2009-07-16 14:09:35 +00:00
|
|
|
if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
|
|
|
|
if (!AM12.Base.Reg.getNode())
|
|
|
|
AM12.Base.Reg = CurDAG->getRegister(0, VT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!AM12.IndexReg.getNode())
|
|
|
|
AM12.IndexReg = CurDAG->getRegister(0, VT);
|
|
|
|
|
|
|
|
getAddressOperands(AM12, Base, Disp, Index);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-07-16 13:44:00 +00:00
|
|
|
/// Returns true if the address can be represented by a base register plus
|
|
|
|
/// index register plus a signed 20-bit displacement [base + idx + imm].
|
2009-07-16 14:09:35 +00:00
|
|
|
bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr,
|
2009-07-16 13:48:42 +00:00
|
|
|
SDValue &Base, SDValue &Disp, SDValue &Index) {
|
2009-07-16 13:44:00 +00:00
|
|
|
SystemZRRIAddressMode AM;
|
|
|
|
bool Done = false;
|
|
|
|
|
2009-07-16 13:47:59 +00:00
|
|
|
if (!Addr.hasOneUse()) {
|
|
|
|
unsigned Opcode = Addr.getOpcode();
|
|
|
|
if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
|
|
|
|
// If we are able to fold N into addressing mode, then we'll allow it even
|
|
|
|
// if N has multiple uses. In general, addressing computation is used as
|
|
|
|
// addresses by all of its uses. But watch out for CopyToReg uses, that
|
|
|
|
// means the address computation is liveout. It will be computed by a LA
|
|
|
|
// so we want to avoid computing the address twice.
|
|
|
|
for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
|
|
|
|
UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
|
|
|
|
if (UI->getOpcode() == ISD::CopyToReg) {
|
|
|
|
MatchAddressBase(Addr, AM);
|
|
|
|
Done = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2009-07-16 14:09:35 +00:00
|
|
|
if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
|
2009-07-16 13:44:00 +00:00
|
|
|
return false;
|
|
|
|
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs() << "MatchAddress (final): "; AM.dump());
|
2009-07-16 13:48:23 +00:00
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT VT = Addr.getValueType();
|
2009-07-16 13:44:00 +00:00
|
|
|
if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
|
|
|
|
if (!AM.Base.Reg.getNode())
|
|
|
|
AM.Base.Reg = CurDAG->getRegister(0, VT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!AM.IndexReg.getNode())
|
|
|
|
AM.IndexReg = CurDAG->getRegister(0, VT);
|
|
|
|
|
2009-07-16 14:09:35 +00:00
|
|
|
getAddressOperands(AM, Base, Disp, Index);
|
2009-07-16 13:44:00 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2009-07-16 13:27:25 +00:00
|
|
|
|
2009-07-16 13:47:59 +00:00
|
|
|
/// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
|
|
|
|
/// mode it matches can be cost effectively emitted as an LA/LAY instruction.
|
|
|
|
bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
|
2009-07-16 13:48:42 +00:00
|
|
|
SDValue &Base, SDValue &Disp, SDValue &Index) {
|
2009-07-16 13:47:59 +00:00
|
|
|
SystemZRRIAddressMode AM;
|
|
|
|
|
2009-07-16 14:09:35 +00:00
|
|
|
if (MatchAddress(Addr, AM, false))
|
2009-07-16 13:47:59 +00:00
|
|
|
return false;
|
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT VT = Addr.getValueType();
|
2009-07-16 13:47:59 +00:00
|
|
|
unsigned Complexity = 0;
|
|
|
|
if (AM.BaseType == SystemZRRIAddressMode::RegBase)
|
|
|
|
if (AM.Base.Reg.getNode())
|
|
|
|
Complexity = 1;
|
|
|
|
else
|
|
|
|
AM.Base.Reg = CurDAG->getRegister(0, VT);
|
|
|
|
else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase)
|
|
|
|
Complexity = 4;
|
|
|
|
|
|
|
|
if (AM.IndexReg.getNode())
|
|
|
|
Complexity += 1;
|
|
|
|
else
|
|
|
|
AM.IndexReg = CurDAG->getRegister(0, VT);
|
|
|
|
|
|
|
|
if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
|
|
|
|
Complexity += 1;
|
|
|
|
|
|
|
|
if (Complexity > 2) {
|
2009-07-16 14:09:35 +00:00
|
|
|
getAddressOperands(AM, Base, Disp, Index);
|
2009-07-16 13:47:59 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-07-16 14:14:33 +00:00
|
|
|
bool SystemZDAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
|
|
|
|
SDValue &Base, SDValue &Disp, SDValue &Index) {
|
|
|
|
if (ISD::isNON_EXTLoad(N.getNode()) &&
|
|
|
|
N.hasOneUse() &&
|
|
|
|
IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
|
|
|
|
return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-07-16 13:27:25 +00:00
|
|
|
/// InstructionSelect - This callback is invoked by
|
|
|
|
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
|
|
|
|
void SystemZDAGToDAGISel::InstructionSelect() {
|
|
|
|
// Codegen the basic block.
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs() << "===== Instruction selection begins:\n");
|
2009-08-23 08:50:52 +00:00
|
|
|
DEBUG(Indent = 0);
|
2009-07-16 13:27:25 +00:00
|
|
|
SelectRoot(*CurDAG);
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs() << "===== Instruction selection ends:\n");
|
2009-07-16 13:27:25 +00:00
|
|
|
|
|
|
|
CurDAG->RemoveDeadNodes();
|
|
|
|
}
|
|
|
|
|
|
|
|
SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
|
|
|
|
SDNode *Node = Op.getNode();
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT NVT = Node->getValueType(0);
|
2009-07-16 13:27:25 +00:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2009-07-16 14:14:33 +00:00
|
|
|
unsigned Opcode = Node->getOpcode();
|
2009-07-16 13:27:25 +00:00
|
|
|
|
|
|
|
// Dump information about the Node being selected
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs().indent(Indent) << "Selecting: ";
|
|
|
|
Node->dump(CurDAG);
|
|
|
|
errs() << "\n");
|
2009-08-23 08:50:52 +00:00
|
|
|
DEBUG(Indent += 2);
|
2009-07-16 13:27:25 +00:00
|
|
|
|
|
|
|
// If we have a custom node, we already have selected!
|
|
|
|
if (Node->isMachineOpcode()) {
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs().indent(Indent-2) << "== ";
|
|
|
|
Node->dump(CurDAG);
|
|
|
|
errs() << "\n");
|
2009-08-23 08:50:52 +00:00
|
|
|
DEBUG(Indent -= 2);
|
2009-07-16 14:14:33 +00:00
|
|
|
return NULL; // Already selected.
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (Opcode) {
|
|
|
|
default: break;
|
|
|
|
case ISD::SDIVREM: {
|
2009-07-16 14:17:52 +00:00
|
|
|
unsigned Opc, MOpc;
|
2009-07-16 14:14:33 +00:00
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT ResVT;
|
2009-07-16 14:17:52 +00:00
|
|
|
bool is32Bit = false;
|
2009-08-11 20:47:22 +00:00
|
|
|
switch (NVT.getSimpleVT().SimpleTy) {
|
2009-07-16 14:14:33 +00:00
|
|
|
default: assert(0 && "Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i32:
|
2009-07-16 14:14:33 +00:00
|
|
|
Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
|
2009-08-11 20:47:22 +00:00
|
|
|
ResVT = MVT::v2i64;
|
2009-07-16 14:17:52 +00:00
|
|
|
is32Bit = true;
|
2009-07-16 14:14:33 +00:00
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i64:
|
2009-07-16 14:14:33 +00:00
|
|
|
Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
|
2009-08-11 20:47:22 +00:00
|
|
|
ResVT = MVT::v2i64;
|
2009-07-16 14:14:33 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue Tmp0, Tmp1, Tmp2;
|
|
|
|
bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
|
|
|
|
|
|
|
|
// Prepare the dividend
|
2009-07-16 14:17:52 +00:00
|
|
|
SDNode *Dividend;
|
|
|
|
if (is32Bit)
|
2009-09-25 18:54:59 +00:00
|
|
|
Dividend = CurDAG->getMachineNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
|
2009-07-16 14:17:52 +00:00
|
|
|
else
|
|
|
|
Dividend = N0.getNode();
|
2009-07-16 14:14:33 +00:00
|
|
|
|
|
|
|
// Insert prepared dividend into suitable 'subreg'
|
2009-09-25 18:54:59 +00:00
|
|
|
SDNode *Tmp = CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
|
|
|
|
dl, ResVT);
|
2009-07-16 14:14:33 +00:00
|
|
|
Dividend =
|
2009-09-25 18:54:59 +00:00
|
|
|
CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
|
|
|
|
SDValue(Tmp, 0), SDValue(Dividend, 0),
|
|
|
|
CurDAG->getTargetConstant(subreg_odd, MVT::i32));
|
2009-07-16 14:14:33 +00:00
|
|
|
|
|
|
|
SDNode *Result;
|
|
|
|
SDValue DivVal = SDValue(Dividend, 0);
|
|
|
|
if (foldedLoad) {
|
|
|
|
SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
|
2009-09-25 18:54:59 +00:00
|
|
|
Result = CurDAG->getMachineNode(MOpc, dl, ResVT,
|
|
|
|
Ops, array_lengthof(Ops));
|
2009-07-16 14:14:33 +00:00
|
|
|
// Update the chain.
|
|
|
|
ReplaceUses(N1.getValue(1), SDValue(Result, 0));
|
|
|
|
} else {
|
2009-09-25 18:54:59 +00:00
|
|
|
Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
|
2009-07-16 14:14:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Copy the division (odd subreg) result, if it is needed.
|
|
|
|
if (!Op.getValue(0).use_empty()) {
|
2009-07-16 14:18:17 +00:00
|
|
|
unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
|
2009-09-25 18:54:59 +00:00
|
|
|
SDNode *Div = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
|
|
|
|
dl, NVT,
|
|
|
|
SDValue(Result, 0),
|
|
|
|
CurDAG->getTargetConstant(SubRegIdx,
|
|
|
|
MVT::i32));
|
2009-07-16 14:18:17 +00:00
|
|
|
|
2009-07-16 14:14:33 +00:00
|
|
|
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs().indent(Indent-2) << "=> ";
|
|
|
|
Result->dump(CurDAG);
|
|
|
|
errs() << "\n");
|
2009-07-16 14:14:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Copy the remainder (even subreg) result, if it is needed.
|
|
|
|
if (!Op.getValue(1).use_empty()) {
|
2009-07-16 14:18:17 +00:00
|
|
|
unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
|
2009-09-25 18:54:59 +00:00
|
|
|
SDNode *Rem = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
|
|
|
|
dl, NVT,
|
|
|
|
SDValue(Result, 0),
|
|
|
|
CurDAG->getTargetConstant(SubRegIdx,
|
|
|
|
MVT::i32));
|
2009-07-16 14:17:52 +00:00
|
|
|
|
2009-07-16 14:14:33 +00:00
|
|
|
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs().indent(Indent-2) << "=> ";
|
|
|
|
Result->dump(CurDAG);
|
|
|
|
errs() << "\n");
|
2009-07-16 14:14:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
Indent -= 2;
|
|
|
|
#endif
|
|
|
|
|
2009-07-16 13:27:25 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
2009-07-16 14:14:33 +00:00
|
|
|
case ISD::UDIVREM: {
|
|
|
|
unsigned Opc, MOpc, ClrOpc;
|
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT ResVT;
|
2009-07-16 14:14:33 +00:00
|
|
|
|
2009-07-16 14:18:17 +00:00
|
|
|
bool is32Bit = false;
|
2009-08-11 20:47:22 +00:00
|
|
|
switch (NVT.getSimpleVT().SimpleTy) {
|
2009-07-16 14:14:33 +00:00
|
|
|
default: assert(0 && "Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i32:
|
2009-07-16 14:14:33 +00:00
|
|
|
Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
|
2009-07-16 14:14:54 +00:00
|
|
|
ClrOpc = SystemZ::MOV64Pr0_even;
|
2009-08-11 20:47:22 +00:00
|
|
|
ResVT = MVT::v2i32;
|
2009-07-16 14:18:17 +00:00
|
|
|
is32Bit = true;
|
2009-07-16 14:14:33 +00:00
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i64:
|
2009-07-16 14:14:33 +00:00
|
|
|
Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
|
2009-07-16 14:14:54 +00:00
|
|
|
ClrOpc = SystemZ::MOV128r0_even;
|
2009-08-11 20:47:22 +00:00
|
|
|
ResVT = MVT::v2i64;
|
2009-07-16 14:14:33 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue Tmp0, Tmp1, Tmp2;
|
|
|
|
bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
|
|
|
|
|
|
|
|
// Prepare the dividend
|
|
|
|
SDNode *Dividend = N0.getNode();
|
|
|
|
|
|
|
|
// Insert prepared dividend into suitable 'subreg'
|
2009-09-25 18:54:59 +00:00
|
|
|
SDNode *Tmp = CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
|
|
|
|
dl, ResVT);
|
2009-07-16 14:18:17 +00:00
|
|
|
{
|
|
|
|
unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
|
|
|
|
Dividend =
|
2009-09-25 18:54:59 +00:00
|
|
|
CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
|
|
|
|
SDValue(Tmp, 0), SDValue(Dividend, 0),
|
|
|
|
CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
|
2009-07-16 14:18:17 +00:00
|
|
|
}
|
2009-07-16 14:14:33 +00:00
|
|
|
|
2009-07-16 14:14:54 +00:00
|
|
|
// Zero out even subreg
|
2009-09-25 18:54:59 +00:00
|
|
|
Dividend = CurDAG->getMachineNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
|
2009-07-16 14:14:33 +00:00
|
|
|
|
|
|
|
SDValue DivVal = SDValue(Dividend, 0);
|
|
|
|
SDNode *Result;
|
|
|
|
if (foldedLoad) {
|
|
|
|
SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
|
2009-09-25 18:54:59 +00:00
|
|
|
Result = CurDAG->getMachineNode(MOpc, dl,ResVT,
|
|
|
|
Ops, array_lengthof(Ops));
|
2009-07-16 14:14:33 +00:00
|
|
|
// Update the chain.
|
|
|
|
ReplaceUses(N1.getValue(1), SDValue(Result, 0));
|
|
|
|
} else {
|
2009-09-25 18:54:59 +00:00
|
|
|
Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1);
|
2009-07-16 14:14:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Copy the division (odd subreg) result, if it is needed.
|
|
|
|
if (!Op.getValue(0).use_empty()) {
|
2009-07-16 14:18:17 +00:00
|
|
|
unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
|
2009-09-25 18:54:59 +00:00
|
|
|
SDNode *Div = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
|
|
|
|
dl, NVT,
|
|
|
|
SDValue(Result, 0),
|
|
|
|
CurDAG->getTargetConstant(SubRegIdx,
|
|
|
|
MVT::i32));
|
2009-07-16 14:14:33 +00:00
|
|
|
ReplaceUses(Op.getValue(0), SDValue(Div, 0));
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs().indent(Indent-2) << "=> ";
|
|
|
|
Result->dump(CurDAG);
|
|
|
|
errs() << "\n");
|
2009-07-16 14:14:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Copy the remainder (even subreg) result, if it is needed.
|
|
|
|
if (!Op.getValue(1).use_empty()) {
|
2009-07-16 14:18:17 +00:00
|
|
|
unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
|
2009-09-25 18:54:59 +00:00
|
|
|
SDNode *Rem = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
|
|
|
|
dl, NVT,
|
|
|
|
SDValue(Result, 0),
|
|
|
|
CurDAG->getTargetConstant(SubRegIdx,
|
|
|
|
MVT::i32));
|
2009-07-16 14:14:33 +00:00
|
|
|
ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs().indent(Indent-2) << "=> ";
|
|
|
|
Result->dump(CurDAG);
|
|
|
|
errs() << "\n");
|
2009-07-16 14:14:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
Indent -= 2;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
}
|
2009-07-16 13:27:25 +00:00
|
|
|
|
|
|
|
// Select the default instruction
|
|
|
|
SDNode *ResNode = SelectCode(Op);
|
|
|
|
|
2009-08-23 06:49:22 +00:00
|
|
|
DEBUG(errs().indent(Indent-2) << "=> ";
|
|
|
|
if (ResNode == NULL || ResNode == Op.getNode())
|
|
|
|
Op.getNode()->dump(CurDAG);
|
|
|
|
else
|
|
|
|
ResNode->dump(CurDAG);
|
|
|
|
errs() << "\n";
|
|
|
|
);
|
2009-08-23 08:50:52 +00:00
|
|
|
DEBUG(Indent -= 2);
|
2009-07-16 13:27:25 +00:00
|
|
|
|
|
|
|
return ResNode;
|
|
|
|
}
|