U test/Makefile
U Makefile.rules
--- Merging r127240 into '.':
U utils/llvm-lit/Makefile
--- Merging r127726 into '.':
U lib/Support/raw_ostream.cpp
--- Merging r127730 into '.':
U test/CodeGen/X86/dyn-stackalloc.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128259 91177308-0d34-0410-b5e6-96231b3b80d8
U test/CodeGen/X86/byval2.ll
U test/CodeGen/X86/byval4.ll
U test/CodeGen/X86/byval.ll
U test/CodeGen/X86/byval3.ll
U test/CodeGen/X86/byval5.ll
--- Merging r127732 into '.':
U test/CodeGen/X86/stdarg.ll
U test/CodeGen/X86/fold-mul-lohi.ll
U test/CodeGen/X86/scalar-min-max-fill-operand.ll
U test/CodeGen/X86/tailcallbyval64.ll
U test/CodeGen/X86/stride-reuse.ll
U test/CodeGen/X86/sse-align-3.ll
U test/CodeGen/X86/sse-commute.ll
U test/CodeGen/X86/stride-nine-with-base-reg.ll
U test/CodeGen/X86/coalescer-commute2.ll
U test/CodeGen/X86/sse-align-7.ll
U test/CodeGen/X86/sse_reload_fold.ll
U test/CodeGen/X86/sse-align-0.ll
--- Merging r127733 into '.':
U test/CodeGen/X86/peep-vector-extract-concat.ll
U test/CodeGen/X86/pmulld.ll
U test/CodeGen/X86/widen_load-0.ll
U test/CodeGen/X86/v2f32.ll
U test/CodeGen/X86/apm.ll
U test/CodeGen/X86/h-register-store.ll
U test/CodeGen/X86/h-registers-0.ll
--- Merging r127734 into '.':
U test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll
U test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
U test/CodeGen/X86/avoid-lea-scale2.ll
U test/CodeGen/X86/lea-3.ll
U test/CodeGen/X86/vec_set-8.ll
U test/CodeGen/X86/i64-mem-copy.ll
U test/CodeGen/X86/x86-64-malloc.ll
U test/CodeGen/X86/mmx-copy-gprs.ll
U test/CodeGen/X86/vec_shuffle-17.ll
U test/CodeGen/X86/2007-07-18-Vector-Extract.ll
--- Merging r127775 into '.':
U test/CodeGen/X86/constant-pool-remat-0.ll
--- Merging r127872 into '.':
U utils/lit/lit/TestingConfig.py
U lib/Support/raw_ostream.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128258 91177308-0d34-0410-b5e6-96231b3b80d8
U include/llvm/Target/TargetLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86ISelLowering.h
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Transforms/Scalar/CodeGenPrepare.cpp
--- Merging r128194 into '.':
G lib/Transforms/Scalar/CodeGenPrepare.cpp
--- Merging r128196 into '.':
G lib/Transforms/Scalar/CodeGenPrepare.cpp
--- Merging r128197 into '.':
A test/CodeGen/X86/tailcall-returndup-void.ll
G lib/Transforms/Scalar/CodeGenPrepare.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@128200 91177308-0d34-0410-b5e6-96231b3b80d8
--- Merging r127350 into '.':
D test/CodeGen/X86/2009-03-11-CoalescerBug.ll
--- Merging r127351 into '.':
A test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll
U test/CodeGen/X86/fold-pcmpeqd-2.ll
U lib/CodeGen/SimpleRegisterCoalescing.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127384 91177308-0d34-0410-b5e6-96231b3b80d8
testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.
Performance results:
roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated
john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES
Small compile time impact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127208 91177308-0d34-0410-b5e6-96231b3b80d8
bitcasts, which are really no-ops here. This fixes slowdowns on
MultiSource/Applications/aha and others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127031 91177308-0d34-0410-b5e6-96231b3b80d8
There was a previous implementation with patterns that would
have matched e.g.
shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
missing patterns for them.
Add a SIMD test subdirectory to hold tests for SIMD instruction
selection correctness and quality.
'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
- Allow i16, i32, i64, float, and double types, using the native .u16,
.u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.
Patch by Justin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
to accept the float type.
- Add appropriate test cases.
Patch by Justin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126636 91177308-0d34-0410-b5e6-96231b3b80d8
It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126568 91177308-0d34-0410-b5e6-96231b3b80d8
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible
It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
Limit the folding of any_ext and sext into the load operation to scalars.
Limit the active-bits trunc optimization to scalars.
Document vector trunc and vector sext in LangRef.
Similar to commit 126080 (for enabling zext).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126424 91177308-0d34-0410-b5e6-96231b3b80d8
registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126380 91177308-0d34-0410-b5e6-96231b3b80d8
