Owen Anderson
04b12a4cfb
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143162 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 22:53:10 +00:00
Jakob Stoklund Olesen
b0117eed84
Also set addrmode6 alignment when align==size.
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Previously, we were only setting the alignment bits on over-aligned
loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 22:39:16 +00:00
Jim Grosbach
55dabaa73a
ARM isel for vld1, opcode selection for register stride post-index pseudos.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 22:25:42 +00:00
Evan Cheng
824a70a384
Avoid partial CPSR dependency from loop backedges. rdar://10357570
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143145 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 21:21:05 +00:00
Kevin Enderby
55c4127134
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
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not depend on In32BitMode. Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode. rdar://9738584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143112 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 17:40:41 +00:00
Jim Grosbach
88484c0030
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
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rdar://10348844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 17:33:59 +00:00
Jim Grosbach
036a67d670
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
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rdar://10348584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 17:16:55 +00:00
Chad Rosier
6d64b3adab
A branch predicated on a constant can just FastEmit an unconditional branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 00:21:16 +00:00
Lang Hames
15701f8969
Rename NonScalarIntSafe to something more appropriate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 23:50:43 +00:00
Chad Rosier
8ff2664f2f
Add a TODO comment. FastISel works by parsing each basic block from the bottom
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up. Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle. This creates many more
opportunities for target specific fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143079 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 23:34:37 +00:00
Chad Rosier
ade620065d
Factor a little more code into EmitCmp, which should have been done in the first
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place. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 23:25:44 +00:00
Chad Rosier
75698f346f
Use EmitCmp in SelectBranch. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143076 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 23:17:28 +00:00
Chad Rosier
530f7cefd3
Factor out an EmitCmp function that can be used by both SelectCmp and
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SelectBranch. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143072 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 22:47:55 +00:00
Jim Grosbach
a581328ceb
Thumb2 ldr pc-relative encoding fixes.
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We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 22:22:01 +00:00
Rafael Espindola
66bf7430f5
Fixes an issue reported by -verify-machineinstrs.
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Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 21:16:41 +00:00
Jim Grosbach
758a519a22
ARM parse parenthesized expressions for label references.
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Partial fix for rdar://10348687.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 21:14:08 +00:00
Rafael Espindola
e840e88239
This commit introduces two fake instructions MORESTACK_RET and
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MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET
followed by a MOV respectively. Having a fake instruction prevents
the verifier from seeing a MachineBasicBlock end with a
non-terminator (MOV). It also prevents the rather eccentric case of a
MachineBasicBlock ending with RET but having successors nevertheless.
Patch by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 21:12:27 +00:00
Lang Hames
75757f9fd1
Make sure short memsets on ARM lower to stores, even when optimizing for size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143055 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 20:56:52 +00:00
Jim Grosbach
9c5edc00c4
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 17:28:15 +00:00
James Molloy
015cca6c08
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 08:53:19 +00:00
Bill Wendling
de39d86f26
Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 07:16:18 +00:00
Evan Cheng
f31151f34e
Revert part of r142530. The patch potentially hurts performance especially
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on Darwin platforms where -Os means optimize for size without hurting
performance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143002 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 01:17:44 +00:00
Bruno Cardoso Lopes
02dc51806e
Corrects previously incorrect $sp change in MipsCompilationCallback.
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The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned
Patch by Petar Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142930 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-25 17:30:47 +00:00
Jim Grosbach
399cdca4d2
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-25 00:14:01 +00:00
Dan Gohman
3e6157de57
Remove the Blackfin backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142880 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-25 00:05:42 +00:00
Dan Gohman
29074ccf6c
Remove the SystemZ backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 23:48:32 +00:00
Jim Grosbach
b36e03d987
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142877 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 23:40:46 +00:00
Jim Grosbach
5921675ff5
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 23:26:05 +00:00
Eli Friedman
5c89cb8cd6
Don't crash on variable insertelement on ARM. PR10258.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142871 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 23:08:52 +00:00
Evan Cheng
aed4952753
ARMConstantPoolMBB::print should print BB number.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 23:01:03 +00:00
Jim Grosbach
12431329d6
ARM assembly parsing and encoding for VLD1 w/ writeback.
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One and two length register list variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 22:16:58 +00:00
Jim Grosbach
10b90a9bbf
ARM refactor am6offset usage for VLD1.
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Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 21:45:13 +00:00
Eli Friedman
3f3f6b067c
Add support to the old JIT for acquire/release loads and stores on x86. PR11207.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 20:24:21 +00:00
Owen Anderson
a7c98f58ea
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 18:04:29 +00:00
Dan Gohman
692c1d8535
Change this overloaded use of Sched::Latency to be an overloaded
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use of Sched::ILP instead, as Sched::Latency is going away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 17:55:11 +00:00
Dan Gohman
334190e47e
Remove the explicit request for "Latency" scheduling from MSP430,
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as the Latency scheduler is going away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 17:53:16 +00:00
Jim Grosbach
f8e74f816d
Thumb2 LDM instructions can target PC. Make sure to encode it.
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PR11220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 17:16:24 +00:00
Craig Topper
5679ec3b52
Add X86 SARX, SHRX, and SHLX instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 22:18:24 +00:00
Craig Topper
75485d6746
Add X86 RORX instruction
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 07:34:00 +00:00
Craig Topper
4fea38f773
Add X86 MULX instruction for disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142738 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-23 00:33:32 +00:00
Craig Topper
272895f0ab
Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142737 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-22 23:13:53 +00:00
Benjamin Kramer
1a2f9886a2
Move various generated tables into read-only memory, fixing up const correctness along the way.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-22 16:50:00 +00:00
Nadav Rotem
5b2bba6122
Fix pr11193.
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SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-22 12:39:25 +00:00
Bill Wendling
b8dcb314f7
The different flavors of ARM have different valid subsets of registers. Check
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that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-22 00:29:28 +00:00
Jim Grosbach
224180e81b
Assembly parsing for 4-register sequential variant of VLD2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 23:58:57 +00:00
Jim Grosbach
4661d4cac3
Assembly parsing for 2-register sequential variant of VLD2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db
Assembly parsing for 4-register variant of VLD1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056
Assembly parsing for 3-register variant of VLD1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 18:54:25 +00:00
Owen Anderson
7784f1d2d8
Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 18:43:28 +00:00