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5271 Commits

Author SHA1 Message Date
Tanya Lattner
db28247522 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 21:44:54 +00:00
Chad Rosier
871f664093 Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 19:59:50 +00:00
Stuart Hastings
1f2cb9824d An imminent fix to the x86_64 byval logic will expose a flaw in the 
x86_64 sibcall logic.  I've filed PR9943 for the sibcall problem, and
this patch alters the testcase to work around the flaw.  When PR9943
is fixed, this patch should be reverted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 19:19:17 +00:00
Eli Friedman
5ceb66692e Force a triple on a couple of tests; we don't support fast-isel of ret on Win64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131540 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 17:16:37 +00:00
Stuart Hastings
11d26f109d Merge pmovzx test case into existing file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131539 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 17:02:04 +00:00
Justin Holewinski
657d1bed23 PTX: add flag to disable mad/fma selection 
Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 15:42:23 +00:00
Tanya Lattner
2a8eb722c7 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 06:42:21 +00:00
Eli Friedman
28b42afcb8 Make some of the fast-isel tests actually test fast-isel (and fix test failures). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 00:00:10 +00:00
Stuart Hastings
ca1ef48585 X86 pmovsx/pmovzx ignore the upper half of their inputs. 
rdar://problem/6945110


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131493 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 22:13:31 +00:00
Tanya Lattner
c81c9709ef vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 20:48:40 +00:00
Galina Kistanova
416b7117b7 Move test for appropriate directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 19:06:43 +00:00
Eli Friedman
19515b4e52 Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. 
This is r131438 with a couple small fixes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131474 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 18:29:03 +00:00
Eli Friedman
c93943b6fe Back out r131444 and r131438; they're breaking nightly tests. I'll look into 
it more tomorrow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 02:36:59 +00:00
Eli Friedman
b70eac42e7 Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131444 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 00:39:14 +00:00
Evan Cheng
50ecb195e1 Add target triple so test doesn't fail on Windows machines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131439 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 00:15:58 +00:00
Eli Friedman
cdc9a20561 Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131438 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-17 00:13:47 +00:00
Jakob Stoklund Olesen
f5497fb1b4 Teach LiveInterval::isZeroLength about null SlotIndexes. 
When instructions are deleted, they leave tombstone SlotIndex entries.
The isZeroLength method should ignore these null indexes.

This causes RABasic to sometimes spill a callee-saved register in the
abi-isel.ll test, so don't run that test with -regalloc=basic.  Prioritizing
register allocation according to spill weight can cause more registers to be
used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131436 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 23:50:05 +00:00
Eli Friedman
57f4b03621 Remove dead code. Fix associated test to use FileCheck. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 21:28:22 +00:00
Eli Friedman
482feb33b2 Make fast-isel work correctly s/uadd.with.overflow intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131420 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 21:06:17 +00:00
Eli Friedman
2586b8f936 Basic fast-isel of extractvalue. Not too helpful on its own, given the IR clang generates for cases like this, but it should become more useful soon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131417 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-16 20:27:46 +00:00
Rafael Espindola
a3f88148e6 Don't produce a vmovntdq if we don't have AVX support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131330 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-14 00:30:01 +00:00
Rafael Espindola
3fa8283744 Make codegen able to handle values of empty types. This is one way 
to fix PR9900. I will keep it open until sable is able to comment on it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-13 15:18:06 +00:00
Stuart Hastings
88882247d2 Since I can't reproduce the failures from 131261, re-trying with a 
simplified version.  <rdar://problem/9298790>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-13 00:51:54 +00:00
Stuart Hastings
8ad145d729 Revert 131266 and 131261 due to buildbot complaints. 
rdar://problem/9298790


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-13 00:15:17 +00:00
Stuart Hastings
4c576ca9db Tweak 131261 (thumb2-cbnz.ll) to generate the intended cbnz. 
rdar://problem/9298790


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-13 00:10:03 +00:00
Stuart Hastings
5adc646380 Non-fast-isel followup to 129634; correctly handle branches controlled 
by non-CMP expressions.  The executable test case (129821) would test
this as well, if we had an "-O0 -disable-arm-fast-isel" LLVM-GCC
tester.  Alas, the ARM assembly would be very difficult to check with
FileCheck.

The thumb2-cbnz.ll test is affected; it generates larger code (tst.w
vs. cmp #0), but I believe the new version is correct.
rdar://problem/9298790


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131261 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-12 23:36:41 +00:00
Galina Kistanova
60bf5c3197 Correction. Use explicit target triple in the test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-12 21:55:34 +00:00
Evan Cheng
7139d35165 Re-enable branchfolding common code hoisting optimization. Fixed a liveness test bug and also taught it to update liveins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131241 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-12 20:30:01 +00:00
Stuart Hastings
007cfce220 Move this test to CodeGen/Thumb. rdar://problem/9416774 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 19:41:28 +00:00
Devang Patel
4243e67bd5 Identify end of prologue (and beginning of function body) using DW_LNS_set_prologue_end line table opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 19:22:19 +00:00
Nadav Rotem
42febc6e99 Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain). 
If there is a store after the load node, then there is a chain, which means
that there is another user. Thus, asking hasOneUser would fail. Instead we
ask hasNUsesOfValue on the 'data' value.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131183 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 14:40:50 +00:00
Nadav Rotem
4301222525 Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 08:12:09 +00:00
Rafael Espindola
41cdc16e73 Revert 131172 as it is causing clang to miscompile itself. I will try 
to provide a reduced testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 03:27:17 +00:00
Evan Cheng
7e20a574eb Add a late optimization to BranchFolding that hoist common instruction sequences 
at the start of basic blocks to their common predecessor. It's actually quite
common (e.g. about 50 times in JM/lencod) and has shown to be a nice code size
benefit. e.g.

        pushq   %rax
        testl   %edi, %edi
        jne     LBB0_2
## BB#1:
        xorb    %al, %al
        popq    %rdx
        ret
LBB0_2:
        xorb    %al, %al
        callq   _foo
        popq    %rdx
        ret

=>

        pushq   %rax
        xorb    %al, %al
        testl   %edi, %edi
        je      LBB0_2
## BB#1:
        callq   _foo
LBB0_2:
        popq    %rdx
        ret

rdar://9145558


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 01:03:01 +00:00
Rafael Espindola
6253c7ca60 Produce a __debug_frame section on darwin ARM when appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 21:04:45 +00:00
Justin Holewinski
f2453a3f2f PTX: add test cases for cvt, fneg, and selp 
Patch by Dan Bailey

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131128 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-10 14:53:13 +00:00
Benjamin Kramer
f51190b697 X86: Add a bunch of peeps for add and sub of SETB. 
"b + ((a < b) ? 1 : 0)" compiles into
	cmpl	%esi, %edi
	adcl	$0, %esi
instead of
	cmpl	%esi, %edi
	sbbl	%eax, %eax
	andl	$1, %eax
	addl	%esi, %eax

This saves a register, a false dependency on %eax
(Intel's CPUs still don't ignore it) and it's shorter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-08 18:36:07 +00:00
Jakob Stoklund Olesen
bf4e10f2f6 Emit a proper error message when register allocators run out of registers. 
This can't be just an assertion, users can always write impossible inline
assembly. Such an assembly statement should be included in the error message.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 21:58:30 +00:00
Justin Holewinski
ab0145d2a9 PTX: add PTX 2.3 language target 
Patch by Wei-Ren Chen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 11:40:36 +00:00
Eli Friedman
5e926ac651 Re-revert r130877; it's apparently causing a regression on 197.parser, 
possibly related to cbnz formation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 05:23:07 +00:00
Rafael Espindola
7af1a59382 Don't produce a __debug_frame. 
I tested both gdb on a bootstrapped clang and and the gdb testsuite on OS X (snow leopard)
and both are happy using __eh_frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-05 18:43:39 +00:00
Eli Friedman
23d3243e62 Avoid extra vreg copies for arguments passed in registers. Specifically, this can make MachineCSE more effective in some cases (especially in small functions). PR8361 / part of rdar://problem/8259436 . 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130928 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-05 16:53:34 +00:00
Jakob Stoklund Olesen
49b2803ec2 Prepare remaining tests for -join-physreg going away. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130893 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 23:54:59 +00:00
Jakob Stoklund Olesen
61396aebee Fix a batch of x86 tests to be coalescer independent. 
Most of these tests require a single mov instruction that can come either before
or after a 2-addr instruction. -join-physregs changes the behavior, but the
results are equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 23:54:51 +00:00
Dan Gohman
becfb889aa Give this test an explicit register allocator, so that it can work even if 
the default register allocator is changed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130883 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 23:14:02 +00:00
Bill Wendling
d29052bf26 SjLj EH could produce a machine basic block that legitimately has more than one 
landing pad as its successor.

SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130881 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 22:54:05 +00:00
Eli Friedman
baf717a08a Re-commit r130862 with a minor change to avoid an iterator running off the edge in some cases. 
Original message:

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130877 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 22:10:36 +00:00
Galina Kistanova
ff4f6eaf4e This test fails on ARM. The test shouldn't explicitly specify alignment (and alignment 4 is wrong) and requires hard-float. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 21:57:44 +00:00
Eli Friedman
24d4c9911e Back out r130862; it appears to be breaking bootstrap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130867 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 20:48:42 +00:00
Eli Friedman
49cec1d818 Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-04 19:54:24 +00:00