Commit Graph

102173 Commits

Author SHA1 Message Date
Christian Pirker
96a6e3bdee ARM: change parameter names of the ELFARMAsmBackend constructor
I removed the underscore at the beginning of the parameter name,
because of a comment from Tim.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205215 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 16:06:39 +00:00
Robert Khasanov
fe6e1e9b3c Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205214 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 16:01:38 +00:00
Daniel Sanders
775a94fd57 [mips] Fix use of uninitialized value reported by the sanitizer-x86_64-linux-bootstrap buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205213 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:58:58 +00:00
Eli Bendersky
416a0e993f Fix for PR19099 - NVPTX produces invalid symbol names.
This is a more thorough fix for the issue than r203483. An IR pass will run
before NVPTX codegen to make sure there are no invalid symbol names that can't
be consumed by the ptxas assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205212 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:56:26 +00:00
Tim Northover
93b3fcae28 ARM64: add extra patterns for scalar shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205209 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:46 +00:00
Tim Northover
812a174ba4 ARM64: add extra scalar neg pattern & tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205208 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:42 +00:00
Tim Northover
b35ffdff16 ARM64: add patterns for scalar sqdmlal & sqdmlsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205207 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:38 +00:00
Tim Northover
9542846832 ARM64: add more patterns for commuted fmsub operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205206 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:34 +00:00
Tim Northover
4417e07e39 ARM64: shuffle patterns around for fmin/fmax & add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205205 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:30 +00:00
Tim Northover
576c3f709f ARM64: add more scalar patterns for usqadd & suqadd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:26 +00:00
Tim Northover
13277a78bc ARM64: add more scalar patterns for reciprocal ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205203 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:22 +00:00
Tim Northover
8f93e159ed ARM64: add i64 scalar pattern for @llvm.arm64.abs
This will be used by the Clang front-end code for vabsd_s64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205202 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:46:17 +00:00
Daniel Sanders
e7c7ba0782 [mips] Implement missing relocations in the integrated assembler.
%got_hi, %got_lo, %call_hi, %call_lo, %higher, and %highest are now recognised
by MipsAsmParser::getVariantKind().

To prevent future issues with missing entries in this StringSwitch, I've added
an assertion to the default case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205200 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 15:15:02 +00:00
Daniel Sanders
857d651ba4 [mips] Remove R_MIPS_GOT which isn't used and shares the same number as R_MIPS_GOT16
Unlike my previous commit, don't try to remove the corresponding VK_Mips_GOT yet
even though it shares the same assembly text since that is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205196 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:47:41 +00:00
Daniel Sanders
1df2ed27dd Revert r205194 - [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.
There's a couple additional bits I missed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205195 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:34:36 +00:00
Daniel Sanders
1200528f17 [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:30:05 +00:00
Rafael Espindola
1c289ab6bb Capitalize the D in parseDirectiveGpDWord.
DWord seems to be the canonical way to camel case dword in llvm.

Thanks to Daniel Sander for noticing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205191 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:15:07 +00:00
Dmitri Gribenko
9982159d26 Remove unused private typedef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205190 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:14:13 +00:00
Tom Stellard
aa23732edd R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205188 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:01:56 +00:00
Tom Stellard
1f143aa3e9 R600/SI: Lower i64 SELECT by bitcasting to a vector type
This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered
using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205187 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:01:55 +00:00
Tom Stellard
1eaaa949f6 R600/SI: Return the correct index for VGPRs in getHWRegIndex()
The register index is stored in the low 8-bits of the encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205186 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:01:52 +00:00
Zoran Jovanovic
077aa54e4e Fixed issue with microMIPS JAL instruction.
Differential Revision: http://llvm-reviews.chandlerc.com/D3200


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205185 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 14:00:10 +00:00
NAKAMURA Takumi
6889086ba1 llvm/test/MC/Mips/mips64r2/valid-xfail.s: This REQUIRES asserts. Seems it doesn't fail with -Asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205182 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 13:30:02 +00:00
Daniel Sanders
5900e1db41 [mips] Added a full set of instruction test cases for all ISA's (but not ASE's).
Summary:
Where those ISA's are not currently supported, the test is run with the smallest
superset of that ISA.

Some instructions are valid but don't pass yet. These have been placed in the
valid-xfail.s's which will XPASS if _any_ instruction starts working.

The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3214

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205180 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 12:13:12 +00:00
Hal Finkel
65fafbb109 Look at shuffles of build_vectors in DAGCombiner::visitEXTRACT_VECTOR_ELT
When the loop vectorizer vectorizes code that uses the loop induction variable,
we often end up with IR like this:

  %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
  %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
  %i = add <2 x i32> %b2, <i32 2, i32 3>

If the add in this example is not legal (as is the case on PPC with VSX), it
will be scalarized, and we'll end up with a number of extract_vector_elt nodes
with the vector shuffle as the input operand, and that vector shuffle is fed by
one or more build_vector nodes. By the time that vector operations are
expanded, visitEXTRACT_VECTOR_ELT will not create new extract_vector_elt by
looking through the vector shuffle (to make sure that no illegal operations are
created), and so the extract_vector_elt -> vector shuffle -> build_vector is
never simplified to an operand of the build vector.

By looking at build_vectors through a shuffle we fix this particular situation,
preventing a vector from being built, only to be deconstructed again (for the
scalarized add) -- an expensive proposition when this all needs to be done via
the stack. We probably want a more comprehensive fix here where we look back
recursively through any shuffles to any build_vectors or scalar_to_vectors,
etc. but that can come later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205179 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 11:43:19 +00:00
Daniel Sanders
dd67fd636c [mips] Check emitted code for llvm.bswap.i32 on MIPS16/MIPS64 and llvm.bswap.i64 on MIPS16.
While reviewing r204163, I noticed that the MIPS16 test only checked for a .ent
directive and didn't actually check the code emitted. Fixed this and added a
check for llvm.bswap.i32 on MIPS64 at the same time.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205177 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 11:00:04 +00:00
Tim Northover
2357a94977 ARM64: fix a couple of signed/unsigned comparison warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205174 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 10:21:36 +00:00
Daniel Sanders
002ba57eb7 [yaml2obj] Add support for ELF e_flags.
Summary:
The FileHeader mapping now accepts an optional Flags sequence that accepts
the EF_<arch>_<flag> constants. When not given, Flags defaults to zero.

Reviewers: atanasyan

Reviewed By: atanasyan

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D3213

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 09:44:05 +00:00
Alexey Samsonov
285606027b Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() always initialize Size argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205171 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 07:59:33 +00:00
Yaron Keren
358d68d383 Correct OS conditionals following r204977 and r204978.
Previously, MinGW OS was Triple::MinGW and Cygwin was Triple::Cygwin
and now it is Triple::Win32 with Environment being GNU or Cygwin.
So,

  TheTriple.getOS() == Triple::Win32 
  
is replaced by

  TheTriple.isWindowsMSVCEnvironment()

and

  (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin)
  
is replaced by

  TheTriple.isOSCygMing()




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205170 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 07:59:14 +00:00
Craig Topper
379e2cf307 [C++11] Mark more classes in the X86 target as 'final'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205166 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 06:53:13 +00:00
Craig Topper
50f8308628 Mark a couple of the X86 target classes as final. Allows the compiler to de-virtualize some internal calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205165 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 06:22:15 +00:00
NAKAMURA Takumi
94821ac1eb ARM64CollectLOH.cpp: Tweak \param. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205162 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 01:10:26 +00:00
Chandler Carruth
2530cd31f4 [ARM64] Fix materialization of an fp128 zero immediate. There currently
is not a pattern to lower this with clever instructions that zero the
register, so restrict the zero immediate legality special case to f64
and f32 (the only two sizes which fmov seems to directly support). Fixes
backend errors when building code such as libxml.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205161 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 00:02:10 +00:00
Adam Nemet
cb1800772a [X86] Adjust cost of FP_TO_UINT v8f32->v8i32
There is no direct AVX instruction to convert to unsigned.  I have some ideas
how we may be able to do this with three vector instructions but the current
backend just bails on this to get it scalarized.

See the comment why we need to adjust the cost returned by BasicTTI.

The test is a bit roundabout (and checks assembly rather than bit code) because
I'd like it to work even if at some point we could vectorize this conversion.

Fixes <rdar://problem/16371920>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205159 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 18:07:13 +00:00
Stepan Dyatkovskiy
b173d9ee35 PR18929:
According to ARM assembler language hash symbol is optional before immediates.
For example, see here for more details:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473j/dom1359731154529.html



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205157 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 17:09:54 +00:00
Hal Finkel
111bcf9b59 Make use of previously generated stores in SelectionDAGLegalize::ExpandExtractFromVectorThroughStack
When expanding EXTRACT_VECTOR_ELT and EXTRACT_SUBVECTOR using
SelectionDAGLegalize::ExpandExtractFromVectorThroughStack, we store the entire
vector and then load the piece we want. This is fine in isolation, but
generating a new store (and corresponding stack slot) for each extraction ends
up producing code of poor quality. When we scalarize a vector operation (using
SelectionDAG::UnrollVectorOp for example) we generate one EXTRACT_VECTOR_ELT
for each element in the vector. This used to generate one stored copy of the
vector for each element in the vector. Now we search the uses of the vector for
a suitable store before generating a new one, which results in much more
efficient scalarization code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205153 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 15:10:18 +00:00
NAKAMURA Takumi
2afefa27b3 llvm/test/MC/ELF/nocompression.s: Loosen an expression to match "llvm-mc.EXE".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205148 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 14:04:00 +00:00
Hal Finkel
ee8e48d4c9 [PowerPC] Handle VSX v2i64 SIGN_EXTEND_INREG
sitofp from v2i32 to v2f64 ends up generating a SIGN_EXTEND_INREG v2i64 node
(and similarly for v2i16 and v2i8). Even though there are no sign-extension (or
algebraic shifts) for v2i64 types, we can handle v2i32 sign extensions by
converting two and from v2i64. The small trick necessary here is to shift the
i32 elements into the right lanes before the i32 -> f64 step. This is because
of the big Endian nature of the system, we need the i32 portion in the high
word of the i64 elements.

For v2i16 and v2i8 we can do the same, but we first use the default Altivec
shift-based expansion from v2i16 or v2i8 to v2i32 (by casting to v4i32) and
then apply the above procedure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205146 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 13:22:59 +00:00
Chandler Carruth
368a977298 [Allocator] Lift the slab size and size threshold into template
parameters rather than runtime parameters.

There is only one user of these parameters and they are compile time for
that user. Making these compile time seems to better reflect their
intended usage as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205143 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 12:07:07 +00:00
Chandler Carruth
0331a894cd [Allocator] Simplify unittests by using the default size parameters in
more places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205141 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 11:36:32 +00:00
Chandler Carruth
7c5042f86b [Allocator] Stop forward-declaring BumpPtrAllocator in a few places.
This is a necessary step to lifting some of its configuration into
template parameters rather than runtime parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205140 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 11:36:29 +00:00
Chandler Carruth
6da21c0e33 Don't mark the declarations of the TSan annotation functions as weak.
That causes references to them to be weak references which can collapse
to null if no definition is provided. We call these functions
unconditionally, so a definition *must* be provided. Make the
definitions provided in the .cpp file weak by re-declaring them as weak
just prior to defining them. This should keep compilers which cannot
attach the weak attribute to the definition happy while actually
resolving the symbols correctly during the link.

You might ask yourself upon reading this commit log: how did *any* of
this work before? Well, fun story. It turns out we have some code in
Support (BumpPtrAllocator) which both uses virtual dispatch and has
out-of-line vtables used by that virtual dispatch. If you move the
virtual dispatch into its header in *just* the right way, the optimizer
gets to devirtualize, and remove all references to the vtable. Then the
sad part: the references to this one vtable were the only strong symbol
uses in the support library for llvm-tblgen AFAICT. At least, after
doing something just like this, these symbols stopped getting their weak
definition and random calls to them would segfault instead.

Yay software.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205137 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 11:20:25 +00:00
Chandler Carruth
1f408b1474 [ARM64] Fix a heap-use-after-free spotted by ASan.
StringRef::lower() returns a std::string. Better yet, we can now stop
thinking about what it returns and write 'auto'. It does the right
thing. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 09:08:07 +00:00
Tim Northover
bcf0c5fd73 ARM64: uncopy/paste helper function
It was doing functional but highly suspect operations on bools due to
the more limited shifting operands supported by memory instructions.

Should fix some MSVC warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205134 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 08:30:28 +00:00
Tim Northover
1eaafd7f38 ARM64: remove unused variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205133 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 07:35:48 +00:00
Tim Northover
e69ff5b01d ARM64: remove -m32/-m64 mapping with ARM.
This is causing the ARM build-bots to fail since they only include
the ARM backend and can't create an ARM64 target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205132 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 07:25:23 +00:00
Tim Northover
c31891e350 ARM64: override all the things.
Actually, mostly only those in the top-level directory that already
had a "virtual" attached. But it's the thought that counts and it's
been a long day.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205131 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 07:25:18 +00:00
Saleem Abdulrasool
b52cb5e0db Support: correct Windows normalisation
If the environment is unknown and no object file is provided, then assume an
"MSVC" environment, otherwise, set the environment to the object file format.

In the case that we have a known environment but a non-native file format for
Windows (COFF) which is used for MCJIT, then append the custom file format to
the triple as an additional component.

This fixes the MCJIT tests on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205130 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 07:19:31 +00:00
NAKAMURA Takumi
a60d50cb9f Suppress llvm/test/CodeGen/ARM64 for targeting pecoff. ARM64 is unaware of that.
FIXME: Could we support them?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205126 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-30 05:01:17 +00:00