Commit Graph

9869 Commits

Author SHA1 Message Date
Eric Christopher
c1a887d76d Partial code for emitting thread local bss data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 00:49:07 +00:00
Bob Wilson
492fd454ca Optimize away insertelement of an undef value. This shows up in
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:42:58 +00:00
Jim Grosbach
de70b1f9be Enable preserving debug information through post-RA scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:57:47 +00:00
Jim Grosbach
309d20c89c Fix the post-RA instruction scheduler to handle instructions referenced by
more than one dbg_value instruction. rdar://7759363


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:57:06 +00:00
Evan Cheng
e163168aab Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:42:23 +00:00
Devang Patel
461a646a03 Revert r104165.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:58:28 +00:00
Jakob Stoklund Olesen
d32e735ae6 Add support for partial redefs to the fast register allocator.
A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.

Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:36:05 +00:00
Devang Patel
f4ccaeaef9 There is no need to maintain InsnsBeginScopeSet separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:26:53 +00:00
Jakob Stoklund Olesen
7ebc4d63db Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:36:22 +00:00
Evan Cheng
211ffa1351 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:19:50 +00:00
Jakob Stoklund Olesen
3437352887 TwoAddressInstructionPass doesn't really know how to merge live intervals when
lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:08:00 +00:00
Bob Wilson
14b2141497 When expanding a vector_shuffle, the element type may not be legal and may
need to be promoted.  The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion.  This fixes part of pr7167.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104141 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 18:48:32 +00:00
Evan Cheng
0a942dbb1e Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:08:17 +00:00
Bob Wilson
417d1705bb Fix a crash when debugging the coalescer. DebugValue instructions are not
in the coalescer's instruction map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 23:19:42 +00:00
Jakob Stoklund Olesen
dcf7708ad9 Remember to update VirtRegLastUse when spilling without killing before a call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:20:09 +00:00
Evan Cheng
28dad2a5ca Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:31:17 +00:00
Jakob Stoklund Olesen
0eeb05c969 Properly handle multiple definitions of a virtual register in the same
instruction.

This can happen on ARM:

>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:10:50 +00:00
Evan Cheng
5012f9b825 Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 20:07:47 +00:00
Evan Cheng
27e4840e03 Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 20:03:28 +00:00
Jakob Stoklund Olesen
6a8d2c6119 Teach the machine code verifier to use getSubRegisterRegClass().
The old approach was wrong. It had an off-by-one error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104034 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:31:12 +00:00
Daniel Dunbar
3538c808f8 llc (et al): Add support for --show-encoding and --show-inst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:22:19 +00:00
Evan Cheng
a083988c8a FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104004 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 00:03:40 +00:00
Evan Cheng
c6dcce3ba5 Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:24:12 +00:00
Bill Wendling
53f7602b61 - Set the "HasCalls" flag after instruction selection is finished.
- Change the logic DisableFramePointerElim() to check for the
  -disable-non-leaf-fp-elim before -disable-fp-elim.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:09:50 +00:00
Eric Christopher
c6177a4531 More data/parsing support for tls directives. Add a few more testcases
and cleanup comments as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 22:53:55 +00:00
Evan Cheng
44bfdd3d78 Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 22:09:49 +00:00
Jakob Stoklund Olesen
b8acb7be80 Pull the UsedInInstr.test() calls into calcSpillCost() and remember aliases.
This fixes the miscompilations of MultiSource/Applications/JM/l{en,de}cod.
Clang now successfully self hosts in a debug build with the fast register allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:02:08 +00:00
Eric Christopher
423c9e3e58 Add some section and constant support for darwin TLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:02:07 +00:00
Evan Cheng
53c779bb3a Careful with reg_sequence coalescing to not to overwrite sub-register indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:57:12 +00:00
Jakob Stoklund Olesen
2997985b4c Remove debug option. Add comment on spill order determinism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103961 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:01:22 +00:00
Jakob Stoklund Olesen
aa4b0159da Avoid allocating the same physreg to multiple virtregs in one instruction.
While that approach works wonders for register pressure, it tends to break
everything.

This should unbreak the arm-linux builder and fix a number of miscompilations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 17:18:59 +00:00
Jakob Stoklund Olesen
f3ea06b108 Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 15:30:37 +00:00
Jakob Stoklund Olesen
548643c573 Extract spill cost calculation to a new method, and use definePhysReg() to clear
out aliases when allocating. Clean up allocVirtReg().

Use calcSpillCost() to allow more aggressive hinting. Now the hint is always
taken unless blocked by a reserved register. This leads to more coalescing,
lower register pressure, and less spilling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103939 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 15:30:32 +00:00
Zhongxing Xu
bae5210321 Remove unused member variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 09:47:55 +00:00
Jakob Stoklund Olesen
0c9e4f5f3f Only use clairvoyance when defining a register, and then only if it has one use.
This makes allocation independent on the ordering of use-def chains.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 04:50:57 +00:00
Jakob Stoklund Olesen
646dd7c899 Eliminate a hash table probe when killing virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 03:26:09 +00:00
Jakob Stoklund Olesen
ac3e529831 Execute virtreg kills immediately instead of after processing all uses.
This is safe to do because the physreg has been marked UsedInInstr and the kill flag will be set on the last operand using the virtreg if there are more then one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103933 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 03:26:06 +00:00
Jakob Stoklund Olesen
41e1401de5 Sprinkle superregister <imp-def> and <imp-kill> operands when dealing with subregister indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 02:49:21 +00:00
Jakob Stoklund Olesen
4b6bbe885d Now that we don't keep live registers across calls, there is not reason to go
through the very long list of call-clobbered registers. We just assume all
registers are clobbered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 02:49:18 +00:00
Jakob Stoklund Olesen
844db9cc6f Boldly attempt consistent capitalization. Functional changes unintended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 02:49:15 +00:00
Jakob Stoklund Olesen
e6aba83797 Spill and kill all virtual registers across a call.
Debug code doesn't use callee saved registers anyway, and the code is simpler this way. Now spillVirtReg always kills, and the isKill parameter is not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 02:07:32 +00:00
Jakob Stoklund Olesen
01dcbf8507 Reduce hashtable probes by using DenseMap::insert() for lookup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103926 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 02:07:29 +00:00
Jakob Stoklund Olesen
6fb69d85e9 Make MBB a class member instead of passing it around everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 02:07:22 +00:00
Evan Cheng
ad6c5a20ba Yes, if the redef is a copy, update the old val# with the copy. But make sure to clear the copy field if the redef is not a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 01:47:47 +00:00
Dale Johannesen
8d908ebd19 Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.
The implementation in LegalizeIntegerTypes to handle this as 
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people.  Use this implementation only
when it is safe.  This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)

Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.

7885399, 5901940.  This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 18:51:12 +00:00
Dale Johannesen
789955127e Improve assertion messages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103882 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 18:38:02 +00:00
Chris Lattner
87565c1d77 improve portability to systems that don't have powf/modf (e.g. solaris 9)
patch by Evzen Muller!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 17:10:24 +00:00
Chandler Carruth
2c13ab2bb8 Fix an GCC warning that seems to have actually caught a bug (!!!) in
a condition's grouping. Every other use of Allocatable.test(Hint) groups it the
same way as it is indented, so move the parentheses to agree with that
grouping.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 10:23:23 +00:00
Jakob Stoklund Olesen
1e03ff4243 Calculate liveness on the fly for local registers.
When working top-down in a basic block, substituting physregs for virtregs, the use-def chains are kept up to date. That means we can recognize a virtreg kill by the use-def chain becoming empty.

This makes the fast allocator independent of incoming kill flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103866 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 06:09:08 +00:00
Evan Cheng
61d531066d A partial re-def instruction may be a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 01:35:44 +00:00