Commit Graph

116 Commits

Author SHA1 Message Date
Bill Wendling
ab55ebda1c Redo the arithmetic with overflow architecture. I was changing the semantics of
ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.

Similar for SUB and MUL instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60915 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-12 00:56:36 +00:00
Bill Wendling
74c3765291 Add sub/mul overflow intrinsics. This currently doesn't have a
target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60800 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-09 22:08:41 +00:00
Nick Lewycky
6ecf5ce3e3 Fix typo, psuedo -> pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60651 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-07 03:49:52 +00:00
Dan Gohman
15511cf166 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 18:15:48 +00:00
Bill Wendling
9f24874f2e Reapply r60382. This time, don't mark "ADC" nodes with "implicit EFLAGS".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60385 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-02 00:07:05 +00:00
Bill Wendling
e3b3c00454 Temporarily revert r60382. It caused CodeGen/X86/i2k.ll and others to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60383 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-01 23:44:08 +00:00
Bill Wendling
a047bcacf2 - Have "ADD" instructions return an implicit EFLAGS.
- Add support for seto, setno, setc, and setnc instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60382 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-01 23:30:42 +00:00
Dan Gohman
c99da1348d Don't set neverHasSideEffects on x86's divide instructions, since
they trap on divide-by-zero, and this side effect is otherwise
unmodeled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59551 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-18 21:29:14 +00:00
Nate Begeman
110e3b3d1b Fix PEXTRQ encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58403 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-29 23:07:17 +00:00
Dan Gohman
63f97201dc Fun x86 encoding tricks: when adding an immediate value of 128,
use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 01:33:43 +00:00
Dan Gohman
74feef261a Define patterns for shld and shrd that match immediate
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17 01:23:35 +00:00
Chris Lattner
e563bbc312 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-11 22:08:30 +00:00
Dan Gohman
6d4b052579 Split x86's ADJCALLSTACK instructions into 32-bit and 64-bit forms.
This allows the 64-bit forms to use+def RSP instead of ESP. This
doesn't fix any real bugs today, but it is more precise and it
makes the debug dumps on x86-64 look more consistent.

Also, add some comments describing the CALL instructions' physreg
operand uses and defs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56925 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-01 18:28:06 +00:00
Dan Gohman
2662d55866 Mark CALL instructions as having a Use of ESP/RSP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56911 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-01 04:14:30 +00:00
Bill Wendling
056292fd73 Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 21:48:12 +00:00
Bill Wendling
9468a9b6be - Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-16 21:12:30 +00:00
Dan Gohman
f5aeb1a8e4 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-12 16:56:44 +00:00
Anton Korobeynikov
b84c1676f1 Reapply 55899: First draft of EH support on x86/64-linux
Now with fix, which prevents subtle codegen bug to trigger on darwin.
No fix for bug though, it's still there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55955 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-08 21:12:47 +00:00
Bill Wendling
a425e0073d Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin:
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55928 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-08 17:59:12 +00:00
Anton Korobeynikov
302affbc53 First draft of EH support on x86/64-linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55899 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-08 14:21:53 +00:00
Evan Cheng
b18ae3cb63 For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 08:54:22 +00:00
Evan Cheng
eb9f89287e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30 02:03:58 +00:00
Dale Johannesen
e00a8a2a2e Split the ATOMIC NodeType's to include the size, e.g.
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28 02:44:49 +00:00
Dan Gohman
7deb17108f Reinstate the x86-64 portion of r55190. When doing extloads into
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55422 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27 17:33:15 +00:00
Evan Cheng
e7321441ac Fix asm printing of MOVSDto64mr and MOV64toSDrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55300 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-25 04:11:42 +00:00
Bill Wendling
449416deb6 Reverting r55190, r55191, and r55192. They broke the build with this error message:
{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55200 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 20:51:05 +00:00
Dan Gohman
b4ae2da7e4 Anyext tweaks for x86. When extloading a value to i32 or i64, choose
instructions that define the full 32 or 64-bit value. When anyexting
from i8 to i16 or i32, it's not necessary to zero out the high
portion of the register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55190 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22 19:19:31 +00:00
Dan Gohman
0bfa1bfbff Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE
out of X86ISelDAGToDAG.cpp C++ code and into tablegen code.
Among other things, using tablegen for these things makes them
friendlier to FastISel.

Tablegen can handle the case of i8 subregs on x86-32, but currently
the C++ code for that case uses MVT::Flag in a tricky way, and it
happens to schedule better in some cases. So for now, leave the
C++ code in place to handle the i8 case on x86-32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55078 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 21:27:32 +00:00
Dale Johannesen
a99e38495f Add remaining 64-bit atomic patterns for x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55029 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 00:48:50 +00:00
Bill Wendling
5bf1b4eacd Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic.
Just expand it like the other X-bit sub_and_fetches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55023 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20 00:28:16 +00:00
Bill Wendling
108ecf3975 Add support for the __sync_sub_and_fetch atomics and friends for X86. The code
was already present, but not hooked up to anything.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55018 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 23:09:18 +00:00
Dale Johannesen
140be2dfb7 Add support for 8 and 16 bit forms of __sync
builtins on X86.

Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54999 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-19 18:47:28 +00:00
Dan Gohman
e3d920699c Re-enable elimination of unnecessary SUBREG_TO_REG instructions in
LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54444 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-07 02:54:50 +00:00
Dan Gohman
8a1510d192 Re-introduce the 8-bit subreg zext-inreg patterns for x86-32,
this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54418 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-06 18:27:21 +00:00
Dan Gohman
165660e417 xchg does not modify FLAGS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54411 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-06 15:52:50 +00:00
Dan Gohman
11ba3b1af6 Reapply r54147 with a constraint to only use the 8-bit
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.

Also, change several 16-bit instructions to use 
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54223 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-30 18:09:17 +00:00
Dan Gohman
7ba145b0b4 Revert 54147.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54148 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-29 01:02:18 +00:00
Dan Gohman
b1e8cad61e Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54147 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-28 22:18:25 +00:00
Mon P Wang
2887310630 Added MemOperands to Atomic operations since Atomics touches memory.
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-25 08:15:39 +00:00
Evan Cheng
601ca4b434 Enable two-address remat by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52701 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-25 01:16:38 +00:00
Bill Wendling
37a6134165 Add the "AsCheapAsAMove" flag to some 64-bit xor instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51761 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-30 06:47:04 +00:00
Dan Gohman
b4106170dd Add patterns for CALL32m and CALL64m. They aren't matched in most
cases due to an isel deficiency already noted in
lib/Target/X86/README.txt, but they can be matched in this fold-call.ll
testcase, for example.

This is interesting mainly because it exposes a tricky tblgen bug;
tblgen was incorrectly computing the starting index for variable_ops
in the case of a complex pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51706 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 21:50:34 +00:00
Anton Korobeynikov
aa57a7f7a1 Fix 80col violation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50654 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 17:08:59 +00:00
Anton Korobeynikov
6625eff8ec Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern),
but should work. Work is in progress, more models will follow


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50630 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-04 21:36:32 +00:00
Evan Cheng
94d7b02c5a Also LXCHG64 -> XCHG64rm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49948 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-19 02:05:42 +00:00
Evan Cheng
7e03280b53 - Fix atomic operation JIT encoding.
- Remove unused instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49921 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-18 20:55:36 +00:00
Evan Cheng
e771ebd7a3 Allow certain lea instructions to be rematerialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48855 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-27 01:41:09 +00:00
Arnold Schwaighofer
4fe3073cfb Don't loose incoming argument registers. Fix documentation style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48545 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-19 16:39:45 +00:00
Christopher Lamb
c929823525 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16 03:12:01 +00:00
Evan Cheng
da47e6e0d0 Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15 00:03:38 +00:00
Evan Cheng
172b794cd5 Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48360 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-14 07:39:27 +00:00
Christopher Lamb
6634e26aa1 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-13 05:47:01 +00:00
Evan Cheng
4499e495ea Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 19:31:26 +00:00
Christopher Lamb
3feb0170a8 Allow insert_subreg into implicit, target-specific values.
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 06:12:08 +00:00
Andrew Lenharth
a76e2f0331 x86-64 atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47903 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-04 21:13:33 +00:00
Chris Lattner
d0ba2a9c14 Compile x86-64-and-mask.ll into:
_test:
	movl	%edi, %eax
	ret

instead of:

_test:
        movl    $4294967295, %ecx
        movq    %rdi, %rax
        andq    %rcx, %rax
        ret

It would be great to write this as a Pat pattern that used subregs 
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47658 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 05:47:54 +00:00
Nate Begeman
cdd1eeca2c SSE4.1 64b integer insert/extract pattern support
Move formats into the formats file


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47035 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-12 22:51:28 +00:00
Evan Cheng
be3bf42331 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
Nate Begeman
63ec90a6a8 SSE 4.1 Intrinsics and detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
Evan Cheng
0d9e976ad2 Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results.
Status: This only works for direct calls, and only the caller side is done. Disabled for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46527 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-29 19:34:22 +00:00
Duncan Sands
f9c98e650d The last pieces needed for loading arbitrary
precision integers.  This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on.  While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46280 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-23 20:39:46 +00:00
Chris Lattner
f9b3f37abc remove xchg and shift-reg-by-1 instructions, which are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45870 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-11 18:00:50 +00:00
Evan Cheng
90e9d4e013 Rename Int_CVTSI642SSr* to Int_CVTSI2SS64r* for naming consistency and remove unused instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45861 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-11 07:37:44 +00:00
Chris Lattner
a731c9fac9 more flags set right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45860 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-11 07:18:17 +00:00
Chris Lattner
ba7e756c22 Start inferring side effect information more aggressively, and fix many bugs in the
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 07:59:24 +00:00
Chris Lattner
36fe6d2f80 rename X86InstrX86-64.td -> X86Instr64bit.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45826 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 05:50:42 +00:00