Commit Graph

95 Commits

Author SHA1 Message Date
17a29a4847 [Hexagon] Pattern match a CTZ loop into a call to countTrailingZeros.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233192 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-25 15:36:57 +00:00
4ced9d418d Make the Hexagon ISelDAGToDAG pass set the subtarget dynamically
on each runOnMachineFunction invocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232874 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-21 03:12:59 +00:00
07121ea974 [Hexagon] Add support for vector instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232728 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-19 16:33:08 +00:00
83d2dd132d [Hexagon] Use pseudo-instructions for true/false predicate values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-18 19:07:53 +00:00
81f2a5d62b Revert "[Hexagon] Use pseudo-instructions for true/false predicate values"
This reverts r232650.

Missed a piece of code in the previous commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232656 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-18 18:50:06 +00:00
0c2e71367e [Hexagon] Use pseudo-instructions for true/false predicate values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232650 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-18 17:20:51 +00:00
f795de029a [Hexagon] Intrinsics for circular and bit-reversed loads and stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232645 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-18 16:23:44 +00:00
6cdcdfe4e4 Generate bit manipulation instructions on Hexagon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232577 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-18 00:43:46 +00:00
11f53b7797 Remove unneeded selection functions from HexagonISelDAGToDAG
- SelectSelect, and
- SelectTruncate



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232569 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-17 23:54:48 +00:00
d65f223529 Selection DAG preprocessing on Hexagon
Simplify: (or (select c x 0) z)  ->  (select c (or x z) z)
          (or (select c 0 y) z)  ->  (select c z (or y z))



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232553 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-17 21:47:16 +00:00
42c951a74c Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
Summary:
But still handle them the same way since I don't know how they differ on
this target.

No functional change intended.

Reviewers: kparzysz, adasgupt

Reviewed By: kparzysz, adasgupt

Subscribers: colinl, llvm-commits

Differential Revision: http://reviews.llvm.org/D8204

Like for the PowerPC target, I've had to add 'i' to the constraint mappings in
order to pass 2007-12-17-InvokeAsm.ll. It's not clear why 'i' has historically
been treated as a memory constraint.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232480 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-17 14:37:39 +00:00
d57194fe94 Revert r232374: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
2007-12-17-InvokeAsm.ll fails on the buildbot but not on my own system. Will investigate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232376 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-16 14:21:22 +00:00
6ea2c6d718 [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
Summary:
But still handle them the same way since I don't know how they differ on
this target.

No functional change intended.

Reviewers: kparzysz, adasgupt

Reviewed By: kparzysz, adasgupt

Subscribers: colinl, llvm-commits

Differential Revision: http://reviews.llvm.org/D8204


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232374 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-16 13:54:19 +00:00
547ba56bd0 Recommit r232027 with PR22883 fixed: Add infrastructure for support of multiple memory constraints.
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break
anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate
Constraint_* values.

PR22883 was caused the matching operands copying the whole of the operand flags
for the matched operand. This included the constraint id which needed to be
replaced with the operand number. This has been fixed with a conversion
function. Following on from this, matching operands also used the operand
number as the constraint id. This has been fixed by looking up the matched
operand and taking it from there. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-13 12:45:09 +00:00
8faeecead0 Revert "r232027 - Add infrastructure for support of multiple memory constraints"
This (r232027) has caused PR22883; so it seems those bits might be used by
something else after all. Reverting until we can figure out what else to do.

Original commit message:

The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232093 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 20:09:39 +00:00
7b110fe366 Remove unused complex patterns for addressing modes on Hexagon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232057 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 16:44:50 +00:00
67f6425792 Add infrastructure for support of multiple memory constraints.
Summary:
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8171


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232027 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 11:00:48 +00:00
55d4acbaf2 Fix build break introduced in r231992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231996 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 00:49:13 +00:00
9a062b62a7 Eliminate constant-extender profitability checks from Hexagon isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231992 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 00:19:59 +00:00
ffc2de43d9 [Hexagon] Reapply r231699. Remove assumption that second operand is an immediate when checking if A2_tfrsi is combinable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231710 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 21:48:13 +00:00
c2d30aebf3 [Hexagon] Reverting r231699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231703 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 21:19:02 +00:00
8c2919a34e [Hexagon] Updating constant set to simpler versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231699 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 20:33:12 +00:00
d913d9d2c3 MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line with countTrailingZeros
Update all callers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228930 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-12 15:35:40 +00:00
916b91acf1 [Hexagon] Renaming A2_addi and formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228318 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 17:49:13 +00:00
243f011835 [Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228220 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:36:28 +00:00
1d75b286e6 [Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228184 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 20:38:01 +00:00
c3bbdbba2d Migrate HexagonISelDAGToDAG to setting a subtarget pointer during
runOnMachineFunction. Update all uses of the Subtarget accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227840 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-02 19:22:03 +00:00
4925c39604 [Hexagon] Deleting a lot of old variants of intrinsics and updating references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227338 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-28 18:29:11 +00:00
dc8beeba1b [Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as compatible with i32 rather than doing custom type conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226500 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-19 20:31:18 +00:00
42fa763380 [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226194 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-15 19:28:32 +00:00
419855bfeb [Hexagon] Replacing old version of convert and load f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226057 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 23:07:36 +00:00
0bd2ffae08 [Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
3dc54ee5a4 [Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:00:43 +00:00
d25cfdb649 [Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224949 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 19:42:14 +00:00
ffba450190 [Hexagon] Adding remaining post-increment instruction variants. Removing unused classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-26 19:31:46 +00:00
a46bee194d [Hexagon] Adding post-increment unsigned byte loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224867 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-26 19:12:11 +00:00
3c52b7b9f2 [Hexagon] Adding post-increment signed byte loads with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224866 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-26 18:57:13 +00:00
5dbd280542 [Hexagon] Adding doubleword load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 20:44:59 +00:00
3c3fc28384 [Hexagon] Reapplying 224775 load words.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224786 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 20:02:16 +00:00
6a9ef539c6 Reverting 224775 until mayLoad flag is addressed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224783 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 19:22:59 +00:00
5b7d5db23b [Hexagon] Adding word loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224775 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 18:06:56 +00:00
c9092d2829 [Hexagon] Adding signed halfword loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224774 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 17:25:57 +00:00
0ece0ce8cd [Hexagon] Adding unsigned halfword load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224772 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-23 16:42:57 +00:00
9c0a115fbe [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224735 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-22 21:40:43 +00:00
76be167773 [Hexagon] Adding classes and load unsigned byte instruction, updating usages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224730 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-22 21:20:03 +00:00
bdfe60c796 [Hexagon] Removing old variants of instructions and updating references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224612 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-19 20:29:29 +00:00
ea204e70fc [Hexagon] Removing old multiply defs and updating references to new versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224340 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-16 16:10:01 +00:00
015408c6b1 [Hexagon] Adding encoding information for sign extend word instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224026 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-11 16:43:06 +00:00
20856353b8 [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223821 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 20:23:30 +00:00
260731d108 [Hexagon] Adding word combine dot-new form and replacing old combine opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223815 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 19:23:45 +00:00